RU1784836C - Displacement measuring device - Google Patents

Abstract

The invention relates to measuring and control equipment and can be used in angular and linear displacement sensors operating in the phase shifter mode for measuring the displacements, speeds and position of moving elements of actuators of various types. The aim of the invention is to increase the accuracy of measurements and expand the functionality. When the phase shifter head is moved, the signals from its output go to the amplifier input and are converted into a sequence of pulses whose frequency is proportional to the movement of the head relative to the rulers. These signals are supplied to the counting input of the register, to the other input of which signals from the counter-timer are received. The code value in the register will change with the arrival of each subsequent pulse from the output of the phase shifter. As a result of subsequent signal processing, a code proportional to the movement of the head relative to the ruler will be generated at the output of the auxiliary counter. 2 ill. (L C

Description

The invention relates to measuring and control technology and can be used in angular and linear displacement sensors operating in the phase shifter mode, such as inductosyn, used to measure the displacements, speeds, or position of moving elements of various types of actuators.

A device for converting the speed of angular displacement into a code is known which comprises a generator, a frequency divider, a phase splitter, a phase shifter, a frequency multiplier and a comparison circuit, to the second input of which a generator output is connected.

A disadvantage of the known device for converting the speed of angular movement into code is the complexity of its hardware implementation due to the presence of two conversion channels, which requires additional elements for constructing the converter and reduces its reliability. In addition, due to the non-identical channel settings and the spread of parameters (phase instabilities of filters and zero organs) and in the presence of

with about

harmonics, the accuracy of the measurement of the displacement parameter, as well as possible failures in reverse mode, are impaired.

Closest to the invention in technical essence is a device for measuring displacements, comprising a phase shifter (inductosine linear displacement sensor), the windings of the head of which are connected to a sinusoidal voltage generator connected via a frequency divider to a pulse generator, an amplifier of the line, the input of which is connected to the output windings of the phase shifter line, and output to a frequency multiplier connected via a pulse converter with a reference channel.

A disadvantage of the known device for measuring displacements is the low accuracy of the measurement, due to the inertia of the phase-locked loop, frequency and phase distortions introduced by the low-pass filter, the presence of combination frequencies at the output of the phase detector, as well as the complexity of the conversion circuit and limited functionality.

The aim of the invention is to increase the accuracy of measurements by eliminating the error from instability of the frequency of the supply voltage and expanding functionality by providing the ability to measure the speed of movement.

This is achieved by the fact that the device for measuring displacements, comprising a phase shifter connected to its excitation winding circuit from a series-connected pulse generator, a frequency divider, a sinusoidal voltage former, an amplifier connected to the output of the signal winding of the phase shifter, is equipped with a timer counter, the first the input of which is connected to a pulse generator, the second to the second output of the frequency divider, by a register, the first input of which is connected to the output of the second amplifier, the second - to the output of the counter-timer, by the former of the logical unit, the first output of which is connected to the third input of the register, by an auxiliary counter, the first input of which is connected to the second output of the former of the logical unit, by an adder, the first input of which is connected to the first output of the register, the second to the third output a gel of a logical unit is formed, the third - with the first output of the auxiliary counter, four OR-NOT elements, four INE elements, the inputs of the first IL-NOT element are connected to the group of low-order bits in the output of the adder, the inputs of the second element OR are NOT connected to the high-order group

the adder output, the outputs of the first and second elements are NOT connected to the corresponding inputs of the first element AND, the output of which is connected to the first input of the second element AND, the second input

which is connected to the second output of the pulse generator, the output to the input of the fourth element OR-NOT and the first input of the third element AND-NOT, the high-order bit of the output of the adder is connected to the second

the input of the third AND-NOT element and the input of the third OR-NOT element, the output of the fourth OR-NOT element is connected to the first input of the fourth AND-NOT element, the second input of which is connected to the output of the third

of an OR-NOT element, the output is to the second input of the auxiliary counter., the third input of which is connected to the output of the third AND-NOT element, and the second outputs of the auxiliary counter and the second AND-NOT element

are the outputs of the device.

The alleged invention allows to apply the method of multiplying the frequency of the output signal of the phase shifter, based on the filling, for example,

a counter-timer operating in cyclic mode, synchronized with the frequency of the power supply, for a time equal to the period of the supply voltage of the excitation winding of the phase shifter.

 Therefore, if we choose the period of the output signal frequency for the measurement time interval, and the period of the supply voltage winding as the reference one, the magnitude of the displacement of the phase shifter head relative to the ruler will be unambiguously determined only by changing the frequency period of the phase shifter output signal:

450

(D

where p is the instantaneous phase of the output signal;

(о о - circular frequency of the current phase shifter;

X is the coordinate of the phase shifter head relative to the ruler;

A is the step of the ruler, within which the component of the instantaneous value, depending on the coordinate of the movement, changes by l,

When moving the phase shifter head relative to the ruler, the current phase

the output voltage of the ruler varies in proportion to its speed, respectively, the frequency of the output signal also changes

0)

dff dt

,,, We + TTdt

where o i is the instantaneous frequency of the output signal of the phase shifter.

Transforming equation (2), we can show that

Ј - & (., -.

(3)

where TI is the frequency period of the output signal of the phase shifter,

That is the period of the frequency of the supply winding of the phase shifter.

Since the period T0 of the supply voltage and the step A of the ruler are constant, therefore, the amount of displacement will only be determined by changing the period Tj.

The period T0 is filled with pulses, the number of which in each period takes values from 1 to N, as shown in the phase shift diagram of the output signal Isig. phase shifter with respect to the energizing winding of the Ivoz voltage supplying it. (figure 2) the number of these pulses for a period of time equal to the period T | output frequency will be equal

T T0 + ti + 1 - tj

where tt, tt-i is the number of pulses counted, for example, from the counter-timer in the previous and subsequent measurement period,

I is the sequence number of the measurement period Ti.

The magnitude of the displacement of the phase shifter head relative to the ruler, provided that

dx dt

DH Ti

and taking into account the expression (3.4) will be equal to

I AM

Dh

Ti

 TiT,

(tl + 1 - tl)

(6)

where from

DX A (tH-i-tO (7) i о

Denoting the initial and final position of the head of the phase shifter relative to the ruler by Xi and X2, we find the magnitude of the displacement of the head over n periods of measurement Ti. According to equation (7) it will be equal to:

X - X2 - Xi - i- Ј (ti + i - ti) 10T ° l 1

(8)

Since -zg- for a given phase wave

the value of the constant, then 15

4 p

R

X K 2 (tH-1 - ti) 1 1

(9)

twenty

where K is the constant phase shifter conversion.

The proposed device allows, depending on the direction of movement of the head of the phase shifter relative to the ruler, a fairly simple way to determine the sign of the direction of movement, as well as measure different movement parameters. Thus, the movements of the ruler relative to the head within the step of the ruler or within the entire length of the ruler can be measured, for example, using known code converters. which can also be displayed in the desired units of measurement using well-known metering devices. The position or movement within the ruler can be determined by counting the number of pulses taken from the output of the second element by an NAND integrating counter, and the movement speed by a digital frequency meter per unit time, thereby expanding the functionality of the device.

Figure 1 is a block diagram of a device for measuring displacements; Fig. 2 is a phase shift diagram of an output signal of a phase shifter relative to a voltage excitation winding supplying it.

The device for measuring displacements comprises a phase shifter 1 (inductance linear displacement sensor) consisting of a head 2 and a ruler 3, an amplifier 4, a sinusoidal voltage generator 5, a second amplifier 6, register 7,

 the adder 8, the auxiliary counter 9, the shaper 10 of the logical unit, the first and second elements 11, 12 AND L AND NOT, the first and second element 13, 14 AND NOT, the third element 15 OR NOT, the third and fourth

25

thirty

35

40

element 16, 17 AND-NOT, the fourth element 18 OR NOT, the pulse generator 19, the frequency divider 20 and the counter-timer 21.

A circuit from a series-connected pulse generator 19, a frequency divider 20, a sinusoidal voltage generator 5, an amplifier 4 is connected to the excitation winding of the phase shifter 1. A second amplifier 6 is connected to the signal winding of the phase shifter. The first input of the counter-timer 21 is connected to a pulse generator 19, and the second to the second output of the frequency divider 20. The first input of the register 7 is connected to the output of the second 6 amplifier, and the second to the output of the counter-timer 21.

The first input of the logical unit former 10 is connected to the third input of the register 7. The first input of the auxiliary 9 counter is connected to the second output of the logical unit former 10. The first input of the adder 8 is connected to the first output of the register 7, the second input with the third output of the logical unit former 10, the third with the first output of the auxiliary 9 counter. The inputs of the first element 11 are NOT connected to the group of low-order bits of the output of the adder 8, the inputs of the second element 12 are NOT connected to the group of the high-order bits of the output of the adder 8, and the outputs of these elements are connected respectively to the first and second input of the first element 13 AND NOT; the output of this element is connected to the first input of the second AND-NOT element 14, the second input of which is connected to the second output of the pulse generator 19, and the output is connected to the input of the fourth OR-NOT element 18 and the first input of the third AND-NOT element 16. The high-order bit of the output of the adder 8 is connected to the second input of the third element 16 AND-NOT and to the input of the third element 15 OR-NOT. The fourth element 18 OR-NOT with its output is connected to the first input of the fourth element 17 AND-NOT, the second input of which is connected to the output of the third element 15 OR-NOT, the output - to the second input of the auxiliary 9 counter. The third input of the auxiliary counter 9 is connected to the output of the third element 16 AND NOT. The second outputs of the auxiliary counter 9 and the output of the second NAND element 14 are the outputs of the displacement measuring device.

A device for measuring displacements operates as follows.

The pulses of a rectangular shape supplied to the input of the sinusoidal voltage generator 5 (Fig. 1) from the frequency divider 20 are converted by the generator 5 to a sinusoidal voltage, which

after filtering (and, if necessary, a phase shifter to obtain two sinusoidal voltages of equal amplitude, but shifted 90 relative to each other

email deg.) are fed through an amplifier 4 to the field windings of the head of phase shifter 1.

When power is supplied to the field windings, in the signal windings of line 3

0 EMF will be induced. The voltage taken from the windings of the line, carrying information about the phase shift, between the period T0 of the supply voltage and the period P - output signal of the line is input

5 of the second amplifier 6, where it is amplified and converted into a train of pulses whose frequency is proportional to the movement of the head relative to the ruler.

0 Pulses from the collector output of the transistor switch (not shown in the drawing) of the second amplifier are supplied to the clock-counting input C2 of register 7, made on the K155IR1 chip. On the front

5 to the front of these pulses and in the presence of logic 1 level at the control input V2 coming from logic unit 10, the information is entered into the register in parallel through the parallel inputs D1 ... D4 from the counter-timer 21.

Counter-timer 21 is a n-bit binary counter operating in a cyclic mode. With the arrival of

5 a frequency divider 20 of a clock pulse, the duration of which is equal to the period T0 of the supply voltage excitation winding, a pulse generated code is generated at the output of the counter-timer

0 arriving at the counting input of the counter-timer from the generator 19 pulses. Information from the counter-timer in parallel code is written to the triggers of register 7 for a period equal to period T (often 5 gs of the output signal of the phase shifter. The code at the output of the register is a temporary analogue of the head position relative to the ruler code mask.

The value of the code in register 7 will change with the arrival of each next pulse from the output of the phase shifter and with the supply of a new code from the counter-timer. When moving the head, the pulse width of the output signal of the phase shifter will be

5 changes as follows: with increasing pulse duration, the value of the register code will increase, and with decreasing pulse duration it will decrease. When the periods T0 of the supply voltage of the field winding and the period T | The voltage of the output signal of the phase shifter (the head is stationary) the same code will be written into the register.

At the moment of moving the head relative to the ruler with the arrival of a pulse of the measured signal between the register 7 and the auxiliary counter 9, the equilibrium of the codes recorded in them is established. The contents of the register in a four-bit parallel code are supplied to the inputs A1 ... A4 of the adder 8, executed on the chip K155IMZ, the inverted four-bit code from the output of the auxiliary counter is supplied to the inputs B1 ... B4 of this adder. Since these codes are equal in absolute value, their total value at the output of the adder is O, i.e. at the output of the adder in all its bits there will be 0, respectively, and at the input of the second element 14 AND-NOT there will be a zero level blocking the passage of pulses from the pulse generator 19 through the third and fourth element 16.17 AND-NOT to the input of the auxiliary counter,

With the arrival of the next pulse of the measured signal, depending on the direction of movement of the head relative to the ruler, a larger (smaller) code is recorded in register 7. If the register code exceeds (decreases) the code of the auxiliary counter, the output of the adder 8 in the high order will be O or 1, respectively. If the high order of the adder 1 is present at the output, the second and third elements 12, 15 will be OR NOT O, accordingly, the output of the first element 13 AND WILL NOT be 1. In this case, through the public key of the second element 14 AND NOT at the input of the fourth element 18 OR, and at the input of the third element 16 AND will NOT receive a train of pulses from the pulse generator 19. Since the third AND-NOT element 16 is opened with a subtraction, the code of the auxiliary counter will be reduced to equality with the register code.

If there is an adder O at the output of the high-order bit, the output of the first element 11 AND-NOT will be 1, which will allow the pulses to pass through the fourth element 17 AND-NOT with the addition of addition, increasing the code of the auxiliary counter to an equality with the register code. Therefore, depending on which input of the elements 16, 17 is NOT-open, it will be determined in sign of the direction of movement of the head relative to the ruler.

Thus, when moving the head relative to the phase shifter bar

auxiliary counter 9 as if catches up with register 7 and depending on the direction of movement and the magnitude of the phase shift between the supply voltage T0 of the field windings and the voltage of the output signal T | a phase shifter will be generated at the output of the auxiliary counter proportional to the movement of the head relative to the ruler.

The work of the register, adder and auxiliary counter-about the aggregate with the counter-timer can be represented on a concrete example as follows. When a clock pulse arrives from the second

6 amplifier in register 7 with a timer counter

21 some kind of code will be written, for example 0110

(decimal 6). In this case, the output

auxiliary counter 9 must be set to the inverse code equal to the code of register 7, namely - 1001 (6), otherwise, at least one logical 1 will be present in the output code of adder 8, which means that the output of the second element 14 is NAND ( Fig. 1) there will also be logic 1, which will allow the passage of pulses to the input of the auxiliary counter from the pulse generator 19. The passage of pulses through the AND-NOT element 14 will cease if a zero code is established at the output of the adder. This will happen if and only if the inverse code of the auxiliary counter is set at its inputs, which is equal to the register code (in fact, at the output of the auxiliary counter

counter, the inverse code will be set equal to the output code of the register already when power is applied to the circuit).

Indeed, when adding the register code 0110 and the auxiliary counter code 1001 (6), we get a code equal to 1111, and the transfer unit that goes to the Po input of the adder from logic unit 10 (chip K155LAZ), we get the code 0000 at the output of the adder.

If with the arrival of the next clock

pulse in the register is written a large code,

e.g. 0111 (7), then adding this

code with previously recorded code 1001 (6)

auxiliary counter and, taking into account the transfer unit, the code at the output of the adder will be 0001. In order for the code at the output of the adder to be zero, it is necessary to reduce the code of the auxiliary counter in this case by one. If a smaller code is written in the register, for example, 0101 (5), the code will be equal to:

0101 + 1001 + 1 1111

In this case, in order for the adder to have a zero code, add logical Г to the output code of the auxiliary counter, i.e. depending on the direction of movement of the head relative to the line of phase shifters, the code of the auxiliary counter will either decrease or increase. Moreover, an excess of the register code over the auxiliary counter code is taken as a positive movement. In this case, the high order of the output code of the adder will be logical O, and the output of the subtraction of element 16 AND-NOT (Fig. 1) will be logical 1, which, when it is fed to the counting input +1 of the auxiliary counter, executed on the K155IK7 chip, working in the mode of summing and subtracting, it will cause a transition from the logical O state to the logical 1 state at the counting input -1 of this counter, i.e. the auxiliary counter will switch from the summing mode to the subtracting mode. And, on the contrary, if there is a logical 1 in the high order of the adder's output code, the subtraction of the AND-NOT element 16 will result in a logical О, and at the output, the addition of the 17 AND-NOT element is logical 1, which will be fed to the inverting counting input -G auxiliary counter and will switch it from the subtraction mode to the addition mode.

It can be seen from the foregoing that, depending on which counting input n-1 or -1 is used to record information s of the counter, the inversion of the code at the output of the auxiliary counter is carried out automatically.

Claims (1)

The claims of the invention A device for measuring displacements, comprising a phase shifter connected to its excitation winding, a circuit of serially connected pulse generator, frequency divider, amplifier sinusoidal voltage driver, connected to the output of the signal winding of the phase shifter, a second amplifier, characterized in that, for the purpose of improving measurement accuracy by eliminating errors from instability in the frequency of the supply voltage and expanding functionality due to providing the ability to measure the speed of movement, it is equipped with a timer counter, the first input of which is connected to a pulse generator, the second to the second output of the frequency divider, a register, the first input of which is connected to the output of the second amplifier, the second to the output of the counter-timer, a logic unit shaper whose first output is connected to the third input of the register. an auxiliary counter, the first input of which is connected to the second output of the logical unit former, an adder, the first input of which is connected to the first output of the register, the second with the third output of the logical unit former, the third - with the first output of the auxiliary counter, four OR-NOT elements, the four elements AND NOT, the inputs of the first element OR NOT connected to the group of low order bits of the adder output, the inputs of the second OR-NOT element are connected to the group of high order bits of the adder output, the outputs of the first and second OR-NOT elements are connected to the corresponding inputs of the first AND-NOT element, the output of which is connected to the first input of the second AND-NOT element, the second input of which is connected to the second output of the generator, the output - to the fourth input of the fourth OR-NOT element and the first input of the third AND-NOT element, senior bit d the output of the adder is connected to the second input of the third AND-NOT element and the input of the third OR-NOT element, the output of the fourth OR-NOT element is connected to the first input of the fourth AND-NOT element, the second input of which is connected to the output of the third OR-NOT element, the output is to the second entry in the auxiliary counter, a third input connected to the output of the third AND-NO element and second outputs of the auxiliary counter, and second AND-devices are Nyo outputs.