RU168602U1 - DECODER LDPC - Google Patents

Abstract

The utility model relates to the field of digital information processing, namely to decoders LDPC (Low density parity check - codes with a low density of parity checks). The technical result of the utility model is the creation of an LDPC decoder with less hardware resources and, accordingly, at a lower cost due to the optimization of the parallel min-sum algorithm, namely, due to one calculation of the reliability from the verification vertex for symbolic vertices, with the only difference in switching these values for a symbol vertex, as well as due to one common adder in each symbol vertex. 5 ill.

Description

The utility model relates to the field of digital information processing, namely to LDPC decoders (Low density parity check - codes with a low density of parity checks), and can be used to decode information encoded by the LDPC code in various data transmission / reception systems.

LDPC codes relate to block coding, and are widely used in information transfer systems. These codes allow you to correct multiple errors in data blocks from a few bits to hundreds of kilobytes (increasing the data block leads to hardware difficulties).

Currently, these LDPC codes are widely used in several data transfer standards. Recent advances in microelectronics manufacturing technology allow for hardware-based implementation of coding (decoding) systems based on LDPC codes, which allows extremely close access to the Shannon border in terms of throughput.

As with any block code, the basis of decoding is the verification matrix. With large data lengths (tens to hundreds of kilobits), this matrix is huge, but the essence of LDPC codes is that the number of units in rows and columns is always no more than a certain number much smaller than the matrix dimension. As a rule, decoding is carried out using the Tanner graph constructed according to the verification matrix. There are several ways of decoding according to the reliability obtained by demodulating received data from a noisy channel. The most adapted way for a hardware implementation with minimal loss in corrective ability is the min-sum algorithm (minimum-sum). Depending on the application, there are parallel, serial and serial-parallel methods for implementing this algorithm. The greatest throughput is the algorithm implemented in a parallel way, that is, the probability exchange between the symbolic and test vertices of the Tanner graph. This implementation requires the most hardware resources.

Known decoder LDPC, described in the application US 2011/0239086 A1, which implements the min-sum algorithm. However, in it, on each edge from the test vertex to the character vertex, a message is calculated, which requires large hardware resources of the decoder. Similarly, a message unique to each vertex is computed from the symbolic vertex to the verification ones, which also requires large hardware resources of the decoder, and therefore increases its cost.

RU 2382493 describes a method for decoding LDPC codes in which the node of the verification vertex is optimized similarly to the claimed utility model in terms of computing two minima, however, there is no element for adjusting the message from the symbol vertex to the verification one. This means that in the symbolic vertex, unique messages are also calculated for each edge emanating from the vertex, which requires large hardware resources of the decoder, and therefore increases its cost.

Closest to the claimed utility model are the LDPC decoder and the method of its operation described in the patent CN 101188426 and selected as prototypes of the claimed utility model, which are similar to the method described in the patent RU 2382493, in terms of storing two minima, however, the values are stored in them FIFO buffers, which indicates a sequential mode of operation, and there is also no element for adjusting the message from the character vertex to the verification one, this indicates the expenditure of large hardware resources of the decoder from s symbolic peaks, and, accordingly, an increase in the cost of the decoder.

The objective of the claimed utility model is to create an LDPC decoder (Low density parity check - codes with a low density of parity checks) with less hardware resources and, therefore, with a lower cost, due to the optimization of the parallel min-sum algorithm, namely, due to one calculation reliability from the test vertex for symbolic vertices, with a difference only in the switching of these values for a symbolic vertex, as well as due to one common adder in each symbolic vertex. The min-sum algorithm is iterative, in it, at each iteration, the reliability originally received from the demodulator is recounted. Reliability calculated from the rule for a symbol vertex according to the Tanner graph (Fig. 1) comes from each test vertex. And, accordingly, on the contrary, reliability is calculated from each symbol vertex calculated according to the rule for the verification vertex.

The problem is solved by creating an LDPC decoder containing at least two common adders (516) with memory elements and at least two blocks (509) for searching two minima whose input is connected to the output of the adder (528) of the current symbolic vertex (501) and at least one input connected to at least one adder (539) of another symbol vertex (541), and the outputs are connected to inputs of memory elements (503), the outputs of which are connected to the zero and first inputs of the multiplexer (532 ), the selection input of which is connected to the output of the element memory (534) storing the value of the selection signal (510), and the output of the same memory element (534) is also connected to the input of the sign multiplexer (533), the zero and first inputs of which are connected to the outputs of the memory elements (503), configured to store the sign of the second and first (507, 506) minimum values of the output of the block for searching for two minima (509), and the output of the multiplexer (533) of the sign is connected to the input of the adder (523) modulo two, the second input of which is connected to the output of the memory element (503), configured to store a common mark (508) community and the output is connected to the input of the inverter (527), the output of which is connected to the input of the constant multiplexer (531), the output of which is connected to the first input of the multiplier (530), the second input of which is connected to the output of the multiplexer (532), while the output the multiplier (530) is connected to the first input of the adder (528), the output of which is connected to the input of the minimum search unit (509) and to the first input of the comparator (511), the second input of which is connected to the output of the multiplier (512), to the second input of which the module the first minimum (504) from the output of the search block mi maxima (509), and the first input receives a signal from the output of the multiplexer (513) of the constant, to the zero input of which the constant value 1 arrives, and to the first input - the constant value -1, the sign value of the first goes to the select input of this multiplexer (513) minimum (506), while the output of the comparator (511) is connected to the input of the memory element (534), to the input of the choice of the multiplexer (521) of the value and the input of the choice of the multiplexer (535) of the sign, to the zero and first input of which the signs of the second (507) and the first (506) minimum from the output of the minimum search block (509) at the same time, the output of the sign multiplexer (535) is connected modulo two to the first input of the adder (536), the second input of which receives the common sign value (508) from the output of the minimum search unit (509), and the adder output (536) modulo two is connected to the input of the choice of the multiplexer (522) of the constant, to the zero input of which the constant value 1 arrives, and to the first input - the constant value -1, while the output of the constant multiplexer (522) is connected to the first input of the multiplier (529), the second input of which connected to the output of the multiplexer (521) values to zero the first inputs of which the first (504) and second (505) minima come from the outputs of the minimum search unit (509), while the output (515) of the multiplier (529) is connected to the input of the common adder (516), the input of which is connected to the input of the decoder, and at least one more input is connected to the output of the multiplier (529) of the current test vertex (502), and the output of the common adder (516) is connected to the input of the memory element (524), the output of which is the output of the decoder and connected to the second input of the adder (528) . For a better understanding of the claimed utility model, its detailed description is given below. writing with the corresponding drawings.

FIG. 1. An example of Count Tanner.

FIG. 2. The message scheme from the symbolic vertex to the verification ones after initialization, made according to the utility model.

FIG. 3. The message scheme from the test vertex C2 to the symbolic D0 (a) and D3 (b), made according to the utility model.

FIG. 4. The message scheme from the symbolic vertex D1 to the verification ones C0 (a) and C1 (b), made according to the utility model.

FIG. 5. Functional diagram of the decoder (with message switching between test and symbol vertices), made according to the utility model.

Consider briefly the principle of operation of the claimed utility model (Fig. 2-4). Decoding according to the min-sum algorithm begins with the initialization of the memory elements of symbolic vertices with the values of the a priori likelihood ratio (201) coming from the demodulator (Fig. 2):

where U _n - a priori likelihood ratio of the received symbol n from the demodulator,

N is the length of the code word,

deg (n) - vertex degree - number of outgoing edges from a symbol vertex

- сообщение для конкретной проверочной вершины k_i (203) от текущей символьной вершины n (202).

- a message for a particular test vertex k _i (203) from the current symbolic vertex n (202).

Next, update the information coming from the test vertices (303), according to the following rule (Fig. 3):

where the function g (...) - determines the minimum modulo value with a common sign from all arguments, so that:

It is worth noting that among the arguments of the search function, the minimum value for a particular symbolic vertex (302) is missing, in fact, a message from this symbolic vertex. Thus, different messages about the minimum emanate from one test vertex to the symbolic vertices; therefore, the combinational logic cloud (305) is different for each outgoing edge (306) (Fig. 3).

Then, all symbolic vertices (402) are updated taking into account the received messages from all verification vertices (403) calculated according to expression (2):

In the next iteration, messages (404) from symbolic vertices to verification vertices are calculated depending on which verification vertex they follow:

Similar to messages from test vertices, messages (404) from symbolic vertices for a specific test vertex do not contain messages in their sum,

actually from this test peak. Thus, from one symbolic vertex to the verification ones, different messages about the sum come out, so the combinational logic cloud (405) turns out to be different for each outgoing edge (406) (Fig. 4).

Let us consider in more detail the embodiment of the inventive decoder shown in FIG. 5, and the method of its operation.

Due to the fact that for each edge from each test vertex, according to the Tanner graph, its own function of finding the minimum is necessary, the hardware resources will be extremely large. In the claimed utility model, this algorithm is optimized in order to reduce hardware resources.

If we consider the way messages from the check nodes (303) to character (302), according to the expression (2) to the top of the symbol n _i (302) it is necessary to find the minimum of all who come in to check node messages from the character of vertices except n _i. And so on, for the n _{i + 1} includes all messages except the messages from the n _{i + 1} (Fig. 3 a, b).

The first stage of optimization consists in determining two minimum (modulo) values from all incoming messages (518 and 519) from symbolic vertices, regardless of which symbolic vertices they are intended for, while significantly reducing hardware resources. The absolute values of the minima (504, 505), as well as the signs (506, 507) of these values are stored in memory elements (503). When distributing the message back to the symbolic ones, the current message from the symbolic vertex is taken into account (518): if it coincides with one of the selected minima taking into account the sign, then the other of the two minima for each vertex is selected for this vertex. At each iteration, both minima (504, 505), both minima of the minima (506, 507), and the common sign of all messages (508) arriving at the verification vertex (502) are stored in memory elements (503). The negative message signal is stored as follows:

then the common negative signal (508) of all incoming messages is calculated as follows:

where the operation ⊕ is addition modulo 2.

The selection signal (510) of one of the minima for the message from the test vertex to the symbolic one is formed at the output of the first comparator (511) based on the values found by the MINIMUM node (509):

Where

, (9)

, (9)

- the value from the output of the first sign multiplexer (513).

Thus, the message module (514) from the test vertex to the character is formed at the output of the second multiplexer (521) as follows:

and since the sign is formed from the common sign of all messages, excluding messages from the symbolic vertex, for which a message is generated at the output of the second comparator (522), excluding from the common sign the sign of the discarded minimum according to (10):

- the negativity signal generated at the output of the adder modulo 2 (523).

(520) от каждой проверочной вершины (502) согласно графу Таннера посылают на входы общего сумматора (516) символьной вершины (501), так что на его выходе формируют значение согласно (4):Messages thus generated

(520) from each test vertex (502), according to the Tanner graph, is sent to the inputs of the common adder (516) of the symbol vertex (501), so that the value according to (4) is generated at its output:

, которое после нескольких итераций сохраняют в элемент памяти

which after several iterations is stored in a memory element

(524), the output of which is the output of the decoder (525).

The second stage of optimization consists in the fact that in each symbol vertex (501) the total sum of all messages (520), according to the graph, from the verification vertices is stored, regardless of which of the verification vertices it is intended for. However, according to expression (5), for the verification vertex (502), the sum of messages from the verification vertices other than this verification vertex (502) is intended. In the circuit of FIG. 5 provides for the correction of the total amount for each of the test vertices from the considered symbol. Subtract from the total amount after the memory element (524) the message from this vertex, memorized in the previous step. All operations with the values of minima and signs stored in memory elements (503) are performed (min1_, min2_, neg1_, neg2_, neg_) similarly to expressions (8-11). An underscore before the index means that it is after the memory element (503). The negative sign (526) from the expression (12) is formed using the inverter (527) exactly the opposite:

Since it is necessary to subtract the message from the given vertex from the total amount, therefore, the sign of the message is changed and added up with the total amount, and the corrected message is received at the output of the adder (528).

The essence of the claimed utility model is to optimize the decoder circuit and the method of its operation, namely the use for each test vertex of one node (this node is indicated by the dashed line in Fig. 5) to search for minima (509) and memory elements (503) for all edges coming from of this test vertex (502) to symbolic (501) according to the graph. And, for each symbol vertex, one common adder (516) of all messages (520 and 515) from the verification vertices according to the Tanner graph and the memory element (524) (the node is marked with a solid line) are used, regardless of the edges emanating from this symbol vertex. A message switching scheme is required for each edge, however this scheme is easy to implement (highlighted in bold dot-and-dash).

Although the embodiment of the utility model described above was set forth to illustrate the present utility model, it is clear to those skilled in the art that various modifications, additions and replacements are possible without departing from the scope and meaning of the present utility model disclosed in the attached utility model formula.

Claims (1)

An LDPC decoder containing at least two common adders (516) with memory elements and at least two blocks (509) for searching two minima whose input is connected to the output of the adder (528) of the current symbolic vertex (501) and at least one more input is connected to at least one other adder (539) of another symbol vertex (541), and the outputs are connected to inputs of memory elements (503), the outputs of which are connected to the zero and first inputs of the multiplexer (532), whose selection input connected to the output of a memory element (534) storing the value of the selection signal (510), and the output of the same memory element (534) is also connected to the input of the sign multiplexer (533), the zero and first inputs of which are connected to the outputs of the memory elements (503), configured to store the sign of the second and first (507, 506) the minimum value of the output of the block (509) searching for two minima, and the output of the multiplexer (533) of the sign is connected to the input of the adder (523) modulo two, the second input of which is connected to the output of the memory element (503), configured to store a common character (508) messages, and the output is connected to the inverter input (527), in the output of which is connected to the input of the constant multiplexer (531), the output of which is connected to the first input of the multiplier (530), the second input of which is connected to the output of the multiplexer (532), while the output of the multiplier (530) is connected to the first input of the adder (528) whose output is connected to the input of the minimum search unit (509) and to the first input of the comparator (511), the second input of which is connected to the output of the multiplier (512), the second input of which receives the first minimum module (504) from the output of the minimum search unit (509) ), and the first input receives a signal from the output of the multiplexer (513), a constant value 1 arrives at the zero input, and a constant value -1 arrives at the first input, the value of the sign of the first minimum (506) is received at the input of the selection of this multiplexer (513), while the output of the comparator (511 ) is connected to the input of the memory element (534), with the input of the choice of the multiplexer (521) of the value and the input of the choice of the multiplexer (535) of the sign, to the zero and first input of which the signs of the second (507) and first (506) minima come from the output of the minimum search unit (509), while the output of the multiplexer (535) sign connected inen with the first adder input (536) modulo two, the second input of which receives the common sign value (508) from the output of the minimum search unit (509), and the adder output (536) modulo two is connected to the input of the multiplexer selection (522) of constant , at the zero input of which a constant value of 1 arrives, and at the first input, a constant value of -1, while the output of the constant multiplexer (522) is connected to the first input of the multiplier (529), the second input of which is connected to the output of the multiplexer (521), to zero and the first inputs of which come first (504) and a minimum (505) from the outputs of the minimum search unit (509), while the output (515) of the multiplier (529) is connected to the input of the common adder (516), the input of which is connected to the input of the decoder, and at least one more input is connected to the output a multiplier (529) of the current check top (502), and the output of the common adder (516) is connected to the input of the memory element (524), the output of which is the output of the decoder and connected to the second input of the adder (528).

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