RU10307U1 - DEVICE FOR CONTROLLING A PULSE SEQUENCE - Google Patents

Abstract

A device for monitoring a pulse sequence comprising an input and an output bus, three triggers, an I element, a clock bus and a counter, the first input of an And element connected to the inverse output of the second trigger, and the information input of the first trigger connected to the input bus of the device, characterized in that an interval bus, an OR-NOT element and three disambiguation elements are additionally introduced into it, while the first input of the first disambiguation element is connected to the input bus of the device, the output of the first trigger is connected from the second the input of the first element of ambiguity, the output of which is connected to the counting input of the counter, the input of which is set to "0" which is connected to the output of the element And, the second input of which is connected to the interval bus, as well as to the information input of the second trigger and the first input of the third element of ambiguity, output which is connected to the output bus of the device, and the second input of the third disambiguation element is connected to the output of the second disambiguation element, the first input of which is connected to the clock bus and to the synchronization inputs first, second and third flip-flops, the second input of the second disambiguation element is connected to the output of the OR-NOT element, the first input of which is connected to the information input of the third trigger and the corresponding counter output, while the second input of the OR-NOT element is connected to the inverse output of the third trigger.

Description

Device for monitoring the pulse sequence

The utility model relates to pulsed and computational technology and can be used in devices that monitor information processing equipment.

Devices for monitoring pulse sequences are known (see, for example, A device for monitoring a pulse sequence in accordance with AS No. 1177899, о 1403358, W 1064444, A device for detecting pulse loss in AS No. II32356 and others).

The closest in technical essence and function to the proposed utility model is a device for monitoring the sequence of pulses on.with. 1064444 authors N.N. Frolova, A.I. Lastochkina, a diagram of which is shown in figure 1.

The prototype device contains an input bus I, the first trigger 2, the first and second elements And 3 and 4, the second and third triggers 5 and 6, the fifth and sixth elements And 7 and 8, the first and second counters 9 and 10, the third, fourth and seventh elements AND II - 13, OR element 14, clock bus 15, output bus 16. If there are no errors in the controlled pulse sequence, the outputs of elements II - 14 and bus 16 have a logic zero level. If pulses disappear in a controlled sequence or when they appear to be false, or when a false constant signal such as false I or false pulses appears, the duration of which exceeds the pulse repetition period of the controlled sequence, at the outputs of the corresponding elements And II - 13, and therefore at the output of the element OR 14 and bus 16, an error signal appears in the form of a pulse (or voltage level) of a logical unit.

- / - I //// I

H 03 to 5/19

The disadvantage of the prototype device is the relatively low reliability of the control, since it does not generate an error signal when a number of individual faults occur. So, when the output of the element 14 is shorted to the common wire, there is always a voltage pull on the bus 16, which corresponds to the absence of errors in the controlled sequence (log.O). Shorting to the common wire of the outputs of elements II - 13 also leads to the failure to detect one or another type of distortion of the controlled sequences, since the malfunctions themselves are not detected.

The objective of the claimed utility model is to increase the reliability of control by performing the device according to the scheme, providing the detection of its own single faults.

The technical result achieved by the claimed utility model is to reduce equipment and increase the reliability of monitoring the correct functioning of processing equipment

information.

To achieve the technical result, in a device for controlling the sequence of shapes, containing the input and output buses, three triggers, an I element, a clock bus and a counter, the first input of the And element connected to the inverse output of the second trigger, and the information input of the first trigger connected to the input bus devices, an interval bus has been introduced, an OR element is NOT and three elements of unevenness, while the first input of the first element of discontinuity is connected to the input bus of the device, the second input to the output of the first the trigger, and the output is to the counting input of the counters of the chick, the zero input of which is connected to the output of the And element, the second input of which is connected to the interval bus, to the information input of the second trigger and to the first is the input of the third disambiguation element, the output of which is connected to the output bus device, and its second input is connected to the output of the second element of unevenness, the first input of which is connected to the clock bus and

with BXoflajHpf synchronization of the first, second and third triggers, the second input of the second ambiguity is connected to the output of the OR-NOT element, the server input of which is connected to the Tpetbero information input of the hour meter and the step meter, and the second is connected to the inverse of the third trigger.

The essential tsar Shak, distinctive from the prototype and necessary in all cases to which the requested object of legal protection applies, include all newly introduced elements and relations.

Figure 1 is a functional diagram of the prototype device. Figure 2 shows the functional scheme of the claimed useful

models. 7,

Fig. 3 shows temporary explanations of the operation.

utility model. ,.

The utility model contains input I and output 4 buses, the first 5, the second 7 and t |) U flip-flop, element And 8, clock bus 3, counter 9, shchig 2 intervals, element IL - NOT II, as well as the first b, second 12 and the third 13 elements of disambiguation. The first input. Element And 8 is connected to the inverse output of the second trigger 7, and the information input of the first trigger 5 is connected to the input bus I of the device; The first input of the first element is unequal, I would be connected to the input bus I of the device, the second input is to the input of the first trigger 5, and the output is to the counter -1th input of the counter 9, the installation input to which is connected to the output of the And 8 element, the second input of which is connected to the bus of 2 intervals, to the information input of the trigger 7 and to the first input of the third element H5 of ambiguity 13, the output of which is connected to the output bus 4 5 of the device, and its second input is connected to the output of the second element of ambiguity J2, the first input of which is connected to the clock bus 3 and with: synchronization inputs of the first 5, second - 7 and 11 || of this Yu triggers. Second input of the second-3

of the second disambiguation element 12 is connected to the output of the OR - NOT II element, the first input of which is connected to the information input of the third trigger Yu and the output of counter 9, and the second is connected to the inverse output of the third trigger Yu. The principle of the device is as follows. The controllable sequence arrives at the input bus I. Using trigger 5 and the first element of the ambiguity b, the edges and decays of the signals that are sent to the counting input of the counter 9 are extracted from it (in the form of short pulses). The signals specifying the monitoring interval are sent via the bus 2. Using trigger 7 and AND element 8, the edges of these signals are selected (in the form of short pulses), which are fed to the counter 9 to be set to 0. Thus, the counter counts the number of transitions from I to O (and vice versa) in the sequence being played at a given interval. Using the trigger U and the OR-NOT IT element, the decays of the signals coming from the L -th digit of counter 9 are extracted to the information input of trigger Yu. During proper operation, the signals on the interval bus and at the output of the IL-NOT II element are identical. The determination of this fact is carried out by the comparison unit, performed on the elements of disambiguation 12 and 13. As a control, a clock sequence is used. When the device is operating properly, the output of the discontinuity element 13 and on bus 4 has a clock sequence identical to the sequence received on bus 3. If the number of transitions from O to I and from I to O in the control interval does not correspond to the expression:, (I) ( where the lower limit of the monitoring interval is 2, and the upper one is chosen arbitrarily, based on the statistical parameters of the controllable sequence), an error signal is generated on the output bus in the form of a clock sequence distortion. Increasing the Reliability of obtaining the correct control result is achieved due to the fact that any single malfunction of the claimed device, as well as a violation of the conditions presented by the input (l) to the controlled sequence, is accompanied by a distortion of the clock sequence on bus 4.

The nature of the distortion of the clock sequence in violation, the condition defined by the expression (T) for P 2 shown in the timing diagrams of the operation of the device shown in Fig.Z. The value of P. determines the place of connection to the counter 9 of trigger Yu. So, with trigger Yu it is necessary to connect to the output of the second discharge of the counter (output 2), and at 2 - to the third (output 2). It follows that when the value / 1 is selected, the connection is made to the category of the counter, in which the degree of two is equal to / I.

Claims (1)

A device for monitoring a pulse sequence comprising an input and an output bus, three triggers, an I element, a clock bus and a counter, the first input of the And element connected to the inverse output of the second trigger, and the information input of the first trigger connected to the input bus of the device, characterized in that an interval bus, an OR-NOT element, and three disambiguation elements are additionally introduced into it, while the first input of the first disambiguation element is connected to the input bus of the device, the output of the first trigger is connected from the second the input of the first element of ambiguity, the output of which is connected to the counting input of the counter, the input of which is set to "0" which is connected to the output of the element And, the second input of which is connected to the interval bus, as well as to the information input of the second trigger and to the first input of the third element of ambiguity, output which is connected to the output bus of the device, and the second input of the third disambiguation element is connected to the output of the second disambiguation element, the first input of which is connected to the clock bus and to the synchronization inputs first, second and third flip-flops, the second input of the second disambiguation element is connected to the output of the OR-NOT element, the first input of which is connected to the information input of the third trigger and the corresponding counter output, while the second input of the OR-NOT element is connected to the inverse output of the third trigger.