NL8101825A - DEVICE FOR QUESTIONING AND CORRECTING A SERIAL DATA SIGNAL. - Google Patents

Description

ψ * * - * * mu 10.005 1 N.V. PHILIPS 'BULB FACTORIES IN EINDHOVEN.

"Device for interrogating and correcting a serial data signal" BACKGROUND OF THE INVENTION

The invention relates to a device for interrogating and correcting a serial data signal. A data signal has the properties that nominally at any time the signal has one of a finite set of values. The complete collection can contain, for example, 2, 3 or 4 elements. In reality, other signal values can also occur due to disturbances or finite edge steepnesses.

When questioning, discrimination also takes place and each requested value is reduced to an element of said collection.

10 This creates a series of polling information, for example polling bits. The aforementioned faults and finite edge steepnesses can also cause the set of poll information to contain erroneous elemental. In some cases, these erroneous elements can be repaired.

For example, it may be that additional information has been added to the data signal, for example by inserting additional information cells, as a result of which an error-correcting code is created. The addition of such extra information cells reduces the efficiency of the channel, which is measured in the amount of information per unit time (without counting said extra information). Under an information cell is meant the smallest logical unit of a data signal, ie the smallest time interval, from which the data information can be recovered a priori without the knowledge of the data information of one or more previous or next information cells there is required. In the case of bivalent information, an information cell contains at least one data bit. In the biphase code to be discussed later, an information cell is identical to the bit cell.

It is possible to add additional information to the signal for other purposes, for example to make the signal self-synchronizing (self-clocking). U.S. Patent No. 3,893,171 discloses an apparatus for interrogating and correcting a data signal constructed according to the MEM (modified frequency modulation) method. This signal has two nominal values 8101825 PHN 10.005 2 and embodies a series of information bits. The signal is interrogated twice per bit cell, and each interrogation then forms an interrogation bit.

The series of nominal interrogation bits consists of series of consecutively one, two or three "zeros", each separated by a single 5 "one". The cited patent takes advantage of the fact that the MEM method introduces some redundancy. Therefore, it is possible to designate a single combination of interrogation bits, namely two directly consecutive "1" signals, as an error. If these two "1" signals are flanked by "zeros" of unequal lengths, an unambiguous correction is possible. It has been discovered by the inventor of the present invention that an increase in the possibility of correction of errors can be achieved: with a single code several types of errors can then be corrected and, moreover, this method can be used with different codes.

15 SUMMARY OF THE INVENTION

It is an object of the invention to be able to correct a larger selection of errors in the interrogation values in order to obtain a sequence of correct interrogation values. For example, the redundancy built into the modulation and the codewords is used to correct errors in the interrogation values. The invention achieves the object by providing an apparatus for interrogating and correcting a data signal consisting of a contiguous series of information cells containing a continuous signal with a finite number of discrete nominal signal values and transitions. between said signal values which transitions have a nominal minimum distance and a nominal maximum distance from each other, characterized in that the device comprises: a. a synchronizing device for deriving and updating an actual synchronization period of said transitions; b. polling generator to control a signal current of said synchronization period to form a series of substantially equidistant interrogation signals with a nominal return time which is at most half of said minimum distance; c. a storage device for receiving and sequentially storing in order one of one of said finite number of nominal signal values discriminated interrogation value under the control of said series of 35 interrogation signals; 8101825 EHN 10.005 3 d. an operating device which is connected to said storage device cm, each time in synchronization with an interrogation signal, to receive a running selection of in each case at least five consecutive interrogation values of said sequence, which consecutive interrogation values contain at least one interrogation value above the number corresponding to the length of an interrogation information cell, and furthermore always under control of one of a first vocrafined number *> 1 of permissible combinations of said consecutive interrogation values generate an agreement signal of that particular combination, under control of one of a second predetermined number "yi of impermissible Combinations of said consecutive interrogation values generate a simulation signal in order each time with an impermissible combination a permissible combination of a third vocra-determined number of 1 in one interrogation value thereof, of permissible combinations of consecutive n to sin the interrogation values, and generate an exceedance signal under control of further impermissible combinations of said successive interrogation values; e. a deck to receive said ordered or simulated poll values and to reform a series of digital information therefrom; f. a second output connected to the decoder cm to a user device to deliver the decoded series of information.

In contrast, the known device uses only a single interrogation signal between two consecutive signal transitions that are the minimum minimum distance of one, and only two interrogation signals per information cell (the value 01 produces a data bit of a first logical value, the interrogation values 00 and 10 a data bit of the second logic value, the poll values 11 signal an error). Furthermore, with the known device, only a single erroneous interrogation pattern 30 can be corrected, namely two directly successive "1" signals flanked by series of zeros of different lengths. By applying the invention, it is possible to impose lower requirements on the error-correcting properties of the code, if used, than when the invention is not applied. Even errors can be corrected if the code itself has no error-correcting properties (and therefore no redundant information cells). It is a particular advantage of the invention that the additional 81 0 1 8 2 5 ^ _ ~ ~ ...... "" "........". - PHN 10.005 4 operating device receives a running selection of the interrogation values, the series length of this selection being greater than corresponding to the length of an information cell in combination with the property that at least two signal transitions between two at the nominal minimum distance * question points. Obviously, more complicated error patterns can be corrected the longer the sequence length of the selection received by the updater.

The related exceedance signal can be used in various ways, for example, to activate complicated error correction measures.

It is advantageous if said storage device is a shift register. For example, a corrected set of poll values, or a set of information values based thereon, can easily be formed based on a continuous selection of uncorrected set of poll values.

15 It will turn out that the corrected set of poll values is not. needs to be formed physically, but that sometimes the information values are derived directly.

It is advantageous if, for use with a divalent continuous signal with two permissible positions for a signal transition per bit cell, the interrogation generator is suitable for generating interrogation signals with a return time which is at most equal to 1/5 of the nominal length of a bit cell .. For many binary codes with self-synchronizing properties, for example, one interrogation value per bit cell can be corrected.

It is advantageous if said exceedance signal acts as an error signal and has a duration corresponding to the length of an information information cell. This way an uncorrectable / cell is correctly signaled.

HEADED DESCRIPTION VKN THE FIGURES

The invention is explained in more detail with reference to some figures.

Fig. 1 gives the nominal biphase code signal forms;

Fig. 2 shows a block diagram of a device according to the invention;

Fig. 3 shows a correction device when using a biphase code;

Fig. 4a, 4b give tables of the respective directions of interrogation values, with resulting conditions in the updating device; 8101825 * # EHN 10.005 5

Fig. 5 shows the nominal signal forms of a code with four signal levels, which is advantageous for use in an apparatus according to the invention.

DESCRIPTION OF A PREVENTION 5 FIG. 1 gives the nominal signal shapes of a biphase code.

The signal is bivalent. The bit cell is determined by the time interval between the two indicia 40 and 42. Signal transitions can occur on the boundary between two bit cells, namely if these bit cells contain the same information, so both a logic "0" or both a logic 10 "1". If the two successive bit cells contain different information, this signal transition is omitted. Furthermore, a signal transition of each bit cell is located in its center. The signal form 44 now indicates, for example, a logic "0", the signal form 46 a logic "1".

This is the so-called inverted biphase code which will be further used in the following description. The bit cells are all nominally the same length. The interval between two consecutive signal transitions is nominally at least half a bit cell and nominally at most one whole bit cell.

Fig. 2 shows a block diagram of a device according to the invention. The input signal arrives at input 110, for example, as a continuous signal according to the nominal shapes shown in FIG. 1. In practice, various deviations can occur.

For example, the edges of the signal transitions usually have a finite slope. If the input signal is interrogated just on such an edge, this can provide both a logic "0" and a logic "1" for the value of the interrogation bit. In addition, the location of the discrimination level between the values "O" and "1" may shift in time. Furthermore, the bit cell frequency may be subject to changes which are not detected immediately and external disturbances may also occur. Element 112 Can be synchronized to form a clock pulse sequence The synchronizer can be formed by an oscillator driven by the signal transitions in the center of the bit cells, the other signal transitions remaining inactive, for example, by having each received signal transition Put ircnostable irultivibrator in the active position.

This active position lasts slightly longer than the time corresponding to a half bit cell and blocks the next signal transition if it already arrives after a half bit cell. The transitions at the boundaries of the bit cells then remain blocked. The invention per se does not concern such a synchronization device. A series of clock pulses with a return time equal to the length of the bit-5 cells then appears on line 113. Element 126 is a frequency multiplier. On line 127 it gives interrogation pulses with a frequency that is five times higher than that on line 113. Line 127 is connected to the shift pulse input of shift registers 116 and 120. Under the control of a shift pulse shift register 116 stores the information binarized by discriminator 114. from 10 input 110 on. Element 118 is an update device. Optionally, it is also synchronized by the signals on line 127 as indicated. The updating device then detects each time pattern of interrogation values stored in shift register 116. If this is one of a collection correct. patterns nothing else happens, so that the accordion is signaled with this pattern. If the pattern is a non-correct pattern, but a correct pattern can be formed by changing one interrogation value (in this case invert), a "1" is stored in shift register 120. This is done at the interrogation value corresponding to the interrogation value to be inverted. bit position. Shift register 120 also receives the pulses on line 127. Element 122 is an EXCLUSIVE-OR gate: when shift register 120 issues a "1", the output bit of shift register 116 is inverted and under the control of a pulse on line 122 in data flip-flop 124 stored. Element 128 is a known decoder for the biphase code. The output bits appear on output 130.

The updating device 118 is also provided with an additional output 119. In the aforementioned cases (correct pattern or recoverable pattern) a logic "0" appears on this output. If the pattern could only be restored by changing two scan values, a logic "1" will appear on this output: this is the exceedance signal. In the description of the biphase code, it is often impossible to give an unambiguous correction for six interrogation values for two errors, and then this exceedance signal acts as an error signal. If redundant information bits are also present, errors can again be corrected, certainly if certain information bits are indicated by the error signal as being of doubtful nature. Such indication is discussed in more detail when dealing with FIG. 4a, 4b.

Next, it is discussed how to correct the 81 01 825 for EHN 10.005 7 code of FIG. 1 the use of the device according to the invention. From fig. 1 it appears that the nominally greatest time between two consecutive transitions is equal to the length of one bit cell. It is further assumed that the interrogation is done with a frequency that is five times the bit cell frequency. The properties of the code and those of the interrogation frequency now give the following characterizations to be fulfilled: a. There can be at most five interrogation points within a bit cell; b. if there are three interrogation points in one half of a bit cell, the other half of that bit cell contains two interrogation points; c. each half of a bit cell always contains at least two interrogation points; d. a high level in one half of a bit cell always leads to a low level in the other half of that bit cell and vice versa.

Suppose shift register 116 contains the following six poll values 15: 0 0 110 1 (the last "1" being the most recent). This set of poll values cannot be in accordance with the above condition c .; Furthermore, one of the interrogation values is known to be assumed to be located in a certain half of a bit cell: in this case, the fourth bit from the left lies in the first half of a bit cell. The following embodiment illustrates in more detail how each interrogation value is in particular processed in combination with the three preceding interrogation values and the two consecutive interrogation values. These six interrogation-25 bits then take place in shift register 116. Now, in the discussed example, the sequence 1-0-1 is inadmissible ♦ A modification can in principle take place to one of the following combinations, assuming that the case of one erroneous interrogation bit is more likely than the case of two or more erroneous interrogation bits.

Moreover, the comment would not be unambiguous if several interrogation bits could be disturbed.

1. 0 0 1 0 0 1: in this case, the 010 sequence is incompatible with condition c.

2. 0 0 1 1 1 1: in this case the order 1-1-1-1 is incompatible with condition d., Otherwise there would otherwise be four high poll values from one bit cell.

3. 0 0 1 1 0 0: this is a permissible combination. Filling the most 8101825 1 * PHN 10.005 8 right bit position of shift register with a simulation signal ("1") can later correct the error. The error can of course also be corrected directly in shift register 116.

Fatal errors may occur. For example, the pattern of interrogation values 010101 is always uncorrectable. Furthermore, it is possible that an inadmissible pattern can be corrected in two different ways, as will become apparent later.

In this connection, FIG. 3 a correction device in a second embodiment at a biphase code. The input information arrives at terminal 20. Input 24 again receives a clock pulse sequence with a frequency of five times the bit cell frequency. The shift register 22 corresponds to the elements 114 and 116 in FIG. 2. The element 26 is a dead memory in working device. The dead memory contains 2 = 128 address locations, whereby six address bits along line 23 are received from shift register 22. The address locations of memory 26 contain three bits. Each time under control of an element of the clock pulse sequence at input 24, the currently addressed word is read in memory 26 and its Information is stored in data register 30 with bit positions 32, 34, 36. Bit position 36 gives the decoded value of the information bit . This need only be known to the outside once every five interrogation bits, in this embodiment at the beginning of the second half of the bit cell. In the exemplary embodiment, in this bit position also at other interrogation positions than at the beginning of such a second half, an information that is irrelevant, for example "O", is always stored. The bit position 34 contains a signal value "1" if an uncorrectable error is detected and the information of bit position 36 thus has no relevance for the time being. This bit position 34 contains a signal value "0" if such an uncorrectable error is not detected. It is also possible in that case that the bit-30 position 36 contains incorrect information, but that it is not signaled that such an error occurred: after all, an error is only detected from an incorrect sequence of interrogation bits, and the interfered sequence may be admissible in itself The bit position 32 contains the information whether the relevant interrogation bit is in the first half or in the second half of a bit cell (this is the interrogation bit located in the fourth position to the right of shift register 22.) If bit position 32 contains a logic "O", it concerns the first half, if bit 8101825 25 10.005 9; ψ position 32 a logic " 1 ", it concerns the second half. For a user decoder 37 with data output 39, a rising edge at the output of stage 32 indicates that the new information bit is available at the output of stage 36 (unless an error has occurred. and, which is controlled by 5 stage 34). It has been found that the death memory 26 can be programmed to consider each interrogation bit in conjunction with neighboring bits and to decode this bit, correct and decode this bit, or signal an uncorrectable error. Via line 28, the bit position 32 provides an additional address bit for memory 26, so that the first and second half of a bit cell are treated differently. Furthermore, the circuit includes a forward reset flip-flop (RS-flipflqp) 54. If the signal from bit position 34 signals an error, flip-flop 54 is set to the "1" position by the leading edge of the signal qp line 58. Therefore the signal on line 56 becomes "0" and this acts as blocking signal for dead memory 28 and register 30 (ENABLE). Therefore, no further information appears on the outputs of register 30. The signal on line 58 further functions as (pulse-shaped) tester signal for the counter 50. So that the clock pulses qp can start counting its count input 60. When the counter has counted five clock pulses, an output transfer signal appears on line 52: this is applied to the blocking input 62 of counter 50, so that it counter for further counting remains blocked. In addition, flip-flop 54 is reset to the "0" position. Therefore, death memory 26 and register 30 are no longer blocked, but a series of further readings can take place.

The processing of the information of the three bit positions 32, 34, 36 in a user can take place in an appropriate manner. For example, the user may encode 37 a shift register two bits wide. Each time under the control of a clock pulse (supplied by stage 32), a data bit of stage 36 is written therein synchronously. The error bit from bit-30 position 34 is written directly because the first stage of the shift register has a differentiating input therefor: if bit position 34 indicates an error, it is automatically transferred independently of the phase relative to the infarmation cell. This error bit then functions as an indication to indicate an information bit as unreliable. This can, for example, simplify the correction in the case of an error-correcting code. However, such correction can be performed according to procedures known per se and will not be discussed further.

_____ 8101825 PHN 10.005 10

In this connection, FIG. 4a, 4b, the working device of FIG. 3 because they give the final reaction for every possible bit pattern. In FIG. 4a the first column gives the decimal value of a bit pattern, the second column gives the bit pattern written out.

5 The left-most bit is received first and the right-most bit is received last. Only six bits (as a running selection of the received information stream) are considered. In particular, FIG. 4a refers to cases where the third bit from the left is in the first half of a bit cell. Similarly, FIG. 4b for the 10 cases where the third bit from the left is in the second half of a bit cell. The serial data stream is queried five times (equidistant) per nominal bit cell period, while the signal transition at this biphase code (Fig. 1) is exactly in the middle of the bit cell.

In that case, the interrogation pattern "00011" for a data bit "O" is 1c exactly as probable as the interrogation pattern "00111".

The third column shows the result code of the updater; the digits of this code have in FIG. 4a has the following meanings: 0: the relevant polling bit ,. the fourth from the left (D). is still in the first half of the bit cell.

1: the respective interrogation bit is the first of the second half of the bit cell, and the data content of the bit cell is a "0" (transition to interrogation signal "1").

2: the relevant interrogation bit is the first of the second half

2S

of the bit cell, and the data content of the bit cell is a "1" (transition to interrogation signal "0").

3: The relevant polling bit is still in the first half of the bit cell and an uncorrectable error has occurred. 4: the relevant interrogation bit is the first of the second half of the bit cell, however an uncorrectable error has occurred, so that the data content of the bit cell cannot be determined.

If a one-bit correction is required, this bit position is provided with a cross. In some cases, a two-way error can be corrected by changing just one interrogation bit.

35 In Fig. 4b, the numbers have the following meanings: 0: the relevant interrogation bit is still located in the second half of the bit cell, 8101825 ESN 10.005 11 1: (2nd relevant interrogation bit is the first bit of the next bit cell, whose value is of course not yet specified, because that only happens at the transition from the first half to the second half.

5 3: the relevant interrogation bit is still located in the second half of the relevant bit cell, but an uncorrectable error has occurred.

4: The relevant polling bit is the first of the next bit cell, but an uncorrectable error has occurred.

It is clear that in FIG. 4b the result code "2" does not occur now. There are now a number of categories of cases. First, there are correct cases. These are formed from test patterns that both have the same number of interrogation bits in the first and second half of the bit cell If a sequence of bit-15 cells occur which yield all the patterns (11100), then cases a14 (Fig. 4a, case 14) a28, a57, b51, 539 are found. Such sequences were also found for combinations of the cartridges (11100) and (00011) and on the other hand also for combinations of the cartridges (11000) and (00111).

Secondly, there are patterns that change from a polling bit into a correct pattern (the corrected bit is crossed; crossed. For example, pattern a2 changes into correct pattern a3, a10 in a14, a26 in a24 b61 in b57, and so on.

Smooth patterns can change into a correct pattern by two different corrections. Thus, the pattern b5 is corrected to the correct patterns b1 and b7, respectively. The same applies to the patterns a17, a19, a25, a30, a33, a38, a44, a46, b13, b25, b29, b34, b38, b40, b50, b58. In the cpzet according to fig. 3 this has no consequences because the results in question always get the same Encodings.

30 There are also correct patterns that can change into another correct pattern by such correction. Such a correction is not taken into account on the assumption that "no error" is more likely than "one error".

There are also a number of cases that can be converted a priori in two ways into a correct pattern. In that case, the resulting code is determined by the previous pattern. For example, pattern 48 can be reached from 64. This means that the result code (O) is most likely __ 81018 2 5 't PHN 10.005 12: the code (2) is enclosed in parentheses, otherwise there would be two transitions between bit cell halves in successive interrogation positions. lie. The same applies to cases a15, a48, a55, b8, b16, b17, b46, b47, b55. Pattern 63 is irrelevant, because it cannot be reached (a1 and a33 have result code 0, b1 and b33 both result code 1). Furthermore, the choice is made: b60: result code 0, because the resulting (subsequent) patterns (b56, b57 then still give both result code 1.

b59 and b4: both result code 1 as a pendant to cases a4, a59.

Finally, the patterns b0 and b63 can be formed into a correct pattern in two ways. Thereby, the pattern 100000 can change into the correct pattern b32 (result code 9). Yet here, in accordance with the correct pattern b1, the result code is chosen as "1", because otherwise a continuous result code 0 could yield results. For case b32, result code bO is chosen because the resulting patterns nevertheless give result code "1". Also for patterns b30, b33, code "1" is chosen.

The error correction described above can be similarly used with other encodings, such as, for example, the Mil-20ler encoding, which contains fewer signal transitions. If more interrogation bits are considered together, a larger error correction capacity is also realized. Then, for example, two incorrect interrogation bits can be corrected or, as in the described embodiment, ignored, respectively. The pattern length of the 25 interrogation bits considered together may also extend further beyond an information cell or bit cell.

Fig. 5 shows the nominal signal forms of a code with four signal levels, respectively A, B, C, D. Each information cell contains two information bits. Each different information content of an information cell gives a different signal form. The length of an information cell is determined by the time interval between indicia 100 and 108, which time interval is divided by indicia 102, 104, 106 into three nominally equal parts. Within an information cell, the transitions can occur in three places, namely: 35 at position 102 from level B to level C and vice versa; at position 104 from level A to level D and vice versa? at position 106 from level B to level C and vice versa.

8101825 • s PHN 10.005 13

Furthermore, at the boundaries of the bit cells all possible.

transitions occur. The sixteen possibilities are indicated at the indications 100 and 108, respectively, by broken lines. The information loads of the infusion cells are indicated in each case. This code is requested with a frequency which is at least 8 times the information cell frequency. Nine interrogation signals are then attempted to generate a simulation signal. If the series of polling signals corresponds to an order of two of the signals of FIG. 5, and the fifth interrogation signal is the first of the second half 10 of an information cell, then a isolation signal for one of the four information values 00, 01, 10, 11 is provided. If that fifth interrogation signal is not (yet) the first of the second half of an information cell, a "wait" signal is generated. These same simulation and waiting signals, respectively, are formed if a correct pattern can be formed by a limited modification of the interrogation signals.

Such a modification that is permissible may, for example, involve a random change of one interrogation signal, or a limited change (for example, exchange of the pairs of signal levels A / B, C / D) of two interrogation values. In other cases, a 20 fput signal is then generated, which remains in effect for 8 times. Likewise, the invention can be applied to other encodings.

25 30 35 81 0 1 8 2 5 ^

Claims (4)

An apparatus for interrogating and correcting a data signal ... consisting of a contiguous series of information cells containing a continuous signal containing a finite number of discrete nominal signal values and transitions (40, 42, 44, 46) between said signal 5 values which transitions have a nominal minimum distance and a nominal maximum distance from each other, characterized in that the device comprises: a. A synchronization device for deriving and updating an actual synchronization period of said transitions; 10 b. a polling generator to form a series of substantially equidistant polling signals having a nominal return time which is at most half of said minimum distance, under the control of a signal current (24) from said synchronization period; c. a storage device (22) to receive and store in sequence qp one in one of said finite number of nominal signal values under the control of said series of 15 interrogation signals; d. an operating device (26) connected to said storage device cm to receive in each case in synchronization with a polling signal a running selection of at least five consecutive polling values of said sequence, which successive polling values contain at least one polling value above the number corresponding to the length of an information cell, and furthermore to generate an agreement signal of that particular combination, under the control of one of a first predetermined number> 1 of permissible combinations of said successive interrogation values, under the control of one of a second predetermined number> 1 of inadmissible combinations of said successive interrogation values generating a simulation signal 30 In order to obtain a permissible combination of a third predetermined number> 1 of admissible combinations of consecutive in a single interrogation value thereof, each time in an impermissible combination to simulate subsequent interrogation values, and generate an exceedance signal under control of further impermissible combinations of said successive interrogation values; e. a decoder (37) to receive said agreed or simulated interrogation values and reform a series of digital information therefrom; 8101825 PHN 10.005 15 f. a second output (39) connected to the decoder to deliver the decoded set of information to a user device. The device according to claim 1, characterized in that said storage device is a shift register. 5 Device as claimed in claim 1, characterized in that for use with a divalent continuous signal with two permissible positions for a signal transition per bit cell, the interrogation generator is suitable for forming interrogation signals with a return time which is at most equal to 1 / 5 of the nominal length of a bit cell. 10 Device as claimed in claim 1 #, characterized in that said exceedance signal acts as an error signal and has a duration corresponding to the length of an information cell. 15 20 i 25 30 35 8 101 825 ^