NL8100348A - METHOD AND DEVICE FOR PREVENTING ERRORS IN AN ERROR CORRECTING DECODE UNIT FOR PULSE CODE MODULATED SIGNALS - Google Patents

Description

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Method and apparatus for preventing errors in an error-correcting decoder for pulse code modulated signals.

The invention relates to a method and an apparatus for preventing errors in an error-correction decoding unit for pulse code modulated signals and in particular to such a method and device, which is particularly suitable for use in connection with a PCM signal processing device that receives PCM signals in a time-interleaved error correction code from one or two different sources of information.

Recently, digital techniques have been applied for the transmission and recording of audio signals. For example, a high-recording-density rotary head video tape apparatus can be used to record pulse code modulated (PCM) signals containing audio information. However, when a PCM-15 encoded signal is recorded and subsequently reproduced, there is the possibility that noise, interference, signal dropout, and the like may be present, thereby destroying some reproduced PCM signals. Such a loss of information can result in serious errors in the reproduced signal, thereby adversely affecting audio reproduction of sufficiently high quality.

In order to minimize this problem of signal loss, error correction codes have been proposed for use in encoding the PCM signals prior to recording or transmission. By using such error correction codes, reproduced or received erroneous PCM signals can be corrected or compensated to avoid the aforementioned adverse effect on the audio reproduction.

An advantageous error correction code proposed for such PCM signals is the so-called 8 1 00 34 8 -2- *. A time-interleaving code, some examples of which are described in the applicant's earlier US patent applications 86,677 / filed in the United States on October 19, 1979 / and no. 195,625 / filed in the United States on October 9, 1980. Generally, in the interlaced time-acting error correction code, multiple channels of PCM signals are displayed, each channel consisting of a sequence or series of consecutive PCM words. These multiple channels may come from an analog-to-digital converter, which is used to digitize an analog audio input signal, for example, a binaural signal. An information block is formed from one word in each channel, which words typically appear in word parallel format. These words appearing in parallel form are used to derive one or more error correction words, for example parity words. Then, each PCM word in the data block, as well as the error correction word (or error correction words) is delayed with an associated mutually different time delay, thereby effectively interleaving the PCI1 and error correction words. These time-interleaved words, which are present in word-parallel form, are simultaneously fed to an error detection word generator, for example, a cyclic redundancy code (CRC) generator to generate and output an error detection word. This error detection word is combined with the time interleaved PCM and error correction words to form a time interleaved transfer block. The time interleaved 3Ό transfer block can then be registered, transferred, or otherwise used.

When the time interleaving subject transfer block is displayed or received, the various interleaved words, together with the error detection word, are examined to determine whether an error is present in this particular transfer block. Error detection codes, for example the CRC code, are known to provide this error detection capability. If an 8100348 r -3 error is detected in this transfer block, all interleaved PCM and error correction words are identified as erroneous, regardless of whether any such word is indeed erroneous or correct. Then, these time interleaved identified PCM and error correction words are time interleaved to restore the original information block. If an interleaved PCM word has been identified as erroneous, it can be corrected using conventional error correction techniques, for example, by parity decoding, provided that none of the other words in the same block are erroneous. If the reconstructed interleaved block includes two error correction words, two erroneous PCM words contained in that interleaved block can be corrected. These said techniques are specifically described in the aforementioned patent applications of the present applicant.

By applying the aforementioned interweaving coding technique, effects as a result of a so-called burst error are minimized. The term "burst-20 error" generally denotes an error interval in which recorded or transmitted information is subject to signal failure, which interval extends over a sufficient period of time to include a number of time-interleaved transmission blocks. However, even if all of the PCM and error correction words in a number of time-interleaved transfer blocks are distorted when reconstructing the original interleaved transfer blocks, it is expected that generally only one word is formed in the reconstructed block. This means that the time-interleaved coding technique is effective for spreading a burst error across a large number of reconstructed blocks. Since, then, a single word in a reconstructed interleaved block is erroneous, such errors can be corrected or compensated for by conventional error correction or compensation techniques.

Advantageously, a PCM signal processing device provided with said interleaved interleaving time / encoding unit 8100348 ί * -4- can be used as an adaptation unit for quick and easy connection to a videotape device so that a conventional videotape can be used. device can be used to record pulse code modulated audio signals. It is also advantageous to use this type of encoding / decoding unit for receiving PCM signals from different sources. For example, the PCM decoder may be connected via a switching unit to the playback section of a videotape device or to the output of a PCM encoder. Depending on the switch state of the switch, interwoven transfer blocks are supplied to the decoder from one (the videotape device) to another (the PCM encoder) information source. Since the time blocks interleaved from both sources are of the same format, the decoder serves to decode the received transfer blocks, regardless of the specific source from which they originate, and to reconstruct the original audio signals. In many cases, the user of the device deems it desirable to switch from one source (eg, the videotape device) to another. During the switchover interval, which is finite, the decoder receives erroneous transfer blocks. If these erroneous transfer blocks are de-weaved in time, in accordance with the usual procedure, a number of de-interleaved blocks, starting with the first de-interleaved block at the start of the switchover interval, contain a number of PCM and / or error correction words, which are are from one source and other PCM and / or error correction words from the other source.

Furthermore, one or more of the words contained in those de-interleaved blocks are erroneous, since they are de-interleaved from those interleaving blocks supplied during the switching interval. If one of these PCM words in the interleaved block is erroneous, the decoder error correction unit will nevertheless attempt to operate in the usual manner and correct this erroneous PCM word.

However, the wrong word may come from 8100348

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-5- from one source / while other words present in this interwoven block come from the other source. Typically, the error correcting function attempts to reconstruct the erroneous PCM word by using the error correction word 5 in conjunction with the remaining non-erroneous PCM words. If all of these words come from the same source of information, there is no problem reconstructing the correct PCM word. However, when some of the words come from one source and another from the other source, there is no relationship between them, and the erroneous word cannot be reconstructed.

When the interleaved time-acting encoding / decoding unit of said type is used in the example just described, the error correction unit contained therein attempts to "correct" the erroneous PCM word, even though such " correction "cannot be performed. Therefore, the "corrected" word is erroneous and, when converted back into analog form and reproduced by means of, for example, a loudspeaker, results in an undesired sound. This noise is annoying and is preferably avoided.

Said undesired disturbing noises can be suppressed by simply performing a known suppression operation when switching from one information source to another; for this purpose, the switch must be detected. For example, an additional, special connection must be made with the video tape apparatus for deriving a control signal therefrom, which signal can be used to control the blanking operation. Since such a control signal is usually not outputted, it would involve specific intervention in the videotape device, which is not desirable. In addition, the output of a blanking control signal attempts to provide the PCM encoding / decoding unit as a simple "matching unit" without special connections.

8100348 -6-

It is therefore an object of the invention to provide an improved method and device for processing a pulse code-modulated signal to avoid the occurrence of an undesired sound when information is supplied to the device which is switched from the from one source of information to another.

Another object of the invention is to provide an improved PCM signal processing device which, for example, can be connected as a simple adaptation unit to a videotape device, without any special connections thereto, and without the need to derive special control signals, such that the videotape device as PCM- recording device can be used.

A further object of the invention is to provide an improved method and apparatus for controlling an error correction unit in a PCM signal processing apparatus to avoid malfunction of said error correction unit when connected to the PCM signal processing device PCM information is supplied, which is switched from one information source to another.

Yet another object of the invention is to provide an improved PCM signal processing apparatus, which is used with PCM information encoded in error correction format with interleaved time.

The. The invention provides a technique for avoiding errors in a PCM signal capable decoding unit of error-correcting type, to which successive transfer blocks are applied, each comprising time-interleaved PCM words, error correction words and error detection words, wherein the transfer blocks i come from a first information source and then j from a second information source to obtain an error interval determined by j the transition period from the first to the second source. According to the technique of the present invention, the presence of an error in an entry;

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a transfer block is detected, and each of the interleaved blocks in that transfer block is identified as erroneous. 8100348 * -7-. Each transfer block is subject to temporal interweaving to recover an interweaved block containing the interwoven PCM and error correction words. An erroneous PCM word in the interleaved blocks is corrected as a function of the remaining non-erroneous PCM and error correction words in that block. The correction of a PCM word in an interleaved block is blocked, if that block comprises at least one word from the first information source and another word from a second information source. Thus, if the PCM words include audio information, the generation of unwanted sounds resulting from an erroneous "correction" of said PCM word is prevented.

The invention will now be elucidated with reference to the accompanying drawing. Show in this:

Figure 1 is a block diagram of a PCM signal processing apparatus in which the present invention can be easily applied;

Figure 2 is a block diagram of a typical time-interweaving coding unit 20 usable in the device of Figure 1; Figure 3 is a block diagram of a typical time-de-interleaving decoder unit which may be used in conjunction with the device of Figure 1;

Figures 4A-4C show schematic time diagrams for explaining the operation of the interweaving coding unit;

Figures 5A-5E time diagrams for explaining the operation of the interweaving decoder? Figure 6 partly a block diagram, partly a logic diagram of an embodiment of the invention;

Figures 7A-7D schematically show waveforms of various signals generated and output by elements of the device of figure 6;

Figures 8A-8E are timetables for explaining one operating state of the device according to Figure 6; 8100348 * 'i -δ-

Figure 9 is a block diagram of another coding unit that can be used in connection with the invention?

Figure 10 is a block diagram of another weaving decoder which can be used in conjunction with the present invention?

Figures 11A and 11B schematic indications to explain the operation of the coding unit according to figure 9? FIGS. 12A-12F time diagrams for explaining the operation of the decoding unit of FIG. 10? and

Figures 13A-13C time diagrams to explain another company of the exemplary embodiment according to Figure 10.

Reference is now made to the drawing, and in particular to figure 1. This figure shows an exemplary embodiment of a PCM signal processing device 2, which can be used in connection with, for example, a video tape device 1 for supplying PCM-encoded audio signals to the videotape apparatus for recording and for receiving reproduced PCM encoded signals for generating and thereby output corresponding audio information. The video tape apparatus 1 may be of the helical scan type 25 having, for example, two (not shown) rotatable heads for recording signals in mutually parallel, inclined tracks along a magnetic tape, as usual. The video tape apparatus includes a recording section 4 with appropriate recording electronics, servo control systems, and the like, for controlling the recording of signals in said tracks. Furthermore, the video tape apparatus 1 comprises a reproducing section 5 with reproducing electronics, servo control systems and the like, which serve to reproduce signals recorded in said tracks. The recording section 4 is coupled to a recording input terminal 3, which is typically supplied with typical video signals of the type having periodic horizontal sync signals, 8100348 φ ϊ -9 vertical sync signals and video information signals. As is known, such a composite television signal comprises high-frequency components.

The display section 5 is coupled to a display 5 output terminal 8 such that when the videotape device 1 is used in a video signal reproduction mode, composite television signals are read from the magnetic tape and applied to the output terminal 8 '. Usually, the output terminal 8 is coupled to a television receiver or a monitor for displaying images corresponding to the video signals displayed.

Also, the videotape device 1 comprises a switching unit 6 with fixed contacts 7a and 7b and a movable contact 7c, which can selectively cooperate with one of both fixed contacts. The movable contact 7c is coupled to the output terminal 8 for supply to this output terminal of the signals supplied to either the fixed contact 7a or the fixed contact 7b.

As shown in the drawing, the fixed contact 7a is coupled to the output of the display section 5 and the fixed contact 7b is coupled to the input terminal 3. When the switching unit 6 is in the configuration shown in Fig. 1, the signals shown by the display section 5 signals reproduced from the contact 7a via the movable contact 7c applied to the output terminal 8. When the circuit 6 is switched such that the contact 7c is in engagement with the contact 7b, the signals normally supplied to the recording section 4 also become applied to the output terminal 8. The switch 6 is shown in this figure as an electromechanical switch; it will be understood, however, that it may also be of the electronic type, the transition interval being the interval during which the movable contact 7c switches between the fixed contact 7a and the fixed contact 7b being relatively short.

The PCM signal processing device 2 is coupled to the terminals 3 and 8 of the videotape device 1 8100348 -10- ¢ -% and serves as an associated adjustment unit. The PCM signal processing device includes an encoding section for generating and outputting an encoded PCM signal; the output of this encoding section is coupled to the input terminal 3 via a PCM output terminal 9. The PCM signal processing device 2 also includes a decoding section, which includes a PCM input terminal 10 coupled to the videotape output terminal 8. The purpose of the PCM signal processing device is to encode an analog input signal, for example an audio signal, in PCM error correction format, and to supply this PCM coded signal to the video tape apparatus 1 for recording. As mentioned above, the videotape device is arranged to record video signals with relatively high frequency components. Furthermore, as is known, videotape devices generally exhibit advantageously high recording densities. Therefore, the videotape device 1 is particularly useful for recording PCM encoded audio information.

When the display section 5 of the videotape device 1 reproduces the PCM encoded audio information, the PCM encoded signals are supplied through the videotape device input terminal 8 to the PCM input terminal 10 such that the decoding section of the device 2 is decode these recovered PCM signals and convert the decoded signals back to the analog audio format.

The coding section of the device 2 comprises an analog input terminal 11, which is adapted to receive an analog input signal such as an audio signal, which terminal 11 is coupled to an analog / digital converter (A / D converter) 13, an encoding unit 14 and a amplifier 15, all of which are connected in series in the manner shown,

The outputs of the amplifier 15 are coupled to the PCM output terminal 9. The A / D converter 13 is arranged for sampling the analog audio signal applied to the audio input terminal 11 and for generating a corresponding multi-bit existing digital word. Typically, this multi-word digital word 8100348 * 11-bit is a pulse code modulated word. For example, each PCM word output from the A / D converter 13 consists of 14 bits of information.

If the audio input signal of the audio 5 input terminal 11 is a binaural signal consisting of left channel and right channel signals, the A / D converter generates 13 PCM words representing each sample of said signals. The A / D converter 13 is shown in block form? it is noted that it may consist of a separate filter for the left and right channels, separate sample and wood circuits and A / D converters, as described in applicant's previously cited US patent applications 86,677. The output of the A / D converter 13 is supplied to the encoder 14 which is operable to convert the PCM information supplied thereto into error correction format and additionally to perform a time base compression operation to form "blank" or "blank" Intervals in the information stream into which various video synchronizing signals are inserted, for example, periodic horizontal and vertical synchronizing signals. Thus, the encoder 14 serves to encode the PCM information into, for example, an interleaved time-correction error correction format and, by inserting therein said video synchronization signals, for generating a simulated video signal.

This simulated video signal is amplified by the amplifier 15 and supplied through the PCM output terminal 9 and the video tape device input terminal 3 to the recording section 4 of the video tape device 1. "This tape device 1 serves to record the PCM signals, which are encoded in error correction format, and include the various video synchronization signals It will be appreciated that the electronic units of this tape apparatus interpret these encoded PCM signals 35 as simulated video signals On display, these simulated video signals are reproduced from the playback section 5 via the video tape apparatus output terminal 8 and PCM input terminal 10 on the decoding section of the 8100348

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-12- PCM signal processing device 2 supplied. This decoding section includes a synchronizing signal separating circuit 16, a decoding unit 17 and a D / A converter 18, all of which are connected in series as shown. The synchronization signal separation circuit 16 serves to separate the video synchronization signals, i.e., the horizontal and vertical synchronization signals, which were inserted into the encoded PCM signals for recording. Thus, the decoder 17 receives encoded 10 PCM signals with "blank" or "blank" information intervals therein, which intervals correspond to the separated sync signals.

The decoder 17 is compatible with the encoder 14 and operates to expand the time base of the encoded PCM signals to the original time base; and in addition, the decoder 17 serves to restore the original PCM signals from the error correction code. As will be described, the encoder 14 operates to encode the 20 PCM signals in the signal format with so-called interlacing in time.

Thus, the decoder 17 serves to de-interleave these PCM signals. Furthermore, the decoder 17 includes error correction and error compensation circuitry for correcting errors that may be present in the recovered PCM signals, for example errors due to signal dropout, noise, interference and the like. If such errors cannot be corrected, an approximation of the erroneous PCM signal is generated by the error correction circuits, and this approach is used to replace the erroneous PCM signal.

Decoder 17 thus operates to reconstruct the original PCM signals supplied by A / D ora converter 13 to encoder 14.

These reconstructed PCM signals are fed to the D / A converter 18, where they are converted back to their original analog audio signal level. For example, the D / A converter 18 can perform a conversion of the 8100348 te -13- corrected or compensated PCM signals to the original binaural left channel and right right channel audio signals. These audio signals are applied to the audio output terminal 12, from where they are supplied for amplification to an audio amplifier 19 for driving the speaker 20 for sound output.

It is noted that by recording the original audio signals in digital form, a high degree of fidelity and accurate reproduction of the original signals is obtained from the speaker 20. Since furthermore, the PCM signal processing device 2 is connected only to conventional video tape input and output terminals. 3 and 8, the device 2 is designed as a simple adaptation unit for the videotape device. Special connections do not need to be made with the videotape device; nor do special control signals need to be taken from them to control or synchronize the operating state of the video tape apparatus and the PCM signal processing apparatus.

When the video tape apparatus 1 is used to record the encoded PCM information signals, the reproduced PCM signals are supplied from the display section 5 to the PCM input terminal 8 when the switching unit 6 has the configuration shown in Figure 1. When this switch is operated to engage the movable contact 7c with the fixed contact 7b, the encoded PCM signals present at the PCM output terminal 9 are applied to the PCM input terminal 10. Thus, the speaker can be 20 are used to monitor the PCM encoded audio information recorded by the recording section of the videotape device.

The present invention is directed to a number of aspects of the PCM signal processing device 2. The device is shown as used in conjunction with a video tape device 1; however, it will be appreciated that the PCM signal processing unit can be used 8100348-14 with other devices, for example, information transfer units, information receivers and the like, if desired. Furthermore, as will be apparent from the following argument, the switch 6 may be used to supply encoded '5 PCM signals to the decoding section of the PCM signal processing device 2 from either a first or a second information source. In the application shown in Figure 1, the first information source includes a video tape device display section 5; the second information source includes the encoding section of the PCM signal processing device. However, as will become apparent, other information sources may also be used for supplying encoded PCM information to the decoding section of the PCM signal processing apparatus 2.

An exemplary embodiment of a part of an encoding unit 14 is shown in Figure 2. This exemplary embodiment is arranged to encode the PCM signals from the A / D converter 13 in error correction format with time interleaving. That portion of the encoder 14 that serves to time-compress the encoded PCM signals and insert blank intervals generated thereby into video synchronization signals is not shown. Nevertheless, the exemplary embodiment according to Figure 2 is referred to in this text only as the encoding unit.

The encoding unit of Figure 2 comprises a distribution unit 22, an error correction word generator 23, time delay circuits 24a and 24b, a mixing unit 25 and an error detection code generator 26. The distribution unit 22 is coupled to an input terminal 21 and arranged to receive consecutive PCM words which can be supplied thereto, for example, by the A / D converter 13 in word-segmental form. Each word can consist of a number of sequential or parallel bits, for example 14 bits.

The distribution unit 22 serves as a demultiplexer for separating or distributing the single channel of consecutive PCM words applied thereto over separate parallel channels, referred to as the left and right channels. Thus, each 8 1 0 0 34 8 -15 channel receives a sequence or series of PCM words, resp. associated with left channel and right channel audio information. Figure 2 shows the sequence of left channel PCM words as the left channel SL and the sequence of 5 right channel PCM words as the right channel SR. It will be explained hereinafter that successive information blocks are generated at the output of the distribution unit 22 in successive time intervals, referred to as transfer block intervals, which intervals are equal to the time interval occupied by a transfer block. A coding unit transfer block of FIG. 2 includes a left channel word: L ^ and a right channel word R ^, both words of which are generated simultaneously at the output of the distribution unit.

The left channel SL and the right channel SR are applied to an error correction word generator 23. For example, the error correction word generator is a parity word generator and arranged to sum the left 20 channel and right channel PCM words and R 1 contained in one information block. , at the output of the distribution unit 22 in modulo-2 form. Thus, the parity word generator 23 may include a conventional modulo-2 adder.

The function of the parity word generator 23 is to generate and output a sequence of parity words SP, each parity word P ^ being generated in response to the modulo-2 addition of the left channel and right channel PCM words, so that P ^ = Θ R ^. The resulting parity word P ^ appears to have the same number of bits (eg 14 bits) as each of the left channel and right channel PCM words, and each parity word P ^ is associated in particular with the PCM words L, and R. from which it is derived.

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It will be apparent to those skilled in the art that the parity word P2 can be used to reconstruct an erroneous PCM word, provided the parity word and the other PCM word are correct. For example, if during the transmission, recording, display and reception of the information block consisting of the PCM words L. and R ^ and 8100348 «·· '<-16-, the parity word P ^ contains an error in the PCM- word L ^, the correct version of the PCM word may nevertheless be recovered depending on the non-erroneous PCM word R ^ and the non-erroneous parity word P ^ in the recovered information word. Such error correction techniques are known to the person skilled in the art and will therefore not be described further.

The PCM and parity words constituting each information block are selectively time delayed by the time delay circuits 24a and 24b. In particular, the right channel series SR and the parity series SP are applied to resp. the time delay circuits 24a and 24b. The left channel series SL in the exemplary embodiment of FIG. 2 is not applied to a time delay circuit. In other words, this left channel sequence is delayed by a time interval corresponding to a zero magnitude delay. The time delay circuit 24a delays the right channel sequence SR by a predetermined amount D; the time delay circuit 24b delays the parity series SP by a larger amount 2D. D is a time interval equal to two transfer block intervals, a transfer block interval equal to the time interval occupied by a transfer block. A transfer block is similar to an information block, except that the specific words constituting the transfer block are formed from the resp. delayed PCM and parity words. This means that the transfer block consists of interleaved PCM and parity words. It will be understood that the time delay circuit 24a and 24b serve to interleave the resp. words. For example, if, as will be described hereinafter, the fourth information block is applied to the time delay circuits, this fourth information block consisting of PCM words L4 and R ^ and a parity word P ^, then the transfer block output from the delay circuits may be that is, the temporally interleaved transfer block consisting of interleaved words are represented as PCM words L ^ ^ and R £ and the 8100348-17 parity word Pq.

According to Figure 2, the resulting interleaved transfer block consists of the sequence of undelayed left channel PCM words SL, the delayed sequence of right 5 channel PCM words at the output of the time delay circuit 24a identified as the delayed right channel sequence. SR ^, and the delayed sequence parity words at the output of the time delay circuit 24b, which delayed parity sequence is identified as SP ^.

10 It goes without saying that in any given transfer block the PCM and parity words therein can be identified as L ±, and Pi_2D-

The equalized PCM and parity words in each transfer block are supplied to the error detection code generator 26. In one exemplary embodiment thereof, this error detection code generator is a cyclic redundancy code (CRC) generator. The use of error detection codes and in particular the CRC code for detecting the presence of one or more errors in a block of information words is generally known. For example, the PCM and parity words in a transfer block applied to the CRC generator 26 can be expressed as polynomial over a Galois field, which polynomial is divided by a generator polygon to obtain a remainder, which is added to 25 a transfer block as CRC codeword. This means that the CRC codeword, together with the PCM and parity words, forms the interwoven transfer block. On display, when this transfer block is displayed, a polynomial is formed from the displayed PCM, parity and CRC words, and this polynomial is shared by the same generator polynomial used in the CRC generator. If no remainder is obtained in this division, it is concluded that the displayed transfer block contains no error. However, if a remainder is generated, the transfer block contains at least one error. As will be described further, when an error is detected in the displayed transfer block, a "pointer" or error flag associated with each PCM and parity word is set, identifying each 8 1 00 34 8 '-18- such word, the displayed transfer block is erroneous.

The CRC generator 26 generates a sequence of error detection words, which sequence is referred to as SC. It will be understood that a PCM word in the 1 ink anal-5 series SL, together with a PCM word in the delayed right channel sequence SR ^, together with a party word in the delayed parity sequence SP. together with a word in the error detection series SC, all occur simultaneously. As shown in Figure 2, these words, which are interwoven in time, form a transfer block and are fed to the mixer 25. The mixer serves as a multiplexer for serial transfer of the words fed thereto in parallel format. The output of the mixer 25 is coupled to an output connection 27 for supplying successive transfer blocks thereto, which are supplied in series format. If desired, the time occupied by a serialized time-interleaved transfer block originating from the mixer 25 may be equal to a transfer block interval.

This is achieved when the mixer 25 receives a read clock signal, the frequency of which is four times higher than that with which each four-word transmission block is applied.

The series-converted transfer blocks at the output terminal 27 can be fed to a synchronizing mixing circuit (not shown) which serves to insert the conventional video synchronization signals into the current transfer blocks. The mixer 25 may serve to perform a time base compression operation on the transfer blocks supplied thereto to obtain blank intervals into which the video synchronization signals are inserted. The circuits which can be used to perform such a time base compression are known to those skilled in the art.

Figure 4A shows successive information blocks formed of parallel PCM words L ^ and R ^ and a parity word P ^. For example, at the time t ^ the information block formed of (LjR- ^ P ^) is output, at the time t ^ the information block (L ^ R ^^), at the time t2 the information 8 1 0 0 34 8-19 "block" etc * The time delay circuits 24a and 24b introduce selective delays of size D and 2D into resp. the right channel PCM word and the parity word. Figure 4B represents the transfer block formed by this temporal interweaving of respective words. Figure 4B also shows the CRC code word C1, which is generated by the CRC generator 26 depending on the PCM and parity words of each transfer block. Thus, at the time t ^ the interwoven transmission block 10 (LqR_2P_ ^ Cq) is generated, at the time t ^ the interwoven transfer block (L ^ R ^ P ^ C ^), at the time t2 the interwoven transfer block (L2RqP_2C2 ^ etc *) it appears that in each transfer block the respective words present therein have a mutually interwoven structure in time In such an interwoven transfer block there is little, if any, correlation between the words present therein.

Figure 4C shows the serial format conversion of successive interleaved transfer blocks. It is clear that a blank interval is formed between adjacent transfer blocks for recording video synchronization signals to be inserted therein.

Figure 3 shows an exemplary embodiment of a decoding unit compatible with the coding unit according to Figure 2. It will be appreciated that the encoder of Figure 2 is a time-interleaved error correction encoder. It is clear with this that the decoding unit according to figure 3 is an interweaving error correction decoding unit, which is in particular compatible with the exemplary embodiment shown in figure 2.

The decoding unit of Figure 3 includes a distribution unit 29, an error detecting unit 30, time delay circuits 31a and 31b, an error correction circuit 32, a compensation circuit 33, and a mixing unit 34. The distribution unit 29 is coupled to an input terminal 28 for receiving the serial converted converting locks of Figure 4C which can be read from a recording medium or from another information source. It will be understood that the transfer blocks supplied / converted to the 8100348-20 distribution unit 29 are substantially free of video synchronization signals, which may be inserted into the original transfer blocks, which synchronization signals have been removed by for example, the synchronization signal separation circuit 16 (see Figure 1). The distribution unit 29 is arranged to distribute the different PCM, parity and error detection words in separate, parallel channels. The distribution unit can also consist of a demultiplexer unit, which works complementary to the multiplexer unit present in the mixer unit 25.

Thus, the distribution unit 29 serves to restore successive interwoven transfer blocks, consisting of the left channel sequence SL, the right channel sequence SR ^, the parity sequence SPj and the error detection sequence SC.

The said restored transfer blocks can be represented by the time diagram of Figure 4D.

The error detection circuit 30 may include a CRC control circuit to which all interleaved words contained in a received transmission block are applied. The CRC control circuit operates in the manner previously discussed in detail for detecting the presence of any error in a received transfer block. If an error is detected, the CRC control circuit 30 generates a "wise 25" or error flag, associated with each PCM and parity word in the received transfer block, for identification or indication that those words are "incorrect." In one embodiment, the CRC check circuit 30 does not determine which specific word is erroneous (or which words are erroneous). With a view to error correction in interweaving over time, it is sufficient to design all words in an erroneous transfer block as erroneous. In another exemplary embodiment, corresponding, for example, to the technique described in applicant's earlier U.S. Patent Application 31,030 of April 18, 1979, the specific erroneous words are indicated.

The time delay circuit 31 is coupled to the distribution unit 29 to introduce a size 2D 8100348-21 time delay into the left channel PCM words contained in the left channel segment SL. As shown by the broken line in Figure 3, the "pointer" or error flag for these left channel words is also delayed. The time delay circuit 31b is provided to introduce a time delay D into the right channel PCM words in the right channel sequence SR ^. The "pointer" or error flag for each right channel PCM word is also delayed. The parity words contained in the parity sequence SP ^ are not delayed. Obviously, the time delay circuits 31a and 31b provide time delays complementary to the time delays which are introduced by the time delay circuits 24a and 24b in the encoder of Figure 2. These decoder time delay circuits serve to time-weave the respective words in each received transmission block. the time delay circuits are the original time relationship of the PCM and pa reality values that include each original information block are restored. The temporal interleaved information block consists of the delayed left channel sequence SL. ^, The delayed right channel sequence SR117, and the undelayed parity sequence SP1. The "pointers" or error flags associated with the de-interleaved words are also available at the outputs of these time delay circuits.

The error correction circuit 32 is connected to receive each sequentially interleaved transfer block. For example, the error correction circuit may be designed as a conventional parity decoder operating when the pointer or error flag associated with one PCM word applied thereto is set. During operation, the error correction circuit 32 sums the PCM and parity words in the interleaved information block, for example, by modulo-2 addition, to obtain a syndrome. This syndrome is then used to correct the erroneous PCM word contained in the interleaved information block. When the erroneous word is corrected, the associated pointer is canceled. As usual, the error correction circuit 32 does not work if the pointers associated with two of the words applied thereto are set. Also, the error correction circuit 32 does not work if the parity word applied thereto has been identified as erroneous. If the parity word is identified as erroneous, but the PCM words are not, there is of course no need for correction of these PCM words.

The corrected PCM words are applied by the error correction circuit 32 to a compensation circuit 33, along with their associated pointers or error flags. If an erroneous PCM word is corrected, its error flag is removed. However, if an erroneous PCM word has not been corrected, for example, if the error flags associated with two words associated with the error correction circuit 32 are made, thereby making the error correction impossible, the error flags are not removed. The compensation circuit 33 serves to approximate a correct value for the erroneous PCM word applied thereto. For example, the compensation circuit 33 may be of the last value holding type and may be operative to replace the erroneous PCM word with the last received correct PCM word. For example, if the PCM word Lg was correct, but the subsequent PCM-25 word cannot be corrected, the previous value Lg is held and used as a replacement for the incorrect value L ^. Since the PCM words represent audio information, and since audio information varies relatively slowly, sufficient compensation is achieved by this type of approach. In another exemplary embodiment, the compensation circuit 33 may be of the so-called "interpolating" type, where the correct value of a PCM word is approximated by interpolating or averaging the two correct PCM words that immediately precede and immediately follow. the PCM word is incorrect, but the PCM words Lg and L2 are correct, the interpolating type compensation circuit obtains an average value of the PCM words Lg and L2 as approximation of the correct value for the interpolating type. PCM word L ^.

The respective PCM words at the output of the compensation circuit 33 are applied to the mixer unit 34 operable to combine the left channel and right channel words applied thereto into a single output channel. These serialized PCM words are applied to an output terminal 35, from which they can be converted to analog form and used to drive a loudspeaker or other transducer. Briefly, during operation, the decoder shown in Figure 3 receives batch-converted, time-interleaved transfer blocks of the type shown in Figure 4C. The distribution unit 29 restores the format of these transfer blocks to obtain the different outputs of the PCM, parity and CRC words, as shown in Figure 4B. If one of the words present in the received transfer block is erroneous, the CRC control circuit 30 sets an error signal associated with each word in that block. The interleaved PCM and parity words in each received transfer block are time-resolved to restore the original time relationship of Figure 4A. If one of these interleaved words was identified as erroneous, this identification will be maintained.

Subsequently, an error correction circuit 32 serves to correct an erroneous PCM word in an interleaved information block. If, as mentioned above, two words in an interleaved information block are identified as erroneous, these words are not corrected. Instead, the compensation circuit 33 approximates the correct value 30 of such "uncorrectable" PCM words. The resulting corrected / compensated left channel and right channel PCM words are then mixed by the mixing unit 34 into a single channel and fed to the output terminal 35.

It will be appreciated that the interleaved error correction code implemented by the encoding unit of Figure 2 and the decoding unit of Figure 3 is advantageous in that burst errors are avoided. That 8100348 -24- means that errors of significant length, which might otherwise corrupt a significant portion of the PCM information, have been minimized, allowing for error correction and compensation. The time interleaving error correction code reduces the possibility of recovering an interleaved information block with two or more erroneous PCM words. For example, suppose the transfer blocks with the words (LqR_2P_ ^) and (L ^ R_ ^ P_3) are detected as erroneous, using the CRC codewords Cq and 10 Each word in these transfer blocks is thus identified as erroneous. Unwrapping these words to restore the original information blocks will show that in the information block with the words (L_3R_3 P_2) only the parity word P_3 is incorrect. In the interleaved information block (L_2R_2P_2 ^ only the PCM word R_2 is incorrect. In the interleaved information block (L_ ^ R__1 P_ ^), only the PCM word R_ ^ is incorrect. In the information block (IjqRqPq) only the PCM word Lq is incorrect. erroneous In the information block (L ^ RP ^), only the PCM word is erroneous 20 In each of these five interleaved information blocks, only one word contained therein is erroneous Such words with only one error can be easily corrected by the error correction circuit 32. In this manner, a burst error of the length D is easy to correct. If the burst error exceeds this length, then the compensation circuit 33 serves to compensate for erroneous PCM words that cannot be corrected by the error correction circuit 32.

As already mentioned above, the PCM signals supplied to the decoding unit according to Figure 3 can be reproduced by, for example, a video tape apparatus. However, suitable PCM signals can also be added to the decoder by another information source.

In Figure 1, the switch 6 provides one switch arrangement 35 for supplying the PCM signals to the decoder of either the reproducing section 5 of the videotape device 1 or from the encoding section of the PCM signal processing device 2. Generally, a switch of the Switching type are applied for supplying time-interleaved transfer blocks PCM signals from either a first information source designated as source 1? 1 or a second information source identified as source 5 In Fig. 1 corresponds to the display section 5 with the source if1, and the PCM encoding section of the PCM signal processing device 2 corresponds to the source ^ 2. However, it will be clear that other suitable sources of information can also be used.

When the switch 6 is operated to change the specific information source associated with the PCM decoding unit, for example, by switching from the information source 4f-1 to the information source # 2, an error interval is produced with a time period determined by the transition time of the switch. That is, as shown in Fig. 5A, if the start of the switching operation occurs at time tQ, the error interval or transition interval extends from the time tg to the time t ^. At time t ^, switch 6 fully couples source ^ = 2 to the PCM decoder. In Figure 5A, this error interval or transition interval is shown by the cross-sectioning section. At the beginning of this error interval, transfer blocks from the information source are supplied to the decoder; at the completion of this error interval, transfer blocks from information source 4f2 are supplied to the decoder. In the exemplary embodiment shown in Figure 1, the decoding unit 17 receives transfer blocks from the display section 5 prior to the error interval; further, transfer blocks are supplied to the decoder by the encoding section of the PCM signal processor 2, following the error interval.

Suppose the error interval is equal to or less than one transfer block interval. Figure 5B shows a time slide -35 grams of consecutive interwoven transfer blocks, which are delivered to the outputs of the distribution unit 29. Those transfer blocks originating from the source - # 1 are shown in the absence of brackets and which are transferred. 34 8 I · Ί ".......... I <iM 1 1111 I 'mm * -26- carrier blocks coming from the source, i.e. those transfer blocks displayed at the outputs of the distribution units, following a start of the transition interval, are indicated with brackets.

If it is assumed that the error interval is equal to or less than a transmission block interval, only one transmission block will be erroneous - that is, the transmission block received immediately following the start of the transition interval. Figure 5B identifies those 10 words in this transfer block, which are considered error, with the index "x". In particular, the CRC control circuit 30 sets the error flag associated with each of the words L1, and Pq. It will be appreciated that signal dropout during this information error interval will result in those error flags being set.

Figure 5C shows a timing diagram of the recovered information blocks obtained by deweaving the transfer blocks shown in Figure 5B. As shown and as will be appreciated, the interleaving / interleaving technique serves to propagate the erroneous words in each interleaved transfer block, with only one word identified as erroneous in several interleaved information blocks. Thus, in the interleaved information block (PqRqLq) only the parity word P1 is identified as erroneous. In the interleaved information block (P ^ R ^ L ^), no words are identified as incorrect. In the interleaved information block (p2R2L2 ^ νοΓ <^ only the PCM word R £ is identified as incorrect. In the interleaved information block (P ^ R ^ L ^) no words are identified as erroneous. Finally, in the interleaved information block ( P ^ R ^ L ^) only the PCM word identified as erroneous Since at most one word in each interleaved information block is identified as erroneous, it will be apparent that the error correction circuit 32 serves to correct the erroneous PCM words.

However, it will be recognized that, during interval 2D, four interleaved information blocks are output with words from both the source J% 2 81ÖO 34 8 -27- and the source # 1. Let the block intervals during which those de-interleaved information blocks are output be represented as block intervals, respectively. TB ^, TB2, and ^ 4 * In the information blocks occupying the block intervals TB ^ and TB2, the PCM words are from the source ^ rl, but the parity words are from the source # 2. in the information blocks occupying the block intervals TB3 and TB ^, only the left channel PCM words are from the source ^ frl. The remaining PCM and parity words come from the source = ^ 2. It will be understood, therefore, that if the error correction circuit 32 operates during the block interval TB ^ to "correct" the erroneous right channel PCM word R2, no correct error correction can be achieved. This is the case, since the error correction for the PCM word R2 will be based on the parity word P2 and the PCM word L2. However, since the information source of the PCM word L2 is different from the information source for the parity word P2 and the PCM word R2, the lack of correlation between them will prevent correct correction of the erroneous PCM word R2. Moreover, there is a risk that the error correction by the error correction circuit 32 will distort the resulting "corrected" word R2 such that, when converted to an analog signal for driving the speaker 20, it produces sharp or otherwise undesired sound.

Because of the error interval due to the operation of the switching unit 6, errors will be distributed among a number of interleaved information blocks. The error correction circuit 32 will operate normally in an attempt 30 to correct individual erroneous PCM words. However, the normal operation of this error correction circuit during the block interval TB ^ will produce an undesirable result. The object of the invention is to prevent this result from occurring without the need for special connections, while also requiring no special control signals, which can be produced by either the switch or by the videotape device associated with which it is used . In particular, the present invention prevents an incorrect error correction operation on the interleaved information blocks which do contain words from source # 1 as words from source φ2.

One exemplary embodiment of the invention is shown in Figure 6. Those elements in figure 6 which are equal to the elements already described with reference to figure 3 are indicated with the same reference symbols. Figure 6 does not show the distribution unit 29. It will nevertheless be understood that this distribution unit 10 is used to provide the interleaved left channel sequence SL, the right channel sequence SR. ^, The parity sequence SP. ^ And the CRC sequence SC. In addition to the elements already described above, the unit of figure 6 comprises a counter 37, a detector 38, a pulse generator 39, an OR gate 36, a non-OR gate 40, a syndrome generating circuit 41, an AND gate 42 and a monostable multivibrator 38. The counter 37 is coupled to the output of the CRC control circuit 30 for counting each pointer or every error signal output from CRC-20 control circuit when an error in a received transfer block is detected. Although not specifically indicated, it will be appreciated that the CRC control circuit delivers an error flag pulse at the end of each transfer block interval. This pulse is converted by a suitable circuit (not shown) so that it is operated for substantially the entire transfer block interval. to which he belongs is present. This can be achieved, for example, by drawing a monostable circuit of an appropriate time constant with the error flag pulse and additionally passing the respective sequences SL ^, SR ^ ^ and SP ^ through a delay circuit having a delay of the size of one block introduces. Thus, the output of the monostable circuit will coincide with the outputs of each of these sequences delayed by one block.

The output of the counter 37 is coupled to the detector 38 adapted to detect when the counter 37 reaches a predetermined counting result. For example, if the counting result of the counter 37 exceeds the number 2, the detector 38 detects this situation and draws the pulse generator 39. This generator 39 may be equal to the said monostable circuit and at 5 draw a simulated pointer or error flag. OR gate 36 includes one input coupled to CRC control circuit 30 and another input coupled to pulse generator 39 to provide either the actual error flag produced by the CRC control circuit or the simulated generated by the pulse generator error flag.

The non-OR gate 40 includes one input connected to receive the pointer associated with each interleaved left channel PCM word in each interleaved information block, another input connected to receive 15 the pointer associated with with each interleaved right channel PCM word in each interleaved information block, and another input connected to receive the pointer associated with each interleaved parity word in each deinterleaved information block. As can be seen from the drawing, this last input is coupled to the output of the OR gate 36 and thus receives either the actual error flag generated by the CRC control circuit 30 or the simulated error flag generated by the pulse generator 39. It will be appreciated that the non-OR gate 40 serves as a coincidence circuit to detect whether all of these error flags have been cleared. The OR gate gives a non-error signal SD, which is a binary "1" when no error flags are detected, and a binary "0" when one or more error flags are detected. This non-error signal SD 30 is applied to one input of AND gate 42. The other input of this AND gate is coupled to the output of a syndrome forming circuit 41.

The syndrome generating circuit receives the PCM and parity words from each interleaved information block for generating a syndrome by the modulo-2 addition of the words. In particular, the syndrome-forming circuit forms the syndrome Θ R ^ © L ^. In the absence of errors in the interleaved information block, and if all words present in that information block originate from the same source, the generated syndrome corresponds to a predetermined value. However, if an error is present in one of the de-interleaved words, or if the information block contains words from different information sources, the resulting syndrome will not correspond to this predetermined value. The generated syndrome is applied to the error correction circuit 32 and used therein to correct an erroneous PCM word.

Furthermore, the syndrome generating circuit 4i generates a syndrome signal SS, which is a binary "1" when the generated syndrome deviates from its predetermined value and is a binary "0" when the generated syndrome corresponds to that predetermined value. This syndrome signal SS is applied to the AND gate 42 in which the coincidence between the syndrome signal SS and the non-error signal SD is detected. As will be appreciated, AND gate 42 outputs an output when an interleaved information block does not contain errors, but the generated syndrome for that interleaved information block is different from said determined value.

The monostable multivibrator 48 is coupled to the AND gate 42 and is drawn depending on the access signal from the AND gate to generate a blocking signal P. This blocking signal is applied to the error detection circuit 42 and serves to block the operation of the error correction circuit for the duration of the blocking signal. Preferably, the monostable multivibrator 48 has a time constant 30 such that the blocking signal Pc has a duration corresponding to two information block intervals. When the error correction circuit 32 is blocked, no error correction operation is performed. Thus, if one of the PCM words supplied to the error correction circuit is identified as erroneous, such a word is not corrected. Then, the compensation circuit 33 performs said compensation or approximation operation to replace the erroneous PCM word with an approximate value 8100348 -31- thereof.

Suppose in operation that the transfer blocks supplied to the decoder according to figure 6 originate from the information source τΆ and then, after the information error interval shown in figure 5, originate from the information source φ2. The words contained in each interleaved transfer block will appear in the form shown in Figure 5B, with the erroneous information words identified by the index "x". The each interleaved, information-blocking, interwoven words will appear in the form shown in Figure 5C. As before, words from information source # 1 are indicated without brackets, and words from information source # 1 are indicated with brackets. Figure 5D shows a signal SD that would be generated if the non-OR gate 40 were replaced with an OR gate, and Figure 7A shows the non-error. signal SD at the output of the non-OR gate 40. FIGS. 5E and 7B show the syndrome signal SS, which is output by the syndrome-forming circuit 41 when the syndrome generated in response to the decomposed PCM and parity words deviates from the syndrome. predetermined value. It appears that the generated syndrome deviates from the predetermined value, when an interwoven word contains an error, and when an interwoven Information block is formed, from a number of words coming from one information source and a number of words coming from another source of information.

This corresponds to expectations, since in these circumstances there is no correlation between all words in the interleaved information block.

In the absence of the present invention, the error correction method 32 would always work when the signals SD and SS (see Figures 5D and 5E) coincide. Such an operation would result in the incorrect "correction" of the PCM word during the block interval TB ^. This incorrect correction is avoided by the exemplary embodiment shown in FIG. In particular, AND gate 42 outputs the output signal shown in Figure 7C. The trailing edge, or negative transition, of the first pulse generated by the AND gate 42 serves to pull the monostable multivibrator 48 to deliver a blocking pulse P for a duration of magnitude two information block intervals. Figure 7D illustrates that the blocking signal P is output during the full information block intervals TBg and TB ^. Thus, the error correction circuit 32 is blocked from operation during these information block intervals. Thus, during the information block TBg, the PCM word R2 is not corrected and, in addition, no correction is performed during the subsequent information block interval TB, even if during this information block interval the generated syndrome deviates from its predetermined value. In this way, the unwanted sound that would otherwise be generated by the erroneous 15 "correction" of the PCM word R2 during the information block interval TBg is avoided. Since the PCM word Rg has been identified as erroneous, and since it is not corrected by the "error correction circuit 32, instead, the compensating circuit 33 serves to replace" the "erroneous PCM word by an approximation thereof. For example, the preceding PCM word R1, which is indicated as correct, is reused as approach for the PCM word R2

In the preceding exemplary embodiment, it may suffice that the blocking signal P shows a duration that is only equal to a single information block interval TBg. It is preferred, however, that the blocking signal extends over two information block intervals to block the erroneous "correction" of, for example, the PCM word Rg in the case where the information error interval comprises two transmission blocks.

Thus, the non-OR gate 40, the syndrome generating circuit 41, the AND gate 42 and the monostable multivibrator 48 serve to block the error correction circuit 35 32 in the case where the information error interval is 1/2 D or D.

Now suppose that the information error interval is greater than D. As a special case, it is assumed that this information error interval is sufficiently large to obtain errors in three consecutive interlaced transfer blocks.

Figure 8A is similar to Figure 5C in that it shows the de-worded words in the de-worded information blocks delivered immediately before, during and after the aforementioned information error interval. As before, brackets identify those words that come from information source == 2, and the index "x" identifies those interleaved words, which are incorrect. It is clear that all words in the received transfer blocks' (P1R3L5) and (P2R3Lg) are identified as erroneous, since those transfer blocks were received during the informational interval.

Figure 8B shows the pointers or error flags generated by the CRC control circuit 30. As mentioned above, these pointers are generated at the end of each transfer block interval detected as error.

Figure 8C shows the waveform of the non-error signal SD. Since at least one word in each interleaved information block 20 during the information block intervals TB ^ ... TB ^ is erroneous, the non-OR gate 40 remains at its binary level "0" during these intervals. This is the case since at least one error flag is supplied to the non-OR gate during each such interval. Figure 8D represents the syndrome signal SS generated by the syndrome generating circuit 40. During the information block intervals TB ^ ... TB ^, the syndrome generated by the syndrome generating circuit differs from its predetermined value, either because at least one interleaved word is erroneous during each interval, or because some interleaved words during these intervals originate from the one information source and in other words, come from the other source of information.

When the CRC control circuit 30 issues the third 35 error flag at the end of the information block interval TB ^, the counting result of the counter 37 increases, thereby exceeding the predetermined counting result by the value 2. Detector 38 now senses that counter 37 8100348 -34- now exceeds this predetermined counting result and thus pulls pulse generator 39, thereby generating the simulated error flag shown in Figure 8E. This simulated error flag is generated after the generation of the third error flag, and thus the simulated error flag extends over the entire information block interval TB ^. This simulated error flag is passed through the OR gate 36 and is therefore associated with the parity word P3 in the interleaved information block (P3R3L3).

Figure 8A shows that since the parity words in the interleaved information blocks (PqRqLq) and (P ^ R-jL ^) are identified as erroneous, the error correction circuit 3 2 is not effective for correcting the PCM words in this blocks. Since further words are identified as erroneous in the information block 15 (P2R2L2 ^ ^, the error correction circuit does not work. However, in the information block (P3R3L3) only the PCM word R3 is identified as erroneous. Therefore, if the error correction circuit 32 is not blocked, he attempts to erroneously "correct" the PCM word R3 20. Such correction operation must be avoided since it is clear that this de-interleaved information block contains the PCM word L3 from the information source ^ 1, and the information source from the information source. other words, since there is no correlation between them, any "error correction" will be erroneous. However, by generating the simulated error flag during the information block interval TB ^, as shown in FIG. 8E, the error correction circuit 32 interprets the parity word P3. , which is associated with this simulated error flag, as erroneous, therefore the error correction circuit 32 interprets the interleaved information block (P3R3L3) as containing two errors, whereby the error correction circuit is not operative to perform an error correction operation.

The remaining de-interleaved information blocks supplied to the error correction circuit 32 contain all of the same information source, namely the source "# - 2, 8100348 -35- coming words. Therefore, for those information blocks containing only a single erroneous word, the error correction circuit 32 normally used for word correction.

It will be appreciated that when the error correction circuit 32 is blocked for operation, the compensation circuit 33 operates to replace non-correctable PCM words by approximations thereof, as described above.

Thus, it appears that when the error interval covers three or more transfer blocks, an erroneous error correction operation, which could otherwise be performed, is avoided. In the above-described exemplary embodiment, the simulated error flag issued by the pulse generator 39 is associated with the interleaved parity word. While this simulated error flag may be associated with an interleaved PCM word, in some cases it may prevent an error compensation operation, which is why it is not preferred.

Figure 9 shows another exemplary embodiment of an interwoven in the time-acting encoding unit. This encoder is arranged to distribute the left channel and right channel PCM words in a number of left channel and right channel sequences. Therefore, the encoding unit includes a distribution unit 22a, which may be similar to the distribution unit 22 already described, for dividing a single channel PCM words into two separate sequences, namely a left channel sequence SL and a right channel sequence SR. These sequences are fed to a further distribution unit 22b which in turn generates the left channel sequences CL · ^, SL2 and SL ^ under the control of the sequence SL, and generates the right channel selections SR ^, SR2 and SR ^ under the control of the sequence SR. For example, if the left channel sequence SL left channel PCM words L_2, L_ ^, L_q, L ^, L2, L ^,

L., L, - and Lr, and if the right channel sequence is 4 O O

the right channel PCM words R_2, R_ ^, R_q, R ^ R2, R3VR4,

Rj. and Rg, the distribution unit 22b is operable to distribute those sequential words into the following word-parallel information blocks ^ L1R1L2 R2L3R3) and (L ^ R ^ L ^ R ^ LgRg). It will be understood that each word in each of these information chunks is contained in an associated sequence SL ^, SR ^, SI ^, SR2, SL3 and ^ R3 * A ^ u, each information block is formed of three left channel words and three right channel words.

The encoder shown in Figure 9 also includes a parity word generator 23 with a plurality of inputs, each of which is connected to receive an associated word in each information block, which parity generator includes, for example, a modulo-2 adder similar to that already described parity word generator 23. Furthermore, another error correction word generator 44 is connected for receiving each of the words contained in an information block. The error correction word generator 44 may, for example, be a so-called "b-adjacent" type encoder adapted to generate a word of the parity type associated with the PCM words applied thereto. For example, suppose the information block (L ^ R ^ L2R2L3R3) is supplied by the distribution unit 22 to the encoder 44. This encoder generates a parity word Q ^, which can be expressed as: = t6l1 Φ T5! ^ Φ t4l2 φ t3r2 Φ t2l3 Θ tr3, where T is an array of an order generating polynomial G (x) and d _ 3. If d = 3, the generating polynomial G (x) is a reduced polynomial on the Galois field GF (2), which reduced polynomial can be expressed as 3 G (x) = 1 + x + x, so T can be expressed as: 30 tip 'T = 101

In the expression for the parity word Q, 2 3 4 5 '' 1 Τ, Τ, Τ, Τ, and T all differ from each other.

The respective PCM words, together with the P parity word generated by the parity word generator 23 and the Q parity word generated by the b-adjacent encoder 44, are all supplied 8100348-37- to an associated time delay circuit 24a. 24g.

These time delay circuits introduce associated time delays to the words applied thereto for time interleaving the PCM and parity words. In particular, the left channel sequence SL ^ is delayed by an amount OD (ie no delay), the right channel sequence SR1 is delayed by an amount D, the left channel sequence SL ^ by 2D, the right channel sequence SR £ by 3D, the left channel sequence SL ^ with 4D, the right 10 channel sequence SR ^ with 5D, the P parity sequence SP with 6D and the Q parity sequence with 7D. In these time delay circuits, the delay interval D is equal to the time occupied by two successive information blocks. It will further be clear that the minimum difference between two 15 time delays is equal to D.

The interleaved PCM and parity words at the output of the delay circuits are applied to the mixer 26 and additionally to the CRC generator 26. This may be the same as the described CRC generator for output 20 of a CRC sequence SC. Each CRC word in the Sequence SC is based on the interleaved PCM and parity words applied to the CRC generator. Obviously, these intertwined PCM and parity words, together with the generated CRC word, form an interwoven transfer block. In the illustrated embodiment, each such interlaced transfer block consists of n PCM words, two error correction (or parity) words and one CRC codeword. In this particular example, n - 6. As will be understood, n may also be any other desired integer.

The mixing unit 25 is similar to the described mixing unit in that it converts each interwoven interwoven transfer block supplied thereto in series format. Successive serial-converted transfer blocks are output to output terminal 27 and may be applied to a time base 35 compression circuit to form blank intervals in the serialized transfer blocks, with a video sync signal inserted at each blank interval.

8100348 -38-

The encoder shown in Figure 9 is the same as the encoder described in applicant's earlier U.S. Patent Application No. 86,677.

If desired, the error correction word generator 44 may be of another conventional type; it is not limited to a b-adjacent type encoder. It is noted that, regardless of the specific type of the error correction word generators used, by including two parity words in each transfer block, the decoder 10 is capable of correcting two erroneous PCM words which may be present in any received information block.

This ability, along with the spreading of burst errors due to the interleaved code, results in an improved error correction scheme.

In the exemplary embodiment shown in Figure 9, the mixing unit 25 generates a series-converted transfer block of the type detected according to Figure 11A. If D is the time delay with an effective magnitude of two information block intervals, at the time when the distribution unit 22b issues the information block (L ^ ^ I ^ R ^^ R ^), the interleaved transfer block at the output of the mixer 25 : '(L1R-5L__l4R_l6L_21R_ <27P_35Q_4lC1). The simulated video signal generated under the control of this series-converted transfer block appears in the form indicated in Figure 11B. It appears that each serialized transfer block corresponds to a "line interval" of video information, while the transfer block itself is identified by the reference number 46, and is preceded by an information synchronizing signal 45, 30 followed by a white level reference signal 47, and is included in the control interval defined by the horizontal sync signals HD. PCM encoded signals with the waveforms shown in Figure 11B can be easily recorded by a conventional video tape device.

An exemplary embodiment of a decoding unit compatible with the encoding unit of Figure 9, which is adapted to decoding each 8100348-39 shown in serial format transfer block received in Figure 11 is shown in Figure 10. This decoding unit comprises a distribution unit 29, a CRC control circuit 30, time delay circuits 31a-31g, an error correction circuit 32, an error compensation circuit 33 and a mixing unit 34. The distribution unit 29 is the same as described above in Figure 3. distribution unit shown, with the proviso that the distribution unit of Figure 10 serves to demultiplex each barely interwoven transfer block into n parallel PCM words, two parity words and one CRC word. In the exemplary embodiment described herein, n = 6. For example, the transfer block shown in Figure 11A is applied in word-parallel form to the multichannel outputs of the distribution unit 29, which outputs correspond to resp. the sequences S1 ^, SR ^, SL12, SR12, SL13, SR13, SP] L, SC ^ and SC.

All interleaved words in the received transfer block are applied to the CRC control circuit 30.

This circuit operates in the manner already indicated above for designing or identifying all words present in the received interlaced transfer block as erroneous. Namely, the CRC control circuit detects an error in a received transfer block and, when an error is detected, the pointer or error flag associated with each word in the received transfer block 25 is set.

The time delay circuit 31a-31g are arranged to introduce time delays into the interleaved words of each received transfer block, which time delays are complementary to the time delays 30 introduced by the coding unit shown in Figure 9. Thus, each left channel PCM word in the sequence SL ^, which was not subject to time delay in the encoder, is now subject to a maximum time delay 7d by the time delay circuit 31a. The right channel 35 PCM words in the sequence SR ^, which were subjected to a time delay of D time units by the encoder, are now subjected to a time delay of 6D by the time delay circuit 31b. Similarly, 8100348 -40- the sequence SL12 is subjected to a time delay 5D by the time delay circuit 31c, the sequence SR12 to a delay 4D by the circuit 3ld, the sequence SL ^ g to a delay 3d by the circuit 31e, the sequence SR13 5 to a delay 2D through circuit 31f, the sequence SP ^ to a delay D through circuit 31g, and the sequence SQ ^ to a delay 0D. Thus, the original time-aligned information blocks, consisting of time-deinterleaved PCM and parity words, are sequentially outputted at the outputs of the time delay circuits. Each interleaved block includes a delayed sequence SL ^, a delayed sequence SR121 / a delayed sequence SL ^ 12, a delayed sequence SR112 / a delayed sequence SL113 / a delayed sequence SR113, a delayed sequence SP ^ j, and an undelayed parity sequence SQj, wherein each interleaved word in these sequences is accompanied by its corresponding pointer or error flag, which is also output at the output of each time delay circuit.

The error correction circuit 32 is coupled to receive the deinterleaved PCM and parity words in each information block, along with the error flags associated with those words. The error correction circuit may be of the type described in applicant's U.S. Patent. application 195,625. It will be appreciated that since the error correction circuit is supplied with two parity words P1, two erroneous PCM words can be corrected in an interleaved information block. For example, the error correction circuit 32 may form a first syndrome based on the PCM words and the P parity word in the '30 interleaved information block; he can also form a second syndrome based on the PCM words and the Q parity word in that information block. These syndromes can then be used to correct two erroneous PCM words. Thus, a burst error with the maximum duration of 2D, that is, a burst error affecting four consecutive transfer blocks, can be corrected.

If three or more PCM words in an interleaved information block are erroneous, or if the parity words 8100348-41- in an information block are erroneous, the error correction circuit 32 is not operative to correct the PCM words. Accordingly, those PCM words that are erroneous and the error flags that are set are applied to the error compensation circuit 33. This error compensation circuit may be equal to the previously described error compensation circuit which approximates the correct value for an uncorrectable PCM word. The corrected / compensated PCM words are then fed through the compensation circuit 33 to the mixing unit 34, in which they are multiplexed into a single PCM channel and fed into the output terminal 35. This single channel of PCM words can then be converted into analog shape and are used, for example, to drive the loudspeaker 20.

The invention, an exemplary embodiment of which has been described with reference to Figure 6, is suitable for use in connection with the interweaving interlocking decoding / decoding arrangement according to Figures 9, 20 and 10. The embodiment according to Figure 6 may be modified, that the syndrome forming circuit 41 is constructed as two separate syndrome forming circuits, one for forming the syndrome in dependence on the P parity words and the other for forming the syndrome in dependence on the Q parity words. The non-OR gate 40 is supplied with the error flag associated with each PCM and parity word, and the monostable multivibrator 48 exhibits a time constant with a period of, for example, 10 information block intervals. Also, pulse generator 39 generates a simulated error flag with a duration of, for example, 9 information block intervals.

It will now be briefly described how the present invention works with the exemplary embodiment of the decoding unit of Figure 10. Figure 12A shows a time diagram of successive interleaved information blocks.

The Sequence Interwoven Parity and PCM words are represented as the sequence SC ^, SP. ^, SR113, SL213 "SR112" Sullig / and SLm "with the 8100348 0" * for each sequence.

-42- corresponding time delay is shown. The solid lines represent the words originating from the source, and the broken lines represent the interleaved words originating from the information source. As before, it is assumed that the de-interleaved transfer blocks are first supplied to the decoding unit from the information source # 2 and then, during a transition interval that forms the error interval as shown by the cross-hatched areas in Figure 12A, successive transfer blocks are issued by the information source ^. In the example of Figure 12A, it is assumed that the information error interval affects only one received interlaced transfer block received. Figure 12A shows those specific information blocks into which the errors due to this transition interval are divided. For the sake of convenience, the parity sequence SQ ^ has been used as reference, since this sequence has not been delayed by the decoding unit shown in Figure 10.

Figure 12B shows the non-error signal SD, which is output, for example, from the non-OR gate 40 depending on successive interleaved information blocks. Figure 12C shows the syndrome signal SS ^ formed by the syndrome forming circuit depending on the de-interleaved P parity sequence SP ^. It appears that this syndrome signal starts at the beginning of the interval 25 TD2, that is, this syndrome signal starts with the error in the delayed P parity sequence. Figure 12D shows the syndrome signal SS2, which is formed by the syndrome forming circuit depending on the Q parity sequence SQ1. It appears that this syndrome signal SS2 starts at the beginning of the interval TD ^, which means that this syndrome signal starts with the detected error in the interleaved Q parity sequence SQ ^. Both syndrome signals SS1 and SS2 end when the last error in the interleaved information blocks is detected? this means that the syndrome signals end upon detection of the error in the delayed sequence SL ^^. It is believed that the only errors present in the interleaved information blocks are those represented by the crosshatch areas.

If the exemplary embodiment of Figure 6 has been used in conjunction with the decoding unit of Figure 10, it is assumed that AND gate 42 receives the syndrome-5 signal (see Figure 12C) as well as the non-error signal SD (see Figure 12A). The resulting output signal from the AND gate thus takes the form shown in Figure 12E. The initial negative direction transition in the output of the AND gate (see Figure 12A) 10 is used to draw the monostable multivibrator 48, which generates the blocking pulse P of Figure 12F. The time constant of the monostable multivibrator is assumed to be equal to five intervals TD, that is, it is equal to the time interval occupied by 10 consecutive information blocks. 30, the error correction circuit 32 is blocked by this blocking pulse Pc from the time when the first de-interleaved PCM word is received in the sequence * to the time when the last de-interleaved PCM-20 word (in the sequence SLi ^) is received. Figure 12A shows that during the duration of the blocking pulse P,

O

each interleaved information block at least one PCM word from the information source ^ 1 and the other from the information source Jfr2. Contains PCM words. It is recalled that when an information block includes PCM words from different information sources, there is no correlation between those PCM words and therefore error correction thereof cannot be properly performed. To avoid an erroneous "correction", the blocking pulse P prevents operation of the error correction circuit 32 during the interval in which said mixed PCM words are present.

It will be apparent from Figures 12A and 12F that no error correction is necessary during intervals TD1 and TD2 since during these intervals the only errors present are those in the parity words. During the intervals TD ^ -TD ^, errors are present in one PCM word in those interleaved information blocks, the first half of each such interval being generated. During normal operation, the error correction circuit 32 operates to correct those erroneous PCM words.

However, each interleaved information block outputted during the 5 intervals TD-TD-DD contains at least one PCM word from source 4 = 1 and the other PCM words from source. Since there is no correlation between the two information sources, an incorrect PCM word in those information blocks cannot be corrected. Therefore, to avoid erroneous "correction" of those PCM words, the error correction circuit 32 is blocked by the inhibit pulse Pc during these intervals TD ^ -TD ^. Even if an erroneous PCM word has not been corrected by the error correction circuit 32 , nevertheless, a good approximation of the correct PCM word for it is substituted by the error compensation circuit 33.

During the interval TDg, the PCM word contained in the sequence SL · ^. ^ Is incorrect. However, in the interleaved information block containing this PCM word, all 20 other PCM and parity words are derived from the same information source, ie, all words present in this information block come from the information source φ2. Thus, the erroneous PCM word present in the sequence can be corrected by the error correction circuit 32 32 in accordance with the usual error correction operation based on parity or on the basis of the b-adjacent type.

Although not expressly stated, it will be understood that if the information error interval is a 30. length of D, for example, the non-error signal SD maintains its binary level "0" throughout the interval bounded by the syndrome signal SS2. Therefore, the output of AND gate 42, as shown in FIG. 12E, also remains on its binary level "O." Therefore, the monostable multivibrator 48 is not drawn, and the blocking pulse P is not generated.

Nevertheless, the occurrence of an information error interval of size D or larger is detected by the 8100348-45 combination described above of the counter 37 and the detector 38 (see Figure 6). For example, suppose the information error interval is equal to / 2.5D as shown in Figure 13A. Thus, the CRC control circuit 30 detects errors in each of five consecutively received transfer blocks.

If now the error correction circuit 32 is not blocked, it appears that the evaded information block delivered during the last half interval TD3 is the PCM word present in the sequence SR113 is erroneous and is derived from the information source 2, but that all other PCM words are correct and come from the information source - & Ί. The error correction circuit would attempt during the last half interval TD ^ to correct this erroneous PCM word in the sequence SR ^ 3. However, this error correction operation would be incorrect due to the various information sources from which the words contained in this de-interleaved information block originate. Likewise, in the interleaved information block received during the last half interval TD ^, the PCM words in sequences SR113 and SL ^ 13 are both erroneous, but none of the remaining words in this interleaved information block are erroneous. The error correction circuit 32 normally operates to correct these two erroneous PCM words under the control of the P parity and Q parity words, as well as the remaining non-erroneous PCM words 25 in this information block. However, such processing will cause an erroneous "correction" of these PCM words due to the fact that these erroneous words are from the information source 4 ^ 2, while the remaining PCM words in this information block are from the information source. 30 The lack of correlation between the information sources prevents correct error correction. The aforementioned erroneous error correction operation will be performed for the two PCM words identified as erroneous in the interleaved information blocks outputted during the last half of each of the intervals TD ^, TD ^ and TD ^.

The present invention is operative to prevent such erroneous error correction operations during these intervals. When the CRC control circuit 30 detects the presence of an error in the fifth received transfer block, for incrementing the counter 37 to a counting result of 5 with a delay time 2.5D 5 following the reception of the first erroneous transfer block , the counter 38 detects this predetermined counting result and draws the pulse generator 39. It generates a simulated error flag with a time such that the flag ends at the delayed time 7D. This simulated error-10 flag is associated with a suitable OR gate, for example an OR gate of the same type as the OR gate 36 already described, with the Q parity words of Figure 13B. For example, during the last half of each of the intervals TD ^ -TD ^, the Q parity words are identified as erroneous. During . In the last half of each of these intervals, two PCM words in each interleaved information block are also identified as erroneous. Since the Q parity word is now also erroneous for each of these information blocks, the correction circuit 32 may not function to correct both erroneous PCM words. Therefore, these PCM words are not corrected and an otherwise erroneous correction operation is blocked. The non-correctable PCM words are nevertheless replaced by close approximations thereof due to the operation of the compensation circuit 33. Thereby, each interleaved information block comprising a number of words from the source 1 and a number of words from the source 2 not subject to error correction. This prevents an erroneous error correction operation and thereby prevents the generation of unwanted sound due to an erroneously corrected PCM word.

Figure 13C shows a variant of the invention in connection with application to the decoder of Figure 10; in this case, the simulated error flag generated by the pulse generator 39 is added to the error flag, associated with each word in the sixth received transmission block.

This causes a "broadening" of each error flag to extend for a duration of 3D instead of the actual duration of 2.5D. From FIG. 13C, it is seen that ai 00 34 8 - 47 - each interleaved information block generated during the intervals TD-TD-3 contains three erroneous PCM words. Although the error correction circuit 32 is capable of correcting two error PCM words in each interleaved information block, the presence of three error PCM words prevents the operation of the error correction circuit.

With regard to the exemplary embodiment according to the invention described with reference to Figure 13A, it can generally be noted that when the CRC control circuit 30 detects the presence of each of the five consecutive received transmission blocks, the Q parity word in the subsequent m transfer blocks is indicated as erroneous. In the exemplary embodiment according to Figure 13A, the Q parity word is indicated as erroneous in the subsequent 9 transfer blocks. This causes a "broadening" of the error flag associated with the Q parity words in the manner indicated with reference to Figure 13B.

This implies that the error flag associated with the Q parity words is set during the reception of 14 consecutive 20 transfer blocks. Therefore, in any interleaved transfer block containing a number of words from the source ψΊ and a number of words from the source 2 2, at least three words in each such block are identified as erroneous. It is recalled that the error correction circuit 32 may not operate to correct more than two erroneous PCM words in any interleaved information block.

The invention is not limited to the exemplary embodiments described above and shown with reference to the drawing. For example, in the described examples, it is assumed that the base time unit or minimum time delay unit D is equal to the time interval occupied by two transfer or information blocks. Thus, it is assumed that D is equal to two transfer block intervals. If desired, other suitable delay times can also be used to increase the correctable length of the burst error interval that could occur due to the transition between the information sources. As a further variant, in the embodiments of Figures 9 and 10, the PCM sequence SL ^ -SR ^ and the parity sequence SP can be interleaved to obtain an interleaved subblock, while furthermore the respective PCM parity words 5 in each interleaved subblock may be further interleaved with the parity sequence SQ to obtain the resulting time interleaved transfer block as described in particular in applicant's U.S. Patent Application 195,625. Parity words have been described as the 10 error correction words in each transfer block; however, it will be appreciated by those skilled in the art that error correction words based on other error correction techniques may also be used.

15 8 i 00 34 8

Claims (21)

A method of error prevention in an error correction pulse code modulated (PCM) decoder to which decoder is supplied with successive transfer blocks each consisting of 5 interleaved PCM, error correction and error detection words from which the transfer blocks originate from an information source and then from another information source for outputting an error interval determined by the transition from one source to another, the method characterized by the following steps: detecting whether an information block supplied contains an error, identifying as erroneous of each of the interleaved words in the input transfer block, the detection operation of which has indicated an error, de-interleaving each input transfer block to recover an interwoven block consisting of interleaved PCM and error correction words, correcting an erroneous PCM word in the de-interleaved block mentioned as func the remaining non-erroneous PCM and error correction words in that interleaved block, and blocking the correction of a PCM word in an interleaved block, if that block contains at least one word from one source of information and another word from the other source of information. 2. A method according to claim 1, characterized in that the step of correcting an erroneous PCM word is characterized by generating a syndrome based on the PCM and error correction words in the interleaved block, and that at the step of blocking the correction of the PCM word is detected, whether said syndrome deviates from a predetermined value, while the absence of an erroneous word is detected in the interleaved block, and a blocking signal of a predetermined duration is detected on -35 awakened in dependence on the perceived absence of 8100348-50-9 an erroneous word / when the syndrome deviates from the predetermined value, all this in order to block the correction of PCM words during the blocking signal. 3. Method according to claim 2, characterized in that each interleaved block consists of two PCM words and one error correction word, and that the predetermined duration of the blocking signal is equal to the time occupied by two successive interleaved blocks. Method according to claim 1, characterized in that each interleaved block consists of n PCM words and two error correction words, such that two erroneous PCM words in the interleaved block are correctable as a function of the remaining non-erroneous PCM words and the non-erroneous two error correction words. Method according to claim 4, characterized in that in the step of blocking the correction of a PCM word, a syndrome is generated based on said PCM words and a predetermined copy of the error correction words; that it is observed whether a syndrome deviates from a predetermined value; that the absence of any erroneous words in the interleaved block is observed; and that a blocking signal is generated, the duration of which is substantially equal to the time occupied by a predetermined number of consecutive blocks of interleaved in response to the / observed absence of erroneous words, when the syndrome deviates from the predetermined value . 6. Method according to claim 1, characterized in that in the step of blocking the correction of a PCM word the number of consecutive blocks of errors is determined; detecting whether the counting result exceeds a predetermined value; that an error correction word is designated in at least the subsequently supplied transfer block as erroneous, wherein at least two words in an interleaved block of words from one and the other information source are identified as erroneous; and blocks the correction of a PCM word in an interleaved block with at least two erroneous words .g - 51 - Method according to claim 6, characterized in that in the time deweaving step of each input transfer block supplied, each word in the input transfer block is delayed by an associated time delay, wherein the minimum difference between two respective time periods is delay intervals equals D, where D equals the time interval occupied by a predetermined number of consecutive transfer blocks, which predetermined value is at least equal to said predetermined number. Method according to claim 4, characterized in that in the time deweaving step of each input transfer block each word in the input transfer block is delayed by an associated time delay interval, with the minimum difference between two consecutive time periods. delays is equal to the time interval occupied by a predetermined number of consecutive transfer blocks; and in the step of blocking the correction of a PCM word, counting the number of consecutive error transfer blocks 20, detecting whether said counting result exceeds the predetermined number, which one error correction word in each of the following m transfer blocks is is incorrectly designed (m equals the number of transfer blocks supplied during the largest occurrence of the time delay intervals), wherein at least three words in an interwoven block with words from one and with words from the other information source have been incorrectly identified and that the correction of a PCM word in an interleaved block contains at least three erroneous words. Method according to claim 4, characterized in that in the time deweaving step of each input transfer block supplied, each word in the input transfer block is delayed with an associated time delay, the minimum difference between two respective time delays being equal is the time interval occupied by a predetermined number of consecutive transfer blocks; and that in each step of blocking the correction of a PCM word, the number of consecutive transmission block counts with errors is counted, if the counting result exceeds the predetermined number, that all words in the next supplied transfer block are identified as erroneous, at least three words in an interweaved block with words from one source and words from the other source being identified as erroneous, and the correction of a PCM word in an interwoven block with at least three wrong words are blocked. 10. PCM signal processing device, arranged for reception of successive transfer blocks, each consisting of time-interleaved PCM error correction and error detection words, originating from a first or a second selectable information source, wherein a error interval is determined during the transition interval 15 when switching from one source to another, characterized by detection means responsive to the error detection words by detection, or a received transfer block containing an error; error identifying means for incorrectly identifying each of the interleaved blocks in the received transfer block which has been detected by detection to contain an error; interlacing means for de-interleaving each transfer block for recovering an interleaved block consisting of de-interleaved PCM and error correction words, identifying erroneous instances of the de-interleaved blocks, respectively; error correction means coupled to the interleaving means for correcting an erroneous PCM word in the interleaved block as a function of the remaining non-erroneous PCM and error correction words in that interleaved block; and blocking means for blocking error correction means if the interleaved block supplied thereto contains at least one word from one information source and another word from the other information source. 11. Device according to claim 10, characterized in that the error correction means comprise syndrome generating means for generating and delivering a syndrome based on the PCM and error correction words in the interleaved block; and ________L 8100348-53 - that the blocking means comprise means for outputting a syndrome signal, if said syndrome deviates from a predetermined value, means for outputting a non-error signal coupled to the interlacing means if none of the words in the interleaving block is erroneous, as well as means for generating and outputting a blocking signal of predetermined time in response to the coincidence of the syndrome and non-error signal, wherein the operation of the error correction means is blocked during the time of occurrence of the blocking signal . 12. Device as claimed in claim 11, characterized in that the error identifying means generate an associated error signal associated with each PCM and error correction word in a received transfer block detected as erroneous, wherein the respective error signals remain associated with the de-interleaved PCM and error correction words, and the means for generating and outputting a non-error signal comprises cox-correction means to which the PCM and error correction words of each interleaved block are applied to detect the absence of error signals associated with said words. Device as claimed in claim 12, characterized in that the co-oxidation means comprise a non-OR gate. 14. Device according to claim 12, characterized in that the means for generating and outputting a blocking signal comprise AND gate means coupled for receiving the syndrome signal and the non-error signal; as well as pulse generating means coupled to the output of the AND gate means. Device according to claim 14, characterized in that each interleaved block consists of two PCM words and one error correction word; and that the pulse generating means comprise monostable multivibrator means, the time constant of which is equal to the time interval occupied by two successive interwoven blocks. Device according to claim 11, characterized in that each de-interleaved block contains two error correction words; Which ? * - 54 - the syndrome generating means generates a syndrome based on PCM words and a predetermined copy of the error correction words, and that the means for generating and outputting a blocking signal output the blocking signal, the duration of which is at least substantially equal at the time interval occupied by a predetermined number of consecutive interleaved blocks. Device according to claim 10, characterized in that the error correction means are ineffective if two 10 or more words in an interleaved block supplied thereto are identified as erroneous; and in that the blocking means comprises counting means for counting the number of consecutive transfer blocks which do not contain any errors; means for detecting if the counting result exceeds a predetermined 15; and error designing means for designating the error correction word in at least the next received transfer block as erroneous, wherein at least two words in an interleaved block containing words from the first and second information sources are identified as erroneous. 18. Device as claimed in claim 17, characterized in that the interlacing means comprise a number of delay means, each of which has its own, mutually different, time delay and are arranged for delaying an associated word in the received transfer block, wherein the minimum difference between two consecutive time delays equals D, D equals the time interval occupied by a predetermined number of consecutive transfer blocks; and that the predetermined value is at least equal to the predetermined number. Device according to claim 18, characterized in that D is the time interval occupied by two successive transfer blocks. 20. Device according to claim 10, characterized in that the error correction means are ineffective if three or more words in an interleaved block supplied thereto are identified as incorrect; and that the blocking means - 55 - comprises counting means for counting the number of successive transfer blocks containing errors; means for detecting if the counting result exceeds a predetermined value; and error designating means for designating / fSSS correction word in a predetermined number of the next received transfer blocks as erroneous, wherein at least three words in each interleaved block containing words from the first and second information sources are identified as erroneous. 21. PCM signal processing device, arranged to receive consecutive transfer blocks, each consisting of time-interleaved PCM, error correction and error detection words from a first or a second selectable information source, wherein an error 15 interval is determined during the transition interval in which switching from one source to the other, the device comprising means responsive to the error detection words by detection, or a received transfer block containing an error; error identifying means for identifying as erroneous each of the interleaved words in the received transfer block which, according to the detection result, contains an error? interleaving means for de-interleaving each received transfer block for de-interleaving a received block, consisting of de-interleaved PCM and error correction words, identifying erroneous instances of the de-interleaved words, respectively? error correction means coupled to the interleaving means and operative to correct an erroneous PCM word in the interleaved block as a function of the remaining PCM and error correction words in that interleaved block, provided that the total number of erroneous words in that block is less is then a predetermined number? syndrome generators for generating the syndrome based on the PCM and error correction words in the interleaved block? means for generating and delivering a syndrome-35 signal, if the syndrome deviates from a predetermined value? means for generating and outputting a non-error signal coupled to the interlacing means, if none of --- - 56 - ^. V * 0 the words in the interleaved block are incorrect; means for supplying the error correcting means of a blocking signal of predetermined time in response to the coincidence of the syndrome and non-error signal, the operation of the error correcting means being blocked for the duration of the blocking signal; counter means for counting the number of consecutive transfer blocks containing errors; means for detecting whether the counting result exceeds a predetermined value, which is indicative of a predetermined duration of the error interval; and error designating means for designating an error correction word in a predetermined number of the next received transfer blocks as erroneous; wherein the number of words identified as erroneously in each de-interleaved block containing words from the first and second sources of information is at least equal to the predetermined number.