MY165522A - Leadframe packagewith die mounted on pedetal that isolates leads - Google Patents

Leadframe packagewith die mounted on pedetal that isolates leads

Info

Publication number
MY165522A
MY165522A MYPI2011000053A MYPI2011000053A MY165522A MY 165522 A MY165522 A MY 165522A MY PI2011000053 A MYPI2011000053 A MY PI2011000053A MY PI2011000053 A MYPI2011000053 A MY PI2011000053A MY 165522 A MY165522 A MY 165522A
Authority
MY
Malaysia
Prior art keywords
die
leadfingers
pedestal
leadframe
attach material
Prior art date
Application number
MYPI2011000053A
Inventor
Ko Mei Wan Sharon
Original Assignee
Carsem M Sdn Bhd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Carsem M Sdn Bhd filed Critical Carsem M Sdn Bhd
Priority to MYPI2011000053A priority Critical patent/MY165522A/en
Priority to CN201210002992.2A priority patent/CN102593090B/en
Publication of MY165522A publication Critical patent/MY165522A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A SYSTEM FOR PACKAGING DIES HAVING INTEGRATED CIRCUITS ON THEM INCLUDES A LEADFRAME HAVING LEADFINGERS, A MOLDED PEDESTAL THAT COVERS PARTS OF THE LEADFINGERS, A DIE-ATTACH MATERIAL DISPOSED OVER THE MOLDED PEDESTAL, A DIE DISPOSED ON THE DIE-ATTACH MATERIAL, A WIRE CONNECTING AT LEAST ONE OF THE LEADFINGERS TO A CONNECTION POINT ON THE DIE, AND AN ENCAPSULATING MATERIAL THAT ENCLOSES THE DIE, THE DIE-ATTACH MATERIAL, THE PEDESTAL, THE WIRE AND PARTS OF THE LEADFINGERS.THE MOLDED PEDESTAL IS A NON-CONDUCTIVE MATERIAL THAT WITHSTANDS SILVER AND COPPER MIGRATION AND ELECTRICALLY ISOLATES THE DIE FROM THE PLURALITY OF LEADFINGERS.A METHOD FOR PACKAGING A DIE INCLUDES FORMING A NON-CONDUCTIVE PEDESTAL ON THE LEADFRAME THAT COVERS PARTS OF THE LEADFINGERS, DISPOSING A DIE-ATTACH MATERIAL OVER THE NON-CONDUCTIVE PEDESTAL, DISPOSING A DIE ON THE DIE-ATTACH MATERIAL, CONNECTING LEADFINGERS TO THE DIE USING A WIRE, AND ENCLOSING THE DIE, THE DIE-ATTACH MATERIAL, THE PEDESTAL, THE WIRE AND A PORTION OF THE LEADFINGERS WITH AN ENCAPSULATING MATERIAL.
MYPI2011000053A 2011-01-06 2011-01-06 Leadframe packagewith die mounted on pedetal that isolates leads MY165522A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
MYPI2011000053A MY165522A (en) 2011-01-06 2011-01-06 Leadframe packagewith die mounted on pedetal that isolates leads
CN201210002992.2A CN102593090B (en) 2011-01-06 2012-01-06 There is the leadframe package of the tube core on the pedestal that is arranged on isolation lead-in wire

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
MYPI2011000053A MY165522A (en) 2011-01-06 2011-01-06 Leadframe packagewith die mounted on pedetal that isolates leads

Publications (1)

Publication Number Publication Date
MY165522A true MY165522A (en) 2018-04-02

Family

ID=46481540

Family Applications (1)

Application Number Title Priority Date Filing Date
MYPI2011000053A MY165522A (en) 2011-01-06 2011-01-06 Leadframe packagewith die mounted on pedetal that isolates leads

Country Status (2)

Country Link
CN (1) CN102593090B (en)
MY (1) MY165522A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097715B (en) * 2015-07-14 2023-10-13 深圳市槟城电子股份有限公司 Method and structure for packaging chip by insulating tube
US20190371989A1 (en) * 2016-11-11 2019-12-05 Lumileds Llc Method of manufacturing a lead frame
CN108269793A (en) * 2016-12-30 2018-07-10 菱生精密工业股份有限公司 The encapsulating structure of optical module
CN108847442B (en) * 2018-06-30 2022-01-25 山东昊润自动化技术有限公司 Pressure chip packaging method
CN112614900B (en) * 2020-11-27 2022-08-30 中国电子科技集团公司第十三研究所 Light guide switch packaging structure

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0363936B1 (en) * 1988-10-12 1996-03-27 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing electric devices
FR2723257B1 (en) * 1994-07-26 1997-01-24 Sgs Thomson Microelectronics BGA INTEGRATED CIRCUIT BOX
JP3483720B2 (en) * 1997-02-12 2004-01-06 沖電気工業株式会社 Semiconductor device
JP2006511080A (en) * 2002-12-20 2006-03-30 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ Electronic device and manufacturing method thereof
KR100601493B1 (en) * 2004-12-30 2006-07-18 삼성전기주식회사 BGA package having a bonding pad become half etching and cut plating gold lines and manufacturing method thereof
CN100533721C (en) * 2006-08-28 2009-08-26 力成科技股份有限公司 Chip packaging structure and method of producing the same

Also Published As

Publication number Publication date
CN102593090A (en) 2012-07-18
CN102593090B (en) 2016-05-04

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