MXPA99008573A - Integrated circuit and method for testing the same - Google Patents

Abstract

The invention relates to an integrated circuit with a CPU and a user ROM characterized by a test ROM whose address range is located inside the user ROM address range, a RAM located outside the CPU and switching means enabling access to either the user ROM or the test ROM and which can be irreversibly placed in a state allowing access to the user ROM only.

Description

INTEGRATED CIRCUIT AND PROCEDURE TO TRY THE SAME BACKGROUND OF THE INVENTION The first generations of chip cards, such as telephone cards or hospital cards, could essentially perform storage functions only. Subsequently, the proportionally simple logical functions, such as numerical comparisons or generation of pseudorandom numbers, were added. With the increasing use of chip cards in areas relevant to security, such as banking, where considerable data is partly stored, or when certain confidential data is stored, a microprocessor is increasingly used, which can lead to carry out complex protection, decoding and / or authentication operations. Increasingly, cryptological procedures are also used, which require considerable calculation work. The semiconductor chips contained in the current chip cards therefore include expensive and complex circuits, which are usually composed of a CPU, a ROM, an EEPROM (or EPROM), as well as other modules, such as a UART or a co-processor and a common line (BUS) that unites them. In general, a RAM is assigned to the CPU, configured most of the time as RAM static Since static RAMs require a lot of space, they are usually very small and have only less than one kilobyte of memory capacity. It is also characteristic of the products of chip cards that only present one to two serial interfaces with the outside, with which a data transmission is very delayed. Since parallel processing with 8 bits takes place internally, a serial / parallel conversion is required, so that said conversion also proceeds very slowly. Since normal data transmission is defined by an ISO standard and is carried out with only a few kilobits per second, it does not constitute a problem for normal operation, that is, operation with the user for the intended use as, for example, example, rechargeable money bag. The complex integrated circuits described, however, must be delivered to the customer with sufficient quality, so extensive testing is required. These product tests are carried out with the help of a self-test software. Therefore, the chip card products include a test memory, configured as ROM. This contains the self-test software, with whose help, after a power-on reset, parts of the chip can be tested. The self-test software consists of various test routines, which are called through vectors test. These can be entered through port 10. Since the size of the test memory is limited and varies among the various products, it usually does not contain all the test routines. For this reason, the other test routines must be loaded later in the EEPROM and executed from there. For this, several programming and deletion processes are required, which take longer than the test itself. The test memory configured as ROM is part of the ROM that is on the semiconductor chip, which also contains user programs, such as the operating system, and subprograms that are often used, such as programs for writing and erasing the EEPROM. The area of the test memory therefore occupies a part of the ROM address space, so that access by mistake, or also, intentionally and for purposes of misuse, to this address area is possible, even when trying to avoid with certain measures an access to this area of ROM addresses after the test. The implementation so far has, therefore, the disadvantage of, on the one hand, being too slow, so that the tests last too long and, thus, are expensive, and on the other, to allow even after the test, a access to the test routines, since these, in a ROM, are almost fixed by wires or, possibly, they can be remain non-volatile in an EEPROM on the chip.

OBJECTIVES AND ADVANTAGES OF THE INVENTION The objective of the present invention is, therefore, to provide a circuit that allows a quick test and offers a high protection against bad uses. The objective is achieved by an integrated circuit, which includes at least one CPU, a user ROM, a test ROM and an internal CPU RAM. The address space of the test ROM is within the address space of the user ROM, with a switching means being provided according to the invention, which allows access only to either the user ROM or the ROM of the user. proof. In an advantageous development, the switching means can be irreversibly transferred to a state that only allows access to the ROM of the user. In this way, at the end of the test phase, the test ROM can be blocked, without its previous address space being no longer occupied. In this way there is no gap in the available address space, in which blocked memory areas can be held, so that an intruder can not take advantage of it. In a development of the invention, in the test ROM there is only one start program of indispensable test to start it. Thus, the test routines themselves are written in a RAM external to the CPU, that is, additional, called X-RAM, where they are executed. A method in accordance with the invention is indicated in claim 7. Storing the test routine only in an X-RAM has the advantage that, after a test, by disconnecting the supply voltage, the routines of test, because the X-RAM is volatile. In the applications of the chip cards, normally only one input / output serial gate is available, since only a limited number of contacts are provided for communication with the outside. The .cumulator controlled by the CPU takes over the serial / parallel or parallel / serial conversion. The above is done by software and is correspondingly slow. For this reason, in a development of the invention, an activatable and deactivable shift register is provided, which connects the input / output gate additionally with an internal common line. Thus, test routines can be written to the X-RAM considerably faster. In a development of the invention, this shift register can be used to transmit the signals that arise during a test, for its monitoring, outward to the test apparatus. In this way, the test can be done more secure and fast. In the foregoing it is advantageous to encode said signals before their transmission, which can be advantageously carried out by a linear or non-linear retro-coupling of the shift register, for example, by means of an XOR gate. However, other gate functions are also possible.

BRIEF DESCRIPTION OF THE DRAWINGS Next, the invention is described in more detail based on an example of embodiment with the help of figures. They show: Figure 1, a connection diagram of an integrated circuit according to the invention. And Figure 2, a detailed connection diagram of an advantageous embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION According to Figure 1, a CPU, together with its assigned RAM, an additional X-RAM as well as a non-volatile EEPROM, are connected to each other through a common line. A serial input / output gate 1/0 is connected through the common line to the accumulator (not shown) contained in the CPU, which also serves for serial / parallel conversion. A ROM, which contains mainly software for the user, and a test ROM are also connected to the common line through a switching means MUX, which can be a multiplexer. The MUX switching medium can be controlled, for example, through the input / output gate 1/0 by the CPU, which is indicated by an arrow St. In accordance with the invention, through the MUX switching means it is always possible to connect and access the common line, either the ROM or the test ROM. The addresses with which the ROM can be accessed are at least partially identical to the addresses with which the test ROM can be accessed. Therefore, based on the addresses, it is not possible to recognize whether the ROM or the test ROM is being accessed. The common line can be irreversibly connected to the ROM through the MX switching means, so that at the conclusion of the test phase, the test ROM can be completely separated from the common line. Preferably, only one test start program required for the start of the test is stored in the test ROM. This program is called with a power on reset, so you can load test routines from outside in the X-RAM and run there. Writing the test routines in the X-RAM has the advantage that this process, on the one hand, takes place considerably faster, and on the other, it is only volatile, so that the test routines found in the X-RAM, for example, by disconnecting the supply voltage, can be quickly erased again. At the conclusion of the test, the MX switching means irreversibly takes a state that makes it impossible to access the test ROM through the common line. Figure 2 shows, in a more detailed manner, an advantageous development of the integrated circuit according to the invention. The I / O input / output gate, as already mentioned, can be accessed through an address decoder by means of a special function register address (SFR), through the common line of the CPU, which, On the other hand, it has parallel connections with the former. When controlling the 1/0 input / output gate via the special function register address, the data that enters and leaves is transported via the common line or the CPU. In it, with a control through programs through the accumulator, a serial / parallel conversion can take place, or, parallel / series of the data that enter, or exit. According to the invention, a shift register SR is connected parallel to this transmission path, by means of which it is possible to carry out a rapid serial / parallel conversion, or parallel / series during the phase of proof. The shift register SR is accessed and read by the CPU also via a special function registration address. For this purpose, a corresponding SFR address decoder is provided in the shift register SR. Through this special function registration address, the CPU can also activate and deactivate the shift register. To be able to recognize when a word was entered to be converted into the shift register SR, a Z counter is provided, which counts the Cl pulses with which the information is entered in the shift register SR, and after a word always sends a signal to the CPU, which controls the registration in the X-RAM. Since an integrated circuit CPU can normally process 8 bits in parallel, in principle an 8-bit shift register is sufficient. In this case, a single start bit must suffice for the synchronization of the data flow. After respectively 8 pulses counted by the counter Z, a serial / parallel conversion takes place at the time of reading, the contents of the shift register SR passing parallel to the common line. However, it is also possible to send a start bit before each byte to read, which would simplify the use of a personal computer as examiner. But then a 9-bit shift register is required. In addition, the data transmission would be less. In principle, the invention can be applied to any word width processed by a CPU, that is, especially also in the case of 16-bit and 32-bit central units. In this case, the shift register must have a corresponding length. The possible development of a test is as follows: first, the examiner sends a logical "0" to announce the start of a data transmission. In this way the counter Z is released, which every 8 pulses, indicates that a byte must be collected. The CPU can receive this notification by means of a special signal, but it is also possible to avoid this time by means of software. In the waiting loop, in which the CPU waits for the start of a transmission, the address counter of the X-RAM was adjusted before it was started. After the transmission, the test routine is called first and then the CPU jumps back to the reception waiting loop. In the pause between two transmissions, it is possible to run the counter Z. In this way, internal signals of 8 pulses could be combined with the pulse of the system Cl with the contents of the shift register SR, through any function, such as , an XOR (phase of collection) and deliver in the following 8 impulses (delivery phase). The combination is indicated by a double arrow from the shift register SR to the XOR gate. Actually, the output signal of the shift register SR is retro-coupled through the XOR to its input. The XOR, controlled by the CPU, can be connected or disconnected for coding purposes. The above is indicated by an arrow Pf. In each collection phase, this process can be interrupted by a start bit, so that a new data flow can be received. The combination of the internal signals with the content of the shift register SR during the collection phase has two reasons. On the one hand, it is possible to review the 8 values that are combined in the collection phase in terms of their accuracy; on the other hand, no signal is given outside, so that it is not possible to misuse this information by potential intruders. This advantageous development serves to increase the coverage of the test and an earlier recognition of defective chips, if the defects can be recognized in the internal signals observed.

Claims (6)

NOVELTY OF THE INVENTION Having described the above invention, it is considered as a novelty, and therefore, the content of the following is claimed as property: CLAIMS

1. An integrated circuit with a CPU, a RAM (XRAM) external to the CPU, a ROM of the user and a test ROM, as well as a common line that joins them, over which an access is only possible through at least one serial input / output (I / O) gateway and a rear serial / parallel converter, characterized: because the address space of the test ROM lies within the address space of the ROM of the user; because a switching means (MUX) is provided which allows access only to either the user's ROM or the test ROM; and because the serial input / output gate (1/0) for the serial / parallel conversion can be additionally connected to the common line by means of an activatable and deactivatable shift register (SR).

2. An integrated circuit in accordance with claimed in claim 1, characterized in that the shift register (SR) is retro-coupled through a logic gate (XOR).

3. An integrated circuit according to claim 1 or 2, characterized in that the deactivation of the shift register (SR) can be performed irreversibly.

4. An integrated circuit according to claim 1, characterized in that the switching means (MUX) can be carried irreversibly to a state, which only allows access to the ROM of the user.

5. A method for testing an integrated circuit, which has a CPU and a test ROM, as well as an external RAM to the CPU, characterized in that it includes the steps: - after a power-up reset, a start-up program is activated. test implemented in the test ROM, - controlled by the test start program, test routines are loaded into the RAM and from there they are executed by the CPU, - at the end of the test, the test routines in the RAM are erased and the execution of the test start program implemented in the ROM of the program is irreversibly avoided. proof.

6. A method according to claim 5, characterized in that the test routines are written to the RAM through an input / output serial gate (1/0) and a connectable serial / parallel converter.