MXPA99005454A - Image element processor for a memory management system using recompression - Google Patents

Abstract

A television receiver includes an MPEG decoder/decompressor (62-66) for providing decoded/decompressed pixel blocks. Decoded/decompressed pixels are recompressed prior to storage in frame memory (14). In the recompression process a reference first pixel is compressed as a function of a pixel block parameter. A reconstructed reference pixel value is used in a prediction network when reconstructing remaining pixels of the pixel block prior to display. A first pixel processor accurately compresses a reference pixel which prevents the propagation of a prediction error throughout the reconstructed block.

Description

I MAGEN ELEMENT PROCESSOR FOR A MINI-STRATION SYSTEM OF ME MORIA This invention relates to a digital video processor. Specifically, the invention relates to a system for encoding and decoding representative image elements of images (pixels or pels) in a block-based image processor. Memory management and memory reduction are important aspects in the design and operation of image processors. For example, consumer products such as television systems can use image processors including MPEG-2 signal processing. The MPEG (Cinematographic Film Experts Group) signal compression standard (ISO / I EC 13181 -2, May 10, 1994) is a widely accepted image processing standard that is particularly attractive for use with broadcast systems terrestrial, via cable, and via satellite that employ high defi nition television processing (H DTV) among other forms of image processing. Products that use high-definition screens require 96Mbits or more of memory to temporarily store MPEG decoded frames before being deployed. A M PEG processor requires that these frames for compensation and calculation of movements reconstruct precise images for their deployment. Systems that reconstruct decoded information images M P EG, commonly use Differential Pulse Coded Modulation (DPCM). In the differential pulse code modulation processing, as is commonly used in an MPEG decoder, a processor generates a prediction that anticipates the next pixel value. A sum network subtracts the prediction of the actual pixel value resulting in a difference. This difference known as prediction error is generally smaller than the original pixel or the pixel values so that quantifying and storing the difference instead of the original pixel value saves memory. Ang and co-inventors, "Video Compression Produces Big Profits", IEEE Spectrum, October 1991, describes an MPEG encoder and decoder. During decoding, a dequantizer substantially regenerates the same prediction of the previously decoded pixels. You only need one difference value and the prediction to decode and reconstruct the current pixel. The prediction is generally used partially or totally based on the previous pixel, which was decoded and reconstructed from the pixel that preceded it. For a more complete description of such forecasters and their operation, see Jain, A., Fundamental Aspects of Digital Image Processing, Prentice-Hall, Inc., page 484 (1989); and Gonzalez et al., Digital Image Processing, Addison-Wesley Publishing Company, Inc., pages 358-368 (1992). Accurately representing the first pixel in a block during compression of blocks of images avoids propagating the prediction error through the entire block of pixels. In soft areas, (ie, a display area that has subtle changes in color or objects or the like), the noise pollution of the first pixel can produce artifacts that an observer may find unacceptable. Therefore, the first processed pixel must be represented by a sufficient number of bits when it is stored in memory to ensure accurate reconstruction of the image. The present inventors recognize the need to provide a data reduction system with reduced equipment and software requirements that save memory without introducing error in the reconstructed data. A system in accordance with the present invention satisfies these objectives. In accordance with the principles of the present invention, a "first pixel" processor recompresses a predetermined reference pixel of a pixel block as a function of a pixel block parameter. In a disclosed embodiment of the invention, a television receiver includes an MPEG decoder. A decoded MPEG signal is provided to a data reduction network that quantizes data before it is stored in memory. The network employs a so-called first pixel processor that compresses (quantizes) a reference pixel of a block of pixels as a function of the minimum pixel block value. After decompression, the reconstructed value of the reference pixel is substantially equal to its value before the coding performed by the first pixel processor. It is so. The reference pixel can be used in a predictor network to reconstruct other quantized pixels in the image data block without worrying about propagating a significant error through a reconstructed pixel block. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of a pixel block processor including an apparatus in accordance with the present invention. Figure 2 shows details of a coding portion of the system of Figure 1 before it is stored in memory. Figure 3 is a flow diagram of a coding process of the reference pixel. Figure 4 shows a decoding portion of the system of Figure 1 after its storage in memory. Figure 5 is a flowchart of a decoding process of the reference pixel. Figure 6 is a block diagram of an MPEG compatible television system employing the present invention. In Figure 1, an MPEG decoder provides a block of MPEG decoded pixel data to a compressor 12. The compressor 12 includes a forecaster 18, a quantizer 20, and a combiner 22. For example, the forecaster 18 may be of the type described in Jain, A., Fundamental Aspects of Digital Image Processing, Prentice-Hall, Inc., page 484 (1989). The quantizer 20 quantizes the pixel block values and provides a block of pixels reduced in data to the memory 14. When the display processor (not shown) accesses the reduced data block in the memory 14 for the display of images, the decompressor 16 reconstructs the original pixel block. The decompressor 16 includes a predictor 24 and a dequantizer 26 for recovering reduced data from the memory 14 and for reconstructing the reduced data block. The quantizer 20 and the dequantizer 26 are configured in accordance with the principles of the present invention as will be described below. The forecaster 24 is of the same type as the forecaster 18. The input 10 of the compressor 12 receives a pixel block from an MPEG decoder that will be described in relation to Figure 6. For example, the pixel block is in the spatial domain and it comprises an 8 x 8 block of pixel images. The input 10 supplies the pixel block data to a non-inverting input of combiner 22 and to the quantizer 20. The output of the predictor 18 supplies pixel prediction data to an inverting input of the combiner 22 and the quantizer 20. The combiner 22 combines signals of its inverting and non-inverting inputs and provides the difference to the quantizer 20. The quantizer 20 outputs the quantized pixel values to the predictor 18. The quantizer 20 also outputs quantized pixel difference values for storage in the memory 14 Figure 2 illustrates quantizer 20 in greater detail. The same reference numbers identify elements common to Figures 1 and 2. Specifically, the quantizer 20 includes the encoder of the first pixel 30, the multiplexer 32 and the quantizing processor 28. The input 10 provides the block pixel data to an encoder of the first pixel 30, which operates by means of a predetermined reference pixel of the pixel block. The term "first pixel" does not refer specifically to a particular position of preferred pixel. The "first pixel" refers to a pixel in a block of pixels that will be used initially in a forecaster to reconstruct the pixel block. Therefore, the pixel becomes a reference pixel for all subsequently reconstructed pixels of a compression network employing a forecaster. The encoder of the first pixel 30 has two main functions. The most important function is to quantify the reference pixel. The second function is to reconstruct the storage requirements of the frame memory 14 by reducing the number of bits required to represent the quantized value of the reference pixel. These functions are described later. If the definition of the reference pixel is lossless or almost lossless, the pixel can be recovered from the memory 14, reconstructed with very little or no error and used as a prediction value for the remaining pixels in the quantized lock. Using an accurate prediction value initially in the prediction process prevents a prediction deviation error from propagating throughout the reconstructed pixel block. Reducing the number of bits required to store the quantized reference pixel reduces the size and cost of memory 14. The encoder of the first pixel 30 reduces the number of bits required to represent the quantized reference pixel by one to five bits in this example. Although this amount may seem insignificant, when considered in the context of a high definition television picture box that can contain more than 32, 600 pixel blocks of 8 x 8, each bit saved produces significant savings in memory. These savings become more significant when multiplied by the number of television receivers produced by a manufacturer. There is a potential conflict between accurately representing the reference pixel value and representing all the pixels including the reference pixel with the smallest possible number of bits. An obvious saving occurs if the memory is reduced by fifty percent, which translates into eight-bit pixel words that are compressed to four bits. Using four bits to represent the reference pixel can induce a significant error in the course of prediction processing. As an accurate representation of the reference pixel is important to begin the prediction process, use more bits, when necessary, than the average number of bits used to represent the remaining pixels is worthwhile. Therefore, the memory reduction is secondary to the precision relative to the reference pixei. For the remaining pixels in a block, memory reduction is more important than the precision of any pixel. The encoder of the first pixel 30 can represent each processed pixel as a word containing three to seven bits. It is practically impossible to determine the amount of frame memory that will actually be used to store frames of images for any given transmission signal due to its random nature. Therefore, the memory would have to accommodate the maximum word length (seven bits) for each pixel processed by the encoder of the first pixel 30 if it processes all the pixels. The encoder of the first pixel 30 receives the minimum pixel block value of the quantizing processor 28. The quantizer 28 receives pixel difference data from the combiner 22 and the predictor 18, and sends the quantized data to the predictor 18. Both the quantizer 28 and the encoder of the first pixel 30 sends quantized data to the multiplexer 32. The multiplexer 32 sends sequenced quantized data to the memory 14 (Figure 1) as will be described later. Figure 3 is a flowchart of the process of encoding the first real pixel hoisted by the encoder of the first pixel 30. In step 31, the encoder of the first pixel 30 processes the value of the first original pixel (Xo) of the input 10 and the least quantized pixel block value (Qm ín) of the unit 28 to produce a value of the first quantized pixel (QXo). Step 31 operates in accordance with the following equation: QXo = (Xo-Qmin) / 2. (1) The pixel values received at input 10 (Figure 1) of an MPEG decoder are integers. Therefore, the quantizing processor 20 and the encoder of the first pixel 30 receive and produce data representative of integers, including QXo. The advantage of using integers is a faster data transfer between elements, faster processing within the processors, and less complicated computer programs and equipment. Since Xo started as an integer when it was received by the encoder of the first pixel 30 of the MPEG decoded signals, data loss will occur only if Xo-Qm ín is a non-number. A non-divided number between two always has a residue of 0.5. If the system stores only the entire portion, then the rest is lost and is not available to reconstruct an image. The encoder of the first pixel 30 divides by two because a divisor of two immediately reduces by one the number of pixels required to represent the entire portion of the result. Use a larger divisor can save more bits but induces greater error. It has been observed that dividing by two produces an unfolded image that is substantially unaffected by the previous compression technique. Coding the first pixel reduces the original eight-bit pixel - > ^ by one to five bits in step 33. The determination of how many bits to use to represent the first encoded pixel depends on the value of the QR quantized range. The quantizer 28 (Figure 2) calculates the quantized range using the expression: QR = Qmax-Qm in + 1, (2) where Qmax represents the maximum quantized value in the block of pixels. The QR quantized range is selected as an indicator to set the number of bits designated to represent the value of the first coded pixel because the number of bits needed to represent the value of the first coded pixel is less than the number of bits needed to represent the value of the quantified range, as explained below. The quantizing processor 28 produces a quantized minimum value that is less than the minimum value of the original pixel block, and a quantized maximum value, which is greater than the maximum value of the original pixel block. Therefore, the following relationship exists: Qmin < = Xo < = Qmax, (3) where Xo represents a pixel value in the pixel block that is currently being processed. Equation (3) can be written as follows, incorporating equation (2): Qmin < = Xo < = Qm ín + QR- 1. (4) Subtracting Qmín from the three parts of equation (4) produces the following equation: 0 < = Xo-Qm ín < = QR-1. (5) Dich or first coded pixel QXo is half of Xo-Qmin (equation (1)), QXo requires one bit less to store it in memory 14 (in a binary system) than what the QR quantized range requires. Therefore, the quantizing processor 28 allocates one bit less than what is needed to represent the quantized range when determining the size of the word required to represent and store the value of the first coded pixel. Continuing with Figure 3, the encoder of the first pixel 30 initially constructs QXo as an eight-bit word in step 31. In step 33 the encoder of the first pixel 30 masks QXo by the appropriate number of bits for the current range and transfers the desired bits to the multiplexer 32. The masked QXo bits of step 33 are sent to the multiplexer 32 which holds QXo until it is transferred to the memory 14. The control and timing of this operation are described in relation to Figure 6. Figure 4 shows the configuration of the decoder of the first pixel 38, demultiplexer 34 and the dequantizer processor 36 in the dequantizer 26. The demultiplexer 34 transfers the data from the memory 14 to the decoder of the first pixel 38 and to the dequantizing processor 36. The decoder of the first pixel 38 receives the value of the first coded pixel of the demiplexer 34, and receives the minimum value of the block of pixels of the dequantizer processor 36. The decoder of the first pixel 38 decodes the first pixel to its quantized value as supplied to the input 10 ( Figure 1) of the MPEG decoded signal. The first reconstructed pixel is transferred to utilization circuits on a data bus along with the other reconstructed pixels of the pixel block of the dequantizing processor 36. The dequantizing processor 36 receives forecaster prediction data 24 (Fig. 1), and the other quantized pixel values of the demultiplexer 34. The dequantizer processor 36 reconstructs the value of the remaining pixel block to match the original bits per pixel size provided to input 10 (Figure 1) and outputs the reconstructed values as output. . The timing control of a local microcontroller causes the decoded reference pixel of the decoder of the first pixel 38 and the reconstructed pixel data of the dequantizing processor 36 to appear on a data bus at the appropriate time as required by a deployment processor. This will be seen in Figure 6. In any differential pulse encoding predictor network, the accuracy of the first data point used by the forecaster, such as forecaster 24, is critical to the accuracy of all data that is subsequently produced by the forecaster network for a data block. Each data point in the block is constructed on preceding data points by the forecaster network. The dequantized data represents the difference between the previous data point and the current data point. During reconstruction this difference is added to the previous reconstructed data point to achieve the current data point. Therefore, any errors introduced in the first data point will propagate as a prediction error for the subsequent data points in the same block. Figure 5 is a flowchart of the decoding process of the first pixel. In step 35, the decoder of the first pixel 38 performs a decoding operation according to the expression: RXo = 2QXo + Qmin, (6) where RXo represents the value of the first decoded pixel. QXo and Qmin are the same as in equation (1). Equation (6) represents the inverse of the operation represented by equation (1). Equation (1) is an operation of dividing by two and equation (6) is an operation of multiplying by two. Since the decoder of the first pixel 38 multiplies the first pixel coded by two during decoding, the maximum error in the value of the first reconstructed pixel is numerically one less than the original value of the first pixel. This occurs only if Xo-Qmin is a non-number, because the encoder of the first pixel 30 keeps only the entire portion of the pixel value during its encoding process. If Xo-Qmin is an even number, the value of the first decoded pixel is equal to the value of the first original pixel. After the decoder of the first pixel 38 calculates the value of the first decoded pixel RXo in step 35, RXo is filled with leading zeros to achieve the pixel word size required by the display processor in step 37. Generally, these are eight bits. In step 37, the decoder of the first pixel 38 adds zeros to the left of the most significant bit of RXo until it is an eight-bit word. All the bits added during this operation are zero (0) so that no error is entered in the value. The value of the first reconstructed pixel RXo is output to the deployment processor. As the compressor 12 and the decompressor 16 perform inverse operations, the architecture and construction of the system is simplified. Also the encoder of the first pixel 30 in step 31 and the decoder of the first pixel 38 in step 35 employ inverse operations that can be implemented by simple bit shifting using known bit shift techniques. Referring again to Figure 1, the memory 14 stores the value of the first coded pixel until it is no longer necessary for the display and reconstruction of pixels. During the time that the first encoded pixel resides in memory 14, it can be accessed and decoded by a subsequent display processor via decompressor 16. Compressor 12 and decompressor 16 resides as a common integrated system. The memory 14, conveniently it resides outside the integrated circuit thus allowing the size of the memory 14 to be selected as necessary to accommodate the signal processing requirements of a particular system. This results in savings in manufacturing cost, for example, in the case of a low cost consumer television receiver that uses a reduced resolution screen that requires less frame memory for the MPEG decoder. Figure 6 illustrates portions of a practical digital signal processing system in a television receiver that includes an apparatus in accordance with the present invention as described above. The digital television system of Figure 6 is simplified so as not to load the drawing with excessive details. For example, not shown are first-in-out input and output compensators associated with several elements, read / write controls, clock generator networks, and control signals to make interfaces with the external memories that may be of the same type. Type of output extended data (EDO) or synchronous type (SDRAM). The common elements in Figure 1 and Figure 6 have the same identifier. The elements in the signal processor 72, except for the compensator 70, correspond to the elements found in the STi 3500A MPEG-2 / CCI R 600 Video Decoder integrated circuit commercially available from SGS-Thomson M icroelectronics. The motion compensation unit 70 can use the STi 3220 Motion Sensor Stimulator integrated circuit available from the same manufacturer.

Briefly, the system of Figure 6 includes a microprocessor 40, bus interface unit 42 and controller 44 coupled to an internal control bus 46. In this example the microprocessor 40 is located external to the integrated circuit containing the MPEG decoder 72. An internal memory bus of 192 bits width 48 is a conduit for data from and to compressor 12, similar decompressors 16 and 50, and external frame memory 14. Units 12, 16 and 50 receive control signals of compression and decompression factor of microprocessor 40 and controller 44, together with activation control signals. The microprocessor 40 also divides the memory 14 into sections of screen display, compensator and frame storage bitmaps for M P EG decoding and display processing. Also included is a local memory control unit 52 which receives So-icity entries and provides Recognition outputs as well as outputs from Enable Write and Enable Read, and exit from Address. The memory control unit 52 generates real-time control and direction signals to control the memory 14. The memory control unit 52 also provides output clock signals Clock Input and Clock Output in response to the clock signals. Clock Input input clock from a local clock generator (not shown). The microprocessor 40 divides the memory 14 into bit compensators, video frame storage sections and frame table com ponents for MPEG decoding, and on-screen display maps and display processing. Deployment processor 54 includes vertical and horizontal resampling filters needed to convert an uncompressed image format into a common format predetermined for deployment by an image player deployment device 56. For example, the system can receive and decode corresponding image sequences. to formats such as progressive scan of 720 lines or 1 125 interleaved lines, or 525 interleaved lines. A television receiver will probably use a common display format for the receiver's formats. The external interface networks 58 transfer configuration and control information between the MPEG decoder and the external microprocessor 40 in addition to inserting compressed video data for processing by the MPEG decoder. The MPEG decoder system resembles a microprocessor-coprocessor 40, i.e. the microprocessor 40 issues a decoding command to the MPEG decoder for each frame to be decoded. The decoder locates the information of the associated header, which in turn is read by the microprocessor 40. With this information the microprocessor 40 outputs data to configure the decoder, for example with respect to the type of frame, quantization matrices, etc. , after which the decoder emits the appropriate decoding commands. The technical specification material for the above-mentioned SGS-Thomson STi 3500A and 3220 integrated circuit devices provides additional information on the manner in which the M PEG decoder operates. The microprocessor 40 passes mode control data, programmed by the receiver manufacturer, to the memory controller 52 to control the operation of the multiplexer 32 (Figure 2) and the demultiplexer 34 (Figure 4), and to set the compression factors / decompression for units 12, 16 and 50 as required. The disclosed system can be used with all the Profiles and all the Levels of the MPEG specification in the context of various digital data processing schemes, such as those which may be associated for example with terrestrial transmission systems, transmission via cable and satellite. Figure 6 also shows a portion of a digital video signal processor 72 such as that which can be found in a television receiver to process a high definition video input signal. Signal processor 72 includes a conventional M PEG decoder constituted by blocks 60, 62, 64. 66, 68 and 70 with the frame memory 14. Ang and coinventores, "Video Compression Produces Big Profits", I EEE Spectrum, October 1991, describes an example of the operation of an encoder and a Decoder MP EG. Signal processor 72 receives a data stream controlled from data encoded in M PEG from a previous input processor (not shown) eg a transport decoder that separates data packets after demodulation of the input signal. In this example, the received input data stream represents high definition image material (1920 x 1088 pixels) as set out in the Grand Alliance specification for the high definition terrestrial television transmission system of the United States of America. . The input data stream is in the form of data blocks representing 8 x 8 pixels. The data blocks represent compressed interframe and intraframe information compressed. The intraframe information includes anchor tables of the l-box. Generally the interframe information comprises residual information coded for predictive movement representing the image difference between frames of adjacent images. Interframe motion coding includes generating motion vectors that represent the offset between a current block that is being processed and a block in a previous reconstru image. The motion vector represents the best simi lity between the previous and current blocks is encoded and tra nsmite. Also the difference (residual) between each block 8 x 8 compensated for movement and the previous reconstru block is Transformed in Discrete Cosine (DCT), quantifies and codes to variable length (VLC) before being transmitted. Several publications, including Ang and co-inventors, mentioned above, describe motion-compensated coding processes in greater detail.

The compensator 60 accepts the compressed input pixel data blocks before they are decoded in variable length by VLD 62. The compensator 60 exhibits a storage capacity of 1.75 Mbits in the case of a M PEG profile data stream. main, main level. The inverse quantizer 64 and DCT 66 decompress decoded compressed data of VLD 62. The DCT output data 66 is coupled to an input of the adder 68. A signal of the compensator 60 controls the size of the quantization step of the inverse quantizer 64 to ensure a smooth data flow. The VLD 62 provides decoded motion vectors to the motion compensation unit 70 as will be described later. The VLD 62 also produces a selection control signal in interframe / intraframe mode as is known (not shown by simplification). The operation performed by units 62, 64 and 66 are inverses of the corresponding operations of an encoder located in a transmitter. By adding the residual image data of the unit 66 with the predicted image data provided from the output of the unit 70, the adder 68 provides a reconstructed pixel based on the contents of the video frame memory 14. When a processor of signals 72 has processed an entire frame of pixel blocks, frame memory 14 stores the resulting reconstructed image. In the interframe mode, the motion vectors obtained from VLD 62 provide the location of the predicted blocks of the unit 70. The image reconstruction process including the adder 68, the memory 14 and the motion compensation unit 70, conveniently exhibits reduced memory requirements significantly due to the use of the block compressor 12 prior to storing data in the frame memory 14. The size of the frame memory 14 can be reduced by up to fifty percent (50%) , for example, when a 50% compression factor is used. The unit 50 performs the inverse function of the unit 12 and is similar to the decompressor 16 described above. The compressor 12 and the decompressors 16 and 50 are constructed in accordance with the principles of the present invention as described and shown above in Figures 1, 2, 4 and 5.

Claims (18)

1. CLAIMS 1. A system for processing a data stream of pixel data blocks representative of compressed images comprising: a first decompressor (62-66) for decompressing such blocks of pixels to produce decompressed data; a compressor (12) for recompressing said decompressed data in recompressed data as a predetermined pixel block parameter function; and a memory (14) for storing such recompressed data. A system according to claim 1, wherein: said compressor recompresses a reference pixel of a data block as a function of said block parameter, and wherein said system additionally includes a pixel prediction network (18). ) that responds to such a reference pixel to facilitate the predictive processing of other pixels of such block of pixels. 3. A system according to claim 1, wherein: said block parameter is selected from at least one of the parameters including the minimum pixel value, the maximum pixel value, a reference pixel value, a range of pixel values, the average block pixel value, and the medium block pixel value. 4. A system according to claim 2, wherein: said block parameter is the minimum pixel value. 5. A system according to claim 1, further comprising: a second decompressor (16) for decompressing recompressed data from such memory as a function of said block parameter; and an output network (54, 56) including a display processor (54) for processing decompressed data by said second decompressor (16). 6. A system according to claim 2, wherein: said compressor (12) and said second decompressor (16) exhibit mutually inverse operational characteristics. 7. A system according to claim 3, wherein: said compressor (12) and said second decompressor (16) exhibit mutually inverse operational characteristics. 8. A system according to claim 5, further comprising: a third decompressor (50) for decompressing such recompressed data; and a motion compensation system (70) for providing compensated movement data in response to the decompressed data of said third decompressor. 9. In a system for processing a stream of image information data including MPEG compressed pixel blocks that constitute an image frame, such pixel blocks each have a block parameter, a processor comprising: a first decompressor (62) -66) to decompress such data stream into decompressed pixel block data; a compression network (12) for recompressing such decompressed pixel data into recompressed data as a function of such a block parameter; a pixel prediction network (18) responds to a reference pixel to facilitate the predictive processing of other pixels of such a data block; and a frame memory (14) for storing such recompressed data. 10. A system according to claim 9, said compression network (12) further comprises: a first data reduction network (30) for processing said reference pixel; and a second data reduction network (28) for processing other pixels of the pixel block. 1. A system according to claim 10, wherein: said first data reduction network (30) and said second data network network (28) are quantifiers. 12. A system according to claim 9, additionally comprising: a second decompressor (16) for decompressing recompressed data from said frame memory (14) as a function of said block parameter; and an output network (54, 56) that includes a display processor (54) for processing data decompressed by said second decompressor (16). 13. A system according to claim 12, wherein: said second decompressor (16) decompresses a second reference pixel of a data block as a function of such a block parameter, and wherein said system additionally includes a second pixel prediction network (24) that responds to such a reference pixel to facilitate the predictive processing of other pixels of said data block during decompression. 14. A system according to claim 13, said second decompressor (16) further comprises: a first data reconstruction network (38) for processing said reference pixel; and a second data reconstruction network (36) for processing other pixels of the pixel block. 15. A system according to claim 11, wherein: said compressor (12) and said second decompressor (16) exhibit mutually inverse operational characteristics. 16. A system according to claim 9, wherein: said block parameter is the minimum pixel value. 17. A system according to claim 10, wherein: said block parameter is selected from at least one of the parameters that include the minimum pixel value, the maximum pixel value, a reference pixel value, a range of pixel values, the average block pixel value, and the medium block pixel value. 18. A system according to claim 12, further comprising: a third decompressor (50) for decompressing said recompressed data; and a motion compensation system (70) for providing compensated movement data in response to the decompressed data of said third decompressor. RESU M E N A TV receiver includes an MPEG decompressor / decoder (62-66) to provide decoded / unzipped pixel blocks. The decoded / decompressed pixels are recompressed before storage in the frame memory (14). In the recompression process, a first reference pixel is compressed as a function of a pixel block parameter. A reconstructed reference pixel value is used in a prediction network when the remaining pixels of the pixel lock are reconstructed before deployment. A first pixel processor compresses precisely a reference pixel that prevents the propagation of a prediction error through the reconstructed block.