MXPA99002346A - Apparatus for processing data elements to be inserted into a frame - Google Patents

Abstract

A first station encodes data as data symbols, rotates the data symbols so that data symbols corresponding to one another across sync portions of data segments of a frame are arranged to be processed together, and inserts the rotated data symbols into data portions of the data segments of the frame such that the frame has a plurality of data segments, wherein each data segment has a segment sync portion and a data portion. A second station processes the data symbols so that corresponding data symbols in a first set of data symbols are processed with a twelve data symbol delay and corresponding data symbols in a second set of data symbols are processed with a twenty-four data symbol delay depending upon the positions of the data symbols in relation to the sync portions.

Description

APPARATUS FOR PROCESSING DATA ELEMENTS TO BE INSERTED IN A FRAMEWORK TECHNICAL FIELD OF THE INVENTION The present invention relates to an apparatus for processing data communicated from a transmitter to a receiver.

BACKGROUND OF THE INVENTION In a terrestrial communication system VSB 8 (ie, a terrestrial vestigial band communication system that transmits symbols each having 1 of possible signal levels), the information is typically transmitted by a transmitting station to a transmitting station. It was receiving station in the air. In an example of such a system, two bits of data to be communicated are encoded by means of the transmitting station as a symbol having one of eight possible signal amplitude levels d so that each byte of data having eight bits s represents four symbols. In a system of these, described in the ATSC digital television standard published on September 16, 1995, each pair of bits is supplied to a precoder and a lattice encoder. One of the bits of each pair of bits is supplied to the precoder, and the other of the bits in each pair of bits is supplied to the lattice encoder. Each of the precoder and the latch encoder incorporates 12 bit delay elements. In this way, the precoder and the lattice encoder can be considered as 12 identical precoders and lattice encoder with (i) an input multiplexer for sequentially connecting two-bit input sets to the identical precoders and lattice encoders and ( ii) an output multiplexer to sequentially connect three-bit output sets to a symbol mapper. The twelve precoders and lattice encoders intercalate the pairs of bits so that each pair of bits in a first byte of data is processed by a prime precoder and lattice encoder, so that a pair of bits in a second byte of data is processed by a second precoder and lattice encoder, ... and so from each pair of bits in the twelfth byte of data is processed by a twelfth precoder and lattice encoder. Each subsequent set of twelve bytes is processed in a similar manner. The precoder and the lattice encoder converts each pair of input bits into three corresponding output bits that are supplied to the symbol mapper. The symbol mapper maps each set of three output bits to a symbol that has a corresponding level of eight levels of eight-level constellation signals The resulting symbols are supplied to a multiplexer which adds synchronization symbols to the data symbols in order to structure the data and the synchronization symbols in a frame. A frame is structured so that it has 31 segments. The first segment of a frame (a framing synchronization segment) includes (i) a portion d segment synchronization containing four segment synchronization symbols and (ii) a portion d field synchronization containing 828 field synchronization symbols. randomly generated pseudor Each of the other 312 segments includes (i) a segment synchronization portion that contains four segment synchronization symbols and (ii) a data portion containing 828 data symbols. After the above, the symbols in the frame structure described above are transmitted, and are received by a receiver. The receiver includes a comb filter and a lattice decoder. The comb filter is present in order to filter the interference that may be caused by the transmission of NTSC channels by the nearest stations. The lattice decoder in the receiver is present in order to decode the symbols in the frames received in their corresponding original bit pairs. The lattice decoder is similar to the lattice encoder in that the lattice decoder processes the symbols of the same byte together . In this way, these symbols must enter the lattice decoder in the correct sequence. As can be seen from the description of the previous frame, the frames that are used in the typical VS 8 system contain only 17.25 groups of data symbols per data segment, where each group contains twelve bytes where each byte contains four symbols. In accordance with the above, each data segment of each frame carries an incomplete group of bytes so that the bytes of the incomplete group are divided between two data segments. As a result, the segment synchronization symbols in the segment synchronization portion of a data segment d separate some data symbols of some bytes and other data symbols of these bytes. In this way, if the data symbols are packed in a frame in the same sequence as they are produced from the symbol mapper, the symbols will not enter the lattice decoder in the correct sequence. In accordance with the above, the lattice decoder in the receiver will not process the symbols of the same bytes together by producing errors in the decoding of the transmitted symbols.

The present invention includes an apparatus for rotating the data to be inserted in the frame structure so that the symbols enter the decoder d lattice in the correct sequence so as to avoid decoding errors due to the presence of symbols of segment synchronization. The present invention also includes a receiver for processing this rotated data.

SUMMARY OF THE INVENTION Therefore, in accordance with one aspect of the present invention, a processing apparatus processes data elements to be inserted into a frame. The frame has a plurality of data segments, each data segment has a synchronization portion and a data portion. The processing apparatus comprises a coding element, a rotating element, and an insertion element. The coding element encodes the data as data elements. The rotation element rotates the data elements so that the corresponding data elements through the synchronization portion of a segment are arranged to be processed together. The insertion element inserts the data elements rotated in the data portions of the frame.

According to another aspect of the present invention, a receiver receives symbols of data accommodated in a frame. The frame has a plurality of data segments. Each data segment has a synchronization portion and a data portion. Each synchronization portion contains four synchronization symbols, each data portion contains 828 data symbols. The data symbols are rotated so that the data symbols of the same bytes separated by a synchronization portion of a data segment are accommodated to be processed together. The receiver comprises a receiving element d and a processing element. The reception element d receives the data symbols of the frame. The processing element processes the corresponding pairs of data symbols of the same bytes together although the data symbols of the same bytes are separated by synchronization portions of each data segment. According to yet another aspect of the present invention, a receiver receives data elements accommodated in a frame. The frame has a plurality of data segments so that each data segment has a synchronization portion and a data portion. The synchronization portion contains S synchronization elements, and each data portion contains an N data element. The data elements are rotated so that the corresponding data elements with each other through each synchronization portion of each data segment are arranged to be processed together. The receiver comprises a receiving element and a processing element. The receiving element receives the frame data elements. The processing element processes the corresponding frames of data elements depending on a separation between the corresponding data elements through the synchronization portions of each data segment.

BRIEF DESCRIPTION OF THE DRAWINGS These and other features and advantages of the present invention will become clearer from the detailed consideration of the invention when taken together with the drawings in which: Figure 1 is a block diagram of an apparatus that embodies the present invention; Figure 2 illustrates a pseudorandom number generator that can be implemented for the data scrambler of Figure 1 in order to randomize the data; Figure 3 is a convolutional byte interleaver that can be implemented for the convolutional byte interleaving of Figure 1; Figure 4 illustrates the symbol grouping as a result of the coding by the byte-to-symbol converter and the lattice encoders of Figur 1; Figure 5 illustrates the interleaved symbols of the Figure 4 to which the segment sync symbol segment has been added; Figure 6 illustrates the symbol byte converter and lattice encoder of Figure 1 in further detail; Figure 7 is a table illustrating the d bytes rotation implemented by the byte rotator of Figure 6; Figure 8 is a table illustrating the "correspondence between the rotation implemented according to the table of Figure 7 and the groups of the rotated data;" Figure 9 illustrates a precoder and lattice encoder that can be used for the precoder and the lattice coders of Figure 6: Figure 10 is a table illustrating the rotation implemented by the symbol rotator of the Figur Figures HA, 11B, 11C, and 11D are a table illustrating the sequence in which the data symbols are inserted into a frame according to the present invention; Figure 12 illustrates the structure of a frame in which data is inserted according to the present invention; and, Figure 13 illustrates a comb filter which introduces the correct amount of delay for the data shown in Figures HA, 11B, 11C and 11D in order for a lattice decoder in a receiver to correctly process the symbols of the same byte together .

DETAILED DESCRIPTION As illustrated in Figure 1, a first station 100 includes an MPE synchronization remover 101 which receives MPEG data packets from an MPEG2 data source (not shown) and which is more fully described in the Application Patent of the United States of America with serial number 08 / 47'9,428 which was filed on June 7, 1995. The MPE data packets arrive at a speed of approximately 12,893 Kpacks per second. These MPEG packets include 187 bytes of MPEG data and one MPEG sync byte. Because the MPEG synchronization is not necessary for processing for the remainder of the terrestrial modem encoder VSB 8 of the present invention, the MPE 101 synchronization remover removes that MPEG synchronization byte from the MPEG packets and passes only the 187 bytes of MPEG data to the data scrambler 102 which randomizes each MPEG data packet supplied by the MPEG 101 synchronizer remover. The data scrambler 102 can implement an EXCLUSIVE bitwise operation between each byte of data received from MPEG 101 synchronizer remover and a pseudo-random sequence. The pseudo-random sequence can be produced, for example, by the random sequence generator shown in Figure 2. The pseudo-random sequence produced by the random sequence generator of Figure 2 is initialized in the first data packet of a frame, and reinitializes every 312 data packets after that. The records of this random sequence generator shown in Figure 2 are initialized at 0xFl80 at the beginning of the framing (where the outputs of the registers X16, X15, X14, X13, X9, X8 are set to the value of one). The pseudorandom sequence generated shown in Figure 2 is advanced for each byte of the input data packet. The pseudo-random sequence generated by this random sequence generator is provided in the DO-D7 outputs that can be connected to the corresponding OR or EXCLUSIVE inputs. The other EXCLUSIVE OR inputs receive the corresponding bits in the bytes of the MPEG 101 synchronizer remover.

The output of the data scrambler 102 s supplies a Reed Solomon 103 encoder. The Reed Solomon 103 encoder calculates 20 parity bytes Reed Solomon adds these 20 bytes to the randomized data packets produced by the data scrambler 102. In accordance with the above , the Reed Solomon 103 encoder produces data packets of which each comprises 207 bytes (ie, 187 bytes of randomized data from scrambler 102 and 20 Reed Solomon parity bytes). The data packets of the Reed Solomo encoder 103 are supplied to a packet-to-byte multiplexer 104. The packet-to-byte multiplexer 104 converts each Reed Solomon data packet of 207 bytes into a continuous byte stream. This byte stream is then processed by a combolutional byte interleaver 105 which is conventionally shown by Figure 3 and which is more fully described in Application 08 / 315,153 which was filed on September 29, 1994. Each block in the Figure 3 is a record that holds a byte. The convolutional byte interleaver 105 is synchronized so that the first byte of the first Reed Solomon data packet enters the uppermost branch of the interleaver shown in Figure 3., the second byte of the first Reed Solomon data packet enters the second branch of the interleaver shown in Figure 3, ... the fifty-twelfth byte of the first Reed Solomon data packet enters the lowermost interleaver branch shown in the Figure 3, the fifty-three byte of the first Reed Solomon data packet enters the uppermost ram of the interleaver shown in Figure 3 and so on. The interleaved byte stream of the interleaved ~ convolutional bytes 105 is supplied to a byte to symbol convert and to a lattice encoder 106 which encodes the data bits in the bytes received as data symbols. As discussed in greater detail hereinafter, the lattice encoder portion of the byte to symbol converter and the lattice encoder 106 is, in effect, 12 lattice encoders in order to accommodate the delay of 12 symbols of the lattice. comb filter that is used in the receiver, such as a second station 109 of Figure 1. That is, the presence of the comb filter in the receiver requires that the byte to symbol converter and the lattice encoder 106 encode the bits data of the bytes of data received as encoded data symbols so that the encoded data symbols of each lattice encoder are separated by the data symbols of the other 11 lattice encoders. Therefore, there are, in effect, 12 lattice encoders. Additionally, the byte to symbol converter, and the lattice encoder 106 must encode the data bit pairs of the data bytes received as encoded data symbols so that the data bit pairs of the same bytes are encoded by the same encoder. Figure 4 illustrates the transmitted data symbols. For example, the symbol EO of group n can represent a symbol that results from the coding by the zero encoder of bits 7, 6 of bytes 0, the symbol EO of group n can represent a symbol that results from coding by the zero encoder of the bits 5, 4 of the zero byte, the symbol EO of the group n + 1 can represent a symbol resulting from the coding by the zero encoder of the bits 3, 2 of the zero byte, and so on. In this way, each EO symbol is separated from the nearest of the other EO symbols by 11 symbols. Similarly, the symbol El of group n-1 may represent a symbol resulting from the coding by the encoder 1 of bits 7, 6 of byte 1, the symbol El of group n may represent a symbol resulting from coding by the encoder 1 of the bits 5, 4 of the byte 1, the symbol El of the group n + 1 can represent a symbol resulting from the coding by the encoder 1 of the bits 3.2 of the byte 1, and so on. Each symbol is separated from the nearest of the other symbols. The eleven symbols. Thus, the zero encoder encodes the symbols of a first byte, the encoder one encodes the symbols of a second byte, the encoder two encodes the symbols of a third byte, and so on. In accordance with the above, the symbols are coded as groups of twelve bytes and transmitted in groups of twelve bytes. As discussed above, each segment includes 832 symbols in the data stream. These 83 symbols include four segment sync symbols and 828 data symbols. In this way, the data symbols in the transmitted data stream are periodically interrupted by segment synchronization symbols as illustrated in Figure 5. Because the transmitted data symbols of each encoder must remain adequately separated, in order to if correctly processed, by the lattice decoder in the receiver, and because the segment synchronization symbols d otherwise would interrupt the proper separation of the data symbols, the present invention rotates the data symbols in each segment in a amount previously determined in order to restore the data symbols the proper separation. For example, this amount of rotation can be zero for the data symbols in the first data segment following the framing synchronization segment, it can be four for the symbols in the next data segment, it can be eight for the data symbols in In the next data segment, it may be zero for the data symbols in the next data segment, and so on. In this way, the data symbol immediately following the synchronization symbols d segment in the data portion of the first data segment following the frame synchronization segment is the EO symbol corresponding to the zero lattice encoder. The following data symbols in this data segment and order are El, E2, E3, E4, E5, E6, E7, E8, E9, El, and Eli com are shown by the group (n - 1) of data symbols e Figure 5. This pattern is repeated throughout this data segment (zero segment) as shown by the lattice column for segment 0 in the table of Figures HA, 11B, 11C, and 11D. However, the data symbol immediately following the segment synchronization symbols (i.e., the segment synchronization symbols SO, SI, S2, and S3 of Figure 5) in the second segment of data following the segment framing sync is the symbol E4 corresponding to the lattice encoder four. The following data symbols in this data segment in order are E5, E6, E7, E8, E9, ElO, Eli, EO, El, E2, and E3 as shown by the group (n) of symbols in Figure 5 This pattern is repeated throughout this segment of data (segment one) as shown by the lattice column for segment one in the table of Figures HA, 11B, 11C 11D. Similarly, the data symbol immediately following the segment synchronization symbols (ie, the symbols of segment synchronization SO, SI, S2 and S3) in the third data segment following the frame synchronization segment is the symbol E corresponding to the lattice encoder eight. The following data symbols in this segment of data in order are E9, ElO, Eli, EO, El, E2, E3, E4, E5, E6, and E7. This pattern is repeated throughout this segment of data (segment two) as shown by the lattice column for segment two in the table of Figures HA, HB, HC and HD. The byte-to-symbol converter and lattice encoder 106, which is shown in more detail in Figure 6, convert the stream of interleaved bytes of the convolutional byte interleaver 105 into symbols having the correct symbol sequence to be properly processed. by the second station 109 (Figure 1) the byte-to-symbol converter and the lattice encoder 106 includes a byte-de-multiplexer 201, a byte-turner 202, such as bit-to-bit byte multiplexers 203, precoders and encoders d lattice 204, a symbol revolver 205, and a multiplexer d symbols 206. The interleaved byte stream of the convolutional byte inlet 105 enters the byte demultiplexer 201. The bytes are grouped by the demultiplexer 201 e groups of bytes that maintain twelve bytes per group. This twelve bytes appear in the outputs BO-BH of byte demultiplexer 201. Each group of twelve byte is rotated by the byte turner 202. Byte rotate 202 has the outputs C0-Cll and rotates the bytes in the outputs B0 - Bll of the demultiplexer d bytes 201 according to the table illustrated in l Figure 7. As shown in the table in Figures HA, 11B, HC and HD, the order of the bytes in the interleaved byte stream supplied to the byte convert The symbol and lattice encoder 106 is changed due to symbol rotation which is implemented because of the segment synchronization symbols at the beginning of each data segment. A rotation of the bytes in each byte group supplied from the byte-multiplexer 201 to the byte-turner 202 is desirable in order to restore the order of the bytes after the adjustment that is made due to the segment synchronization symbols.

As shown in the table of Figure 7, the byte rotator 202 rotates the bytes in the BO-Bll outputs and is zero, four, or eight positions. This rotation of bytes is implemented in order to properly assign the bytes to the correct lattice encoder. The rotation of bytes follows a periodic pattern that is repeated after 12 segments of the frame. The duration of each rotation d bytes follows a pattern of 18, 17, 17, 17 of repetition. This is, as shown by the table in Figure 8, the first eighteen groups of twelve bytes received by the rotator d bytes 202 are rotated to zero, the next seventeen group of twelve bytes received by the 202 byte rotator is rotated by four, the next seventeen groups of twelve byte received by the 202 byte turner are rotated by eight, the following seventeen groups of twelve bytes received by the 202 byte turner are rotated by zero, the next eighteen groups of twelve bytes, received by The rotator d bytes 202 rotate by four, and so on, so that this pattern of 18, 17, 17, 17 ... repeats every doc data segments. This byte rotation is shown in Figures HA, HB, HC and HD. Figures HA, HB, 11C and 11 illustrate the first five data segments following the framing synchronization segment of a frame. The last eight data symbols of the data segment zero (ie, the data symbols 816-827 of Figure HD) correspond to the bit pairs 7.6 of the bytes 204-215. These bytes 204-215 are completed by the first 36 data symbols in the data segment one. The 828 data symbols in the zero data segment and the first 36 data symbols in the data segment one represent the first eighteen groups of twelve bytes of data processed by the byte turner 202. As indicated above, the bytes 202 applies a zero rotation to these first eighteen groups of twelve bytes. These first 216 bytes are applied in order (without rotation) to the corresponding lattice encoders E0 - Eli. The byte turner 202 then applies a rotation of four to the next seventeen groups of bytes of data received by the byte turner 202 so as to return the bytes to their original byte order. These bytes comprise the bytes 216 - 419. This rotation of four causes these bytes to be coded by the corresponding lattice encoders E4 - E3. In this way, the data symbol 36 in the data segment one corresponding to the bits 7,6 is in the byte 216 and corresponds to the lattice encoder 4. In accordance with the above, the order of the bytes is restored in the data segment one starting with the data symbol 36. These seventeen groups of twelve bytes and end with the twenty-three data symbol of data segment two. The byte turner 202 then applies a rotation of eight to the next seventeen groups of twelve bytes received by the byte turner 202 so as to return the bytes to their original byte order. These bytes comprise bytes 420-623. This rotation of eight causes these bytes to be encoded by the corresponding lattice encoders E8-E7. In this way, the data symbol twenty-four in the data segment two corresponding to the bits 7,6 is in the byte 420 and corresponds to the lattice encoding eight. In accordance with the above, the order of the bytes is restored in the data segment do beginning with the data symbol twenty-four. This seventeen groups of twelve bytes end with the symbol d data eleven of data segment three. The byte turner 202 then applies a zero rotation to the next seventeen doc bytes groups received by the byte turner 202 so that it returns the bytes to their original byte order. These byte comprise the bytes 624 - 827. This zero rotation causes these bytes to be coded by the corresponding lattice d coders E0 - Eli. . In this wayThe data symbol twelve in the tre data segment corresponding to the bits 7.6 is in the byte 624 corresponds to the zero lattice encoder. This seventeen groups of twelve bytes terminate with data symbol 827 of data segment three. In accordance with the above, the order of the bytes is restored in the three data segment starting with the data symbol twelve. The bit-to-bit byte multiplexers multiplex each data byte supplied in the output lines CO-Cll by means of the byte rotator 202 to four corresponding pairs in series of bits. The s bits are supplied by the byte multiplexer to bit pairs 203 in the DO-DH outputs and are processed by the precoders and the grid encoders 204. The precoders and the latch encoders 204 convert the bit pairs into the DO outputs. - DH for the corresponding sets of three output bits and maps the sets of three output bits into data symbols. In this mode, each data symbol has one of eight possible levels defined by three bits. The lattice encoder pre-encoders 204 include the lattice encoder precoders E0-Eli which supply data symbols on the corresponding outputs E0 Eli. Figure 9 illustrates a precoder and a lattice encoder. The precoder and the lattice encoder of FIG. 9 may be replicated twelve times so as to separately code each bit-pa stream in the corresponding DO-DH outputs of byte multiplexer to bit pair 203. In this case, the The delay elements of the pre-encoder and lattice decoder of Figure 9 are single-bit delay elements. According to the above, the bit X2 of a bit pair in the current of bit pairs DO is encoded by the precoder of the precoder and the encoder d lattice EO as an output bit Z2, and the bit XI of the pair d bits in the current of bit pairs DO is encoded by the lattice encoder of the precoder and the lattice encoding EO as the output bits Z1 and Z0. A symbol mapping (not shown) of the precoder and lattice encoder E8 maps the output bits Z2, Z1, Z0 to a corresponding data symbol. Similarly, bit X2 of a bit pair in the bit-pair stream DI is encoded by the precoder of the lattice encoder precoder El as an output bit Z2 and bit XI of the bit pair in the latch current. bit pairs Di is encoded by the lattice encoder of the precoder and the lattice encoder El as the output bits Zl Z0. A mapper of precoder and lattice encoder symbols maps these output bits Z2, Z1, Z0 into a corresponding data symbol. The remaining byte streams are processed in a similar manner by other lattice encoders and encoders E2-Eli. The data symbols on the EO Eli output lines of the precoder and the grid encoders 20 are rotated by the symbol rotator 205 according to the table shown in Figure 10. This symbol rotation provides for the separation of twelve symbols of each symbol stream encoded within a segment and through d the segment synchronization symbols. Each application is applied to all sixty-nine groups of twelve data symbols in a data portion of a data segment. In accordance with the foregoing, the data symbols in the data portion of the first data segment (zero segment) following the frame synchronization segment is rotated by zero, the data symbols in the second segment data portion of the data segment. data (segment one) are rotated by four, the data symbols in the data portion of the third data segment (segment two) are rotated by eight, the data symbols in the data portion of the fourth data segment (segment three) ) are rotated by zero, and so on, through all 312 data segments of a frame. Thus, with reference to Figure 10 to Figures HA, HB, HC, and HD, the zero segment data symbols (the first data segment following the frame synchronization segment) are rotated by zero. In accordance with the above, the encoded data symbols of the EO, El, E2, ... Eli encoders of Figure 6 appear at the outputs FO, Fl, F2, ... Fll of the symbol revolver 205 and are transmitted in the order EO - Eli. However, the symbols in the data segment one (the second data segment following the framing synchronization segment) are rotated by four. In this way, the encoded data symbols of the encoders E4, E5, E6, ... Eli, EO, ... E3 of Figure 6 appear in the outputs FO, Fl, F2, ... Fll of the symbols 205 and are transmitted in the order E4, ... E3. Furthermore, the data symbols in data segment two (the third data segment following the frame synchronization segment) are rotated by eight. In this way, the data symbols encoded from the encoders E8, E9 / ElO, Eli, EO, ... E7 of Figure 6 appear at outputs FO, Fl, F2, Fll of the spinner symbol 205 and are transmitted in the E8 order, ... E7. The data symbols in data segment three (the fourth data segment that follows the frame synchronization segment) are rotated by zero. In accordance with the above, the encoded data symbols of the encoders E0, El, E2, ... Eli of Figure 6 appear at the outputs F0, Fl, F2, ... Fll of the symbol revolver 205 and are transmitted in the order E0 - Eli.

With this rotation arrangement, the first data symbol d in the data segment one (ie the data symbol d corresponding to bits 5.4 of the 208 byte) is processed with the symbol that is transmitted twelve previous symbols (e say. The data symbol corresponding to bits 7.6 of byte 208). Similarly, the second data symbol e data segment one (ie, the data symbol qu corresponds to bits 5.4 of the 209 byte) is processed with the data symbol that is transmitted twelve symbols before (e said, the data symbol corresponding to bits 7,6 of byte 209) also, each of the data symbols corresponding to bits 5, 4 of bytes 210-215 s process in second station 109 with bits 7 , 6 of the 210-215 bytes which are presented above to the four segment symbols that are inserted at the beginning of data segment one. However, the corresponding data symbol bits 5.4 of the byte 204 are separated by twenty-three other data symbols of the symbol corresponding to the bits 7 of the byte 204. In accordance with the foregoing, as will be discussed later herein, the ninth, tenth, eleventh, and twelfth data symbols in a data segment following the four segment synchronization symbols at the beginning of the data segment are presented twenty-four symbols after the above data symbols of the corresponding lattice encoders . Therefore, this delay of twenty-four symbols must be taken into account so that these data symbols corresponding to the bits 5.4 in these bytes 204 207 can be processed with the corresponding symbols bits 7.6 of the corresponding bytes 204 - 207 near the end of the zero data segment. After this in the data segment one, the delay of twelve symbols can be used again by the second station 109. In accordance with the foregoing, the d symbol revolver 205, together with the delay of twelve and twenty-four symbols imposed by the second station 109 ensures that the data symbols of the same bytes are processed by the same lattice encoder and are therefore processed together. Similarly, the byte turner 202 ensures that by following this transition through a segment synchronization portion, the bytes are rotated so that they are again in ascending order instead of in mixed order. A multiplexer 206 multiplexes the data symbols provided by the symbol turner 205 back into a stream of data symbols that is provided to a frame structure inserter 107 (Figure 1). The framing structure inserter 107 inserts the framing structure by adding the framing synchronization segment and the segment synchronization symbols to the data symbols in the framing structure that has been discussed above and which is shown in Figure 12 In accordance with the above, the framing includes a framing synchronization segment (which is the first segment in a frame) and 312 data segments. The beginning of each segment includes four segment synchronization symbols. A transmitter 108 receives the frames from the frame structure inserter 107, performs certain signals conditioning the data contained in the frames, and transmits the frames of symbols in the framing structure shown in FIG. 12. The second station 109 receives the information transmitted by the first station 100 in order to decode the symbols in their corresponding pairs d bits X2 / X1. The second station 109 includes, among others, a receiver 110 and a comb filter and a lattice decoder 111. The receiver 110 performs certain signal conditioning such as demodulation. E comb filter and lattice decoder 111 filters interference from nearby NTSC stations decodes the symbols to retrieve the original bits. A 1300 comb filter, which is the comb filter portion of the comb filter and the lattice decoder 111, s shown in FIG. 13. The lattice decoder portion of the comb filter of the lattice decoder 111 may be a conventional Viterbi decoder. The comb filter 1300 includes a first filter portion 1302 having a delay element 1304 to impose a delay of twelve symbols on the data symbols processed by the comb filter. The comb filter 130 also includes a second filter portion 1306 having an additional delay element 1308 for imposing a second delay of twelve symbols on the data symbols processed by the comb filter 1300. The first and second filter portions 1302 and 1306 can be separated by a conventional equalizer. A multiplexer 1310 selects the first filter portion 1302 for all data symbols in a data segment except for the ninth through the twelve data symbols that follow the four segment synchronization symbols at the beginning of each data segment. . In accordance with the above, all data symbols in the data segment except for the ninth through twelve data symbols following the four segment synchronization symbols at the beginning of the data segment are processed with a delay of twelve symbols. The multiplexer 1310 otherwise selects the second filter portion 1306 from the ninth to the twelfth data symbol after the four segment synchronization symbols at the beginning of the data segment. In accordance with the above, from the ninth to the twelfth data symbol following the four segment synchronization symbols at the beginning of the data segment are processed with a delay of twenty-four symbols. Some modifications of the present invention have been discussed previously. Other modifications may be devised by those who practice the technique of the present invention. For example, a single precoder and lattice encoder can be used for the precoder and the lattice encoders 204 (EO-El) if the delay elements in the precoder and lattice encoder shown in Figure 9 are delayed elements of twelve. bits. Because the delay element is twelve bits long, the precoder the lattice encoder shown in Figure 9 is the equivalent of twelve grid pre-encoders and coders 204 (EO-Eli) shown in Figure 6. For example, the precoder and the lattice encoder of FIG. 9 processes the bits 7 (X2) and 6 (XI) of the zero byte, twelve symbols later processes the bits 5 (X2) and 4 (XI) of the zero byte. In the same way, the lattice encoding precoder shown in Figure 9 processes the bits 7 (X2) and 6 (Xl) of the one byte, and twelve symbols after processes the bits 5 (X2) and 4 (XI) of the byte one . If the precoder and the lattice encoder of twelve delay symbol shown in FIG. 9 are used, the by-multiplexer of byt 201 can be eliminated, the byte rotator 202 can comprise, for example, a memory and a router which writes the When the bits are read and the bits in the memory are read out that the bytes are rotated as discussed above, the byte multiplexer to the bit pair 203 can be deleted, the symbol tumbler 205 can comprise, for example, a memory and a address that write the symbols and read the symbols in the memory so that the symbols are rotated as discussed above, and the symbol multiplexer 206 can be deleted. Moreover, although the present invention has been specifically described herein in terms of data symbols having corresponding ones of eight levels of possible signals, it is possible that the transmitted data are data elements having any number of possible signal levels. . Also, specific encoders and decoders have been described herein. Nevertheless, other types of encoders and decoders can be used in the present invention. Additionally, the byte turner 202 can be eliminated. If so, the second station 109 can be accommodated to recognize the correct correspondence between the data symbols and the bytes. The functions of the blocks described herein may alternatively be implemented and software. In accordance with the foregoing, the description of the present invention will be considered illustrative only for the purpose of teaching those skilled in the art the best way to carry out the invention. The details may be varied substantially without departing from the spirit of the invention, and exclusive use of all modifications within the scope of the appended claims is reserved.

Claims (17)

1. CLAIMS 1. A processing apparatus for processing data elements to be inserted in a frame, wherein the frame has a plurality of data segments in which each data segment has a synchronization portion and a portion of data, comprising and processing apparatus: an encoding element for encoding the data as data elements; a rotation element for rotating the data elements so that the data elements corresponding to each other through a synchronization portion of a segment are arranged to be processed together and, an insertion element for inserting the data elements rotated in the framing data portions.
2. 2. The processing apparatus of claim 1 wherein a synchronization portion d each segment of a frame contains S synchronization elements, wherein the rotation element rotates the data elements to be inserted in a first segment by zero, in where the rotation element rotates the data elements to be inserted in a second segment by S, where the rotation element rotates the data elements to be inserted in a third segment by 2S, and where the first, the second, and the third segment are presented in order in the frame.
3. 3. The processing apparatus of claim 2 wherein the data element byte contains D data elements, where data elements in B bytes of data elements are interleaved, e where DB is a group of data elements. , where the insertion element inserts N data elements in the data portion of the first segment so that the first segment contains N / DB groups of data elements, where N / DB produces a remainder of R data elements, where the insertion element inserts N data elements in the second segment so that the first DB-R data element inserted in the data portion of the second segment are from a group of data elements inserted in the first segment, in where the rotation element rotates the bytes of data elements inserted in the first segment by zero, where the rotation element rotates the bytes d the data elements to be inserted in the second segment by S after d e the first DB-R data elements inserted in the second segment, where the rotation element rotates the bytes of the data elements inserted in the third segment by 2S following the first DB-2R data elements to be inserted e the third segment.
4. 4. The processing apparatus of claim 1 wherein the rotation element comprises a byte rotator and a symbol rotator.
5. 5. The processing apparatus of claim 4 wherein a synchronization portion of each segment of a frame contains S synchronization symbols, wherein the symbol revolver is set to rotate the data symbols to be inserted into a first segment by zero, where the symbol revolver s accommodates to rotate the data symbols that are to be inserted into a second segment by S, where the symbol dizer is accommodated to rotate the data symbols that are to insert a third segment by 2S, and where the first, the second, and the third segment are presented and ordered in the frame.
6. 6. The processing apparatus of claim 4 wherein a data symbol byte contains D data symbols, wherein the data symbols in B bytes of data symbols are interleaved, wherein DB e a data symbol group. , where the insertion element inserts N data symbols in the data portion of the first segment so that the first segment contains N / DB data symbol groups, where N / DB produces a remainder of R data symbols, wherein the insertion element inserts N data symbols in the second segment so that the first DB-R data symbols inserted in the data portion of the second segment are d a group of data symbols inserted in the first segment, where the byte turner is set to rotate the bytes of the data symbols to be inserted in a first segment by zero, where the byte turner s accommodates to rotate the bytes of the data symbols that are going to insert in the second segment by S after the first DB-R data symbols inserted in the second segment, and where the byte turner is arranged to rotate bytes of the data symbols to be inserted in the third segment by 2S after the first DB - 2 data symbols to be inserted in the third segment.
7. The processing apparatus of claim 6 wherein a synchronization portion of each segment of a frame contains S symbols, wherein the symbol rotator is arranged to rotate the data symbols to be inserted in a first segment by zero, where the symbol revolver is arranged to rotate the data symbols to be inserted in a second segment by S, where the symbol rotator is arranged to rotate the data symbols to be inserted a third segment by 2S and where the first, second, and third segments are presented in order in the frame.
8. 8. A receiver for receiving data symbols accommodated in a frame, wherein the frame has a plurality of data segments, wherein each data segment has a synchronization portion and a data portion, wherein each synchronization portion contains symbols of data. synchronization, wherein each data portion contains N data symbols, wherein the data symbols are rotated so that the data symbols of the same bytes separated by a synchronization portion of a data segment are accommodated to be processed together , wherein the receiver comprises: a receiving element for receiving the data symbols of the frame; and, a processing element for processing the corresponding pairs of the data symbols of the same bytes together even when the data symbols of the same bytes are separated by synchronization portions of each data segment.
9. The receiver of claim 8 wherein the frame data symbols are rotated so that the processing element processes the corresponding pairs of the data symbols of the same bytes together when the data symbols of the same bytes are separated by synchronization portions of each data segment.
10. 10. The processing apparatus of claim 9 wherein a synchronization portion of each segment of a frame contains S synchronization symbols wherein the data symbols inserted in a first segment are rotated by zero, wherein the data symbols inserted in a second segment is rotated by S, where the data symbols inserted in a third segment are rotated by 2S, and where the first, the second, and the third segment are presented in order in the frame.
11. The processing apparatus of claim 9 wherein a data element byte contains D data symbols, wherein the data symbols in B bytes of the data elements are interleaved, where DB is a group of data elements. data, where N data symbols are inserted into the data portion of the first segment so that the first segment contains N / DB groups of data symbols, where N / DB produces a remainder of R data symbols, where N data symbols are inserted in the second segment so that the first DB-R data symbols inserted in the data portion of the second segment are from a data symbol group inserted in the first segment, where the symbol bytes of data inserted in the first segment are rotated by zero, wherein the bytes of the data symbols inserted in the second segment are rotated by S after the first DB-R data symbols inserted in the second segment, and wherein the bytes of the data symbols inserted in the third segment are rotated by 2 after the first DB-2R data symbols to be inserted in the third segment.
12. 12. The processing apparatus of claim 11, wherein a synchronization portion of each segment of a frame contains S synchronization symbols, wherein the data symbols inserted in a first segment are rotated by zero, wherein the data symbols inserted in a second segment are rotated by S, e where the data symbols inserted in a third segment are rotated by 2S, and where the first, second, and third segments are presented in order in the frame.
13. 13. The receiver of claim 8, wherein = 4, where N = 828, where the corresponding data symbols in a first set of data symbols are separated by eleven symbols, and where the corresponding data symbols in a second set of data symbols are separated by twenty-three symbols.
14. The receiver of claim 13 wherein the data symbols of a first data segment are rotated by zero, wherein the data symbols of a second data segment are rotated by four, wherein the data symbols of a third data segment is rotated by eight, where the first, second and third segment are presented in order in the received frame, and where the processing element is accommodated to process the ninth, tenth, eleventh, and twelfth data symbols in the data portion of the second data segment as data symbols of the second set and pair ?, processing all the other data symbols in the data portion of the second data segment as data symbols of the first set.
15. The receiver of claim 13 wherein a data symbol byte contains four data symbols, wherein the data symbols in each twelve bytes of data symbols are interleaved, wherein a group of data symbols contains forty and eight bytes of data symbols, wherein the last twelve data symbols in the data portion of the first data segment and the first thirty six data symbols in the data portion of the second data segment belong to the same twelve bytes of data symbols, wherein the first eighteen groups of twelve bytes of the data symbols beginning with the first data segment are rotated by zero, wherein the next seventeen groups of data symbol bytes are rotated by four, wherein the next seventeen groups of bytes of data symbols are rotated by eight, where the next seventeen groups of twelve bytes of the data symbols are rotated by zero, and in do The next eighteen groups of twelve bytes of data symbols are rotated by four.
16. 16. The receiver of claim 15 wherein the data symbols of a first data segment are rotated by zero, wherein the data symbols of a second data segment are rotated by four, wherein the data symbols of a third data segment is rotated by eight, where the first, second, and third segments are presented in order in the received frame, and where the processing element is accommodated to process the ninth, tenth, eleventh and twelfth symbols data in the data portion of the second data segment as data symbols of the second set and for processing all other data symbols in the data portion of the second data segment as data symbols of the first set. The receiver of claim 8 wherein the corresponding data symbols in a first set of data symbols are separated by eleven symbols, wherein the corresponding data symbols in a second set of data symbols are separated by twenty-three symbols, and wherein the processing element is arranged to process the corresponding data symbols in the first set with a delay of twelve symbols and to process the corresponding symbols in a second set with a delay d twenty-four symbols. • k -k -k -k -k