MXPA98007223A - Apparatus for sampling and exhibiting an auxiliary image with a principle image - Google Patents

Abstract

The present invention relates to an apparatus for displaying a combined image of an auxiliary image and a main image includes a source of a main image signal, and a source of samples representing an auxiliary image signal. A quincunx sub-sampler is coupled to the sample source of the auxiliary image. A signal combiner is coupled to the signal source of the main image and the quincunx sub-sampler. The sample combiner combines the signal from the main image and a signal representing the samples subsampled in quincunx, to generate a signal representing a combined image of the main and auxiliary images.

Description

APPARATUS FOR SAMPLING AND EXHIBITING AN AUXILIARY IMAGE WITH A MAIN IMAGE The present invention relates to an image-in-picture system that uses quincunx sampling to improve horizontal resolution. Today's visual display systems include the ability to display a small auxiliary image in addition to a larger main image. This smaller image can be displayed within the boundaries of the larger main image, in which case, this system is called an image-in-picture (PIP) system, or the smaller image can be located outside (for example, towards the left or right side of the main image), in which case, the system is called an out-of-picture (POP) image system. The main and auxiliary images can be derived from the same image source, such as a frozen frame PIP image of the main image, or can be derived from a separate source, such as a system, where a tuner tunes to a video signal that is displayed as the main image, and a second tuner tunes to a second video signal, regardless of the first tuner, that is displayed as the PIP image. A PIP or POP system operates by storing the compressed image data representing the auxiliary image, as presented in the auxiliary video signal, and then replacing this compressed image data with the signal of the main image in the portion of the main image that is designed to display the auxiliary image. The system must supply a sufficient amount of memory to store the data of the auxiliary image from the moment it is presented in its video signal until the moment it is displayed in the main image. Known systems provide sufficient memory to contain an auxiliary video data frame or field. Because memory is relatively expensive, it is desirable to minimize the amount of memory required. To decrease the amount of memory required, the known PIP and POP systems sub-sample the auxiliary video signal, and store only one field of sub-sampled auxiliary video data. A visual display method is used, complementary to the sub-sampling method to generate the signal of the visual display image for the inserted PIP or POP image. However, the known sub-sampling techniques consist of 'taking a sample, discarding N samples' directly, repeated by each line in the auxiliary video signal. This undesirably decreases the horizontal resolution of the PIP or POP image. This, in turn, decreases the perceived quality of the PIP or POP image displayed. A sub-sampling method that can increase the horizontal resolution of a PIP or POP image is desirable, without increasing the amount of memory needed to store the PIP or POP image data to be subsequently displayed with the main image. In accordance with the principles of the present invention, an apparatus for displaying a combined image of an auxiliary image and a main image includes a source of a main image signal and a source of samples representing an auxiliary image signal. A quincunx subsample is coupled with the auxiliary image sample source. A signal combiner couples with the main image signal source and the quincunx subsampler. The sample combiner combines the signal from the main image and a signal representing the sub-sampled samples in quincunx, to generate a signal representing a combined image of the main and auxiliary images.

In the drawing: Figure 1 illustrates a visual display image illustrating a main image and an image in image (PIP), and embodying the present invention. Figure 2 is a diagram, partially in the form of blocks, partially in logical form, of a portion of a PIP system embodying the present invention. Figure 3 is a more detailed illustration of the PIP visual display image, which illustrates the qumcunx sampling. Figure 4 is a diagram of the waveform of the main video and PIP signals, and of the PIP memory access addresses. Figures 5 and 6 are more detailed illustrations of portions of a PIP visual display image, illustrating a problem using quincunx sampling for a PIP image, and the solution. Figure 7 is a diagram, partially in the form of blocks and partly in logical form, of an encoder for generating PIP data to be stored in a field memory. Figure 8 is a diagram, partly in the form of blocks and partly in logical form, of a decoder, for generating PIP data to be inserted into a main image. The illustrated embodiment is described in terms of an image-in-picture (PIP) system, which produces an image as illustrated in Figure 1. However, the principles of the present invention are equally applicable to other multiple imaging systems, such as as an out-of-picture image (POP), where a small image is placed outside (ie, to the left or right) of a main image. Figure 1 illustrates a PIP visual display image including a main image and an auxiliary image, and embodying the present invention. In Figure 1, a main image 2 is shown as it could be displayed in a visual display device, such as a television receiver or monitor. The main image 2 can be generated by known signal processing circuits, including a tuner that responds to a television signal received from the antenna or from a cable. Also in Figure 1 there is shown a second image 4 which is inserted in the lower left corner of the main image 2. The auxiliary image 2 in the illustrated embodiment is called an image in image (PIP) image. The PIP image is also generated by the known signal processing circuits, possibly including a second tuner that responds to a second television signal received from an antenna or a cable. In an alternative way, the second tuner can be incorporated into a separate video cartridge recorder (VCR). A signal representing the PIP image 4 is combined with the signal representing the main image 2 in a known manner, and the combined signal is supplied to a visual display device, which exhibits the image illustrated in Figure 1. The Figure 2 is a diagram, partially in the form of blocks, partially in logical form, of a portion of a PIP system embodying the present invention. In Figure 2, a source 102 of a signal representative of the main video image includes an output terminal coupled with the respective input terminals of a synchronization component processor 103 and a video component processor 104. A terminal The output of the synchronization component processor 103 is coupled to a main time signal generator 106. An output terminal of the video component processor 104 is coupled to a first data input terminal of the multiplexer 108. An output terminal of the multiplexer 108 produces the combined video signal, and is coupled with a visual display device (not shown) in a known manner. The respective output terminals of the main time signal generator 106 are coupled to a clock input terminal of the video component processor 104, and to a control input terminal of the multiplexer 108. A source 110 of an image signal PIP video is coupled to an input terminal of an analog-to-digital converter of PIP 112. An output terminal of the analog-to-digital converter of PIP 112 is coupled to the respective input terminals of a PIP video processor 113 and a PIP time generator 114. An output terminal of the video processor PIP 113 is coupled to a data input terminal of a quincunx subsampler 116. An output terminal of the subsampler 116 is coupled to a data input terminal of a Field memory 120. A data output terminal of the field memory 120, is coupled with a data input terminal of an inserted visual display display signal generator 124. An output terminal of the visual display generator 124 is coupled to a second data input terminal of the multiplexer 108. The terminals of respective outputs of the PIP time signal generator 114 are coupled to the corresponding input terminals of the subsampler 116 and a write address generator 118. The write address generator 118 has an output terminal coupled to the address input terminals of the sub-sampler 116 and the field memory 120 respectively. The respective output terminals of the main time signal generator 106 are coupled to the corresponding input terminals of a read address generator 122 and the visual display generator 124. The read address generator 122 has an output terminal coupled with the terminals respective reading address input of sub-sampler 116 and field memory 120. Referring to both Figure 1 and Figure 2, the main video signal from the main video signal source 102 includes a video component and a synchronization component. The processor of the synchronization component 103 extracts and processes the signal from the synchronization component. The synchronization signal is supplied to the timing generator 106, which generates a timing signal synchronized with the clock signal at 4 • fsc (the color subcarrier frequency). This timing signal is coupled with the main video processor 10. The video processor 104 processes the main video signal in a known manner. For example, in a preferred embodiment, the main video processor 104 contains a luminance / chrominance signal separator, such as a comb filter, which produces separate luminance and chrominance signals. The main video processor 104 may also include a demodulator for the chrominance signal, and produce separate I and Q, or U and V signals, and in addition may include a color signal matrix, and generate color component signals R, G and B. Also, in the preferred embodiment, the main video processor 104 includes an analog-to-digital converter, and can perform part of its processing, including comb filtering, in digital circuits. In an alternative way, it is also possible not to perform video processing absolutely. In this case, the main video signal is passed, unchanged, from the main video signal source 102 to the multiplexer 108. The main time signal generator 106 also produces a signal indicating when the visual display device is scanning the portion of the visual display image where the inserted PIP image will be located. This signal is supplied to the control input terminal of the multiplexer 108. When the main picture is to be displayed, the multiplexer 108 is conditioned to couple the main video processor 103 to its output terminal, and when the output is to be displayed. PIP image, the multiplexer 108 is conditioned to couple the visual display generator 124 with its output terminal. Simultaneously, the PIP video signal is processed by the analog-to-digital converter of PIP 112, to produce samples representing the PIP video signal at a frequency of 4-fsc. These samples are processed by the PIP time signal generator 114 and the PIP video signal processor 113. Specifically, the PIP time signal generator 114 identifies, extracts and processes the PIP synchronization component. The PIP video processor 113 comprises digital circuits that process the samples of the PIP video signal from the analog to digital converter PIP 112. In a manner similar to the main video processor 104 described above., in a preferred embodiment, the video processing includes circuits, such as a comb filter, to separate the luminance and chrominance components of the PIP video signal. The PIP video processor 113 may further include a demodulator to separate the chrominance components I and Q, or U and V. Alternatively, the PIP video processor 113 may not perform further processing of the PIP video signal samples. , in which case, the output of the PIP analog to digital converter 112 is coupled directly to the input terminal of the quincunx subsampler 116. This PIP image sampling sequence from the PIP video processor 113 is sub-sampled by the quincunx subsampler 116 , in response to a timing signal from the PIP timing signal generator 114, and the read and write addresses of the field memory, in a manner that will be described in more detail below. In general, each field of the PIP sample sequence is sub-sampled in an independent manner, as follows. In the vertical direction, three vertically aligned horizontal PIP samples are filtered to generate a single subsampled PIP sample. In a preferred embodiment, the three vertically aligned samples are averaged. In the horizontal direction, the filtered sequence is sub-sampled in a ratio of 6: 1, that is, a sample is saved, and five samples are discarded in a manner that will be described in more detail below. The timing of the horizontal sub-sampling is controlled in the manner described in more detail below, to provide the quincunx sampling. It is possible to sub-sample in quincunx only one component of the PIP image sample stream. For example, in the preferred embodiment, the sample stream of the luminance component is sub-sampled in quincunx. A field of the subsampled PIP samples from the subsampler 116 is stored in the field memory 120. Under control of the main time signal generator 106, the visual display generator 124 extracts the previously sampled samples stored from the memory field 120, when the PIP image 4 is being displayed. The visual display generator 124 performs an inverse function to the sub-sampling performed on the quincunx sub-sampler 116, to generate a sequence of samples representing the inserted auxiliary image. In addition, the visual display generator 124 includes a digital-to-analog converter, if the main video signal 104 is maintained in the analog domain. The output signal from the visual display generator 124, accordingly, corresponds to the output signal from the main video processor 104. That is, if the output signal from the main video processor 104 is from the respective analog signals. of luminance and chrominance (as in the preferred embodiment), then the output signal from the visual display generator 124 is also from the respective analog luminance and chrominance signals. During the time in which the inserted PIP image 4 is to be displayed, the multiplexer 108 is conditioned to pass the decoded samples from the decoder 124 to its output terminal. When the main image 2 is being displayed, the main video samples are passed from the main analog converter 104, through the multiplexer 108. In the preferred embodiment, when the main image and PIP signals comprise analog luminance and chrominance signals. respective, the multiplexer 108 comprises two analog signal switches, which switches between the analog luminance components of the main video and PIP video signals, and the other which switches between the chrominance analogue components of the main and the video signals. PIP video If the main chrominance signal is demodulated in I and Q signals, or U and V, or is further dematrixed in the signals of color components R, G and B, then three multiplexers are provided, one for each component. As described above, when horizontal sub-sampling is performed, the horizontal resolution of the image represented by the sub-samples has a low horizontal resolution. The use of quincunx sampling, described below, is a method to overcome the low horizontal resolution of the subsampled PIP image. Figure 3 is a more detailed illustration of the received PIP visual display image 4, illustrating the quincunx sampling. As described above, in the preferred embodiment, the luminance and chrominance components of the PIP video signal are separated in the respective sample streams. The upper portion of Figure 3 illustrates the sampling pattern of a portion of a frame of the sample sequence of the PIP image. Each line in Figure 3 represents the results of vertically filtering (for example, averaging) three vertically adjacent lines in each field. Each line of vertically filtered samples (referred to simply as lines below) is represented by a horizontal line of "X" or "+" (simply referred to as samples below). Each of these samples is produced in a cycle of the timing signal PIP 4 • fsc (PIP CLOCK), illustrated below the illustrated portion of the received PIP visual display image, and consists of a portion representing the luminance component of that sample, and a portion that represents the chrominance component of that sample. Each "X" represents a sample taken in the horizontal sub-sampling process, and each "-" represents a skipped sample. Because the PIP video image is interlaced, adjacent vertically filtered horizontal lines are transmitted in the successive fields. In the uppermost line of Figure 3, the samples, "X", are taken every sixth sample, with the sample to the left being the first sample taken. Then five "+" samples are skipped, before the next "X" sample is taken. This pattern is repeated throughout the rest of the line. The samples of the third and fifth lines vertically filtered illustrated, are taken in the same set of horizontal locations of the first line. Due to entanglement, these lines are all from the same field. Therefore, each line of a field is sampled in an identical pattern. This pattern is designated as the SPI sample pattern. In the second line of Figure 3, in the next field, the first sample taken is the fourth sample, "X". Then, five samples are skipped, "+", before the next sample is taken. This pattern is repeated throughout the rest of the line. The samples of the fourth line are taken in the same set of horizontal locations as the second line. Samples of this field are taken from. the horizontal locations midway between the horizontal locations of the samples of the adjacent lines from the previous field. This pattern, designated as the sample pattern SP2, can be produced by delaying the subsampling timing signals that generate the SPI sample pattern by three PIP clock cycles 4-fsc. The use of sample patterns SPI and SP2 results in a sampling pattern called quincunx sampling, and increases the perceived horizontal resolution of the PIP image, providing samples from more horizontal locations in the PIP image. The samples taken illustrated as "X" in the upper portion of Figure 3 are stored in the memory 120 (of Figure 2). The lower portion of Figure 3 illustrates the method for displaying the inserted PIP samples previously stored in the memory 120 (of Figure 2), as described above. The lower portion of Figure 3 illustrates a portion of the PIP image 4, as shown in the combined image illustrated in Figure 1. Each le illustrated in the lower portion of Figure 3 occurs at a time of main timing signal 4 • fsc (MAIN CLOCK). In general, each le is displayed, as represented by an "X", and then repeated immediately, as represented by an "O" immediately to the right of its corresponding "X". The le is displayed to the left of the uppermost line of the illustrated portion of the PIP image 4, "X". This le is then repeated in the next main clock time 4-fsc, "O". Then the next previously stored le is displayed, "X", and immediately repeats, "O". This is repeated for the rest of this PIP image line. This pattern is repeated for the third and fifth (and all odd numbers) lines of the PIP image. These lines are in the field as those in the first line. Therefore, as for the PIP video signal ling process described above, each line of a field is displayed in the pattern. This pattern is designated as the visual display pattern DPI, and corresponds to the SPI le pattern, described above. The le to the left of the second line is an "O", which is a repetition of a previous le (not shown), immediately to its left. The second le of the second line, "X", is displayed, and then repeated immediately in the next time of the main clock 4-fsc, "0". Then the next previously stored le, "X", is displayed, and "0" is repeated. This is repeated for the rest of this inserted PIP image line. The pattern is repeated for the fourth (and all even numbers) line of the PIP image. This pattern is designated as the visual display pattern DP2, and corresponds to the pattern SP2, described above. The visual display pattern DP2 can be produced by delaying the les produced as the visual display pattern DPI by a cycle of the main clock 4 • fsc. Each le consists of a portion that represents the luminance component of that le, and a portion that represents the chrominance component of that le. In the preferred embodiment, these le portions are converted independently to the analog form, and the respective analog luminance and chrominance signals are generated, which correspond to the analog luminance and chrominance signals generated by the main video processor 104 As can be seen, the "X" s, which represent the first visual display of the previously stored PIP image les, are configured in a quincunx visual display pattern, the as the ling pattern illustrated in the upper portion of the Figure 3. In this way, the perceived horizontal resolution of the PIP image is increased, without increasing the required memory size of the field memory 120 (of Figure 2). However, a problem can be presented using quincunx ling for a PIP image signal. This problem can be better understood by referring to Figures 4 and 5. Figure 4 is a diagram of the waveform of the main video and PIP signals, and of the PIP memory access addresses. In Figure 4, the signal from the main video signal source 102 (of Figure 2) is illustrated in the upper waveform, consisting of successive frames. As in conventional interlaced video signals, in each frame there are two fields whose lines are interlaced in a known manner, and are usually designated as even and nons fields. Each field of the main video signal is represented by a rectangle. This is represented in Figure 4 by the numbering of the rectangles representing the fields of the main video signals 1 and 2. Two complete fields of the main video signal, 1 and 2, respectively, are illustrated in Figure 4. The left edge of each rectangle represents the time location of the vertical synchronization pulse associated with that field. There is no intended correspondence between the even and nons fields of a video frame, and the field designations 1 and 2 of Figure 4. The signal from the PIP video signal source 110 is illustrated in the second waveform. This video signal also includes successive frames, each frame containing two interlaced line fields, each represented by rectangles numbered 1 and 2. The left edge of each rectangle represents the timing location of the vertical synchronization pulse associated with that field. The PIP video signal is not temporarily aligned with the main video signal, as indicated by the different time locations of the. vertical synchronization pulses between the main video and PIP signals. Referring to Figure 2, as samples of the PIP video signal are generated, which contain a luminance portion and a chrominance portion in the preferred embodiment, by means of the PIP video processor 113, they are first filtered vertically, and then the vertically filtered samples are sub-sampled horizontally, in a manner that will be described in more detail below, at the times controlled by the sub-sampler 116, and these sub-sampled samples are stored in the '120 memory, at locations controlled by the address generator. 118. In response to the PIP vertical sync pulse, the write address generator resets the write address to the beginning of the field memory 120 (or to the beginning of a buffer area within the field memory 120) , which will contain the subsampled PIP inserted samples. This buffer zone is normally filled from a low address to a high address, so that this initial address is the minimum address. The write address produced by the write address generator 118 is represented in Figure 4 in the third waveform. At the beginning of field 2 in the PIP video signal (second waveform), the write address generator 118 is conditioned to produce a PIP write address which is the minimum address. As subsampled samples are produced by the sub-sampler 116 (of Figure 2), they are stored in the field memory 120 in increasing directions supplied by the write address generator 118. This is indicated in Figure 4 by a signal of Gradually increasing writing direction. At the end of field 2, the subsampled samples have been written throughout the write buffer area, and the address signal has reached its maximum value. The vertical synchronization pulse of the next field (field 1) then resets the write address generator 118 to the beginning of the buffer zone (ie the minimum address) again, and the process is repeated. While the subsampled PIP samples in the memory 120 are being written under the control of the sub-sampler 116 and the write address generator 118, as described above, the scanning location of the main video signal is being monitored by the signal generator. visual display 124. During the first portion of the main image, 6 (of Figure 1), no portion of the PIP image is being displayed. During the last portion of the main image 8 (for example, in the illustrated embodiment, the lower third of the combined image), previously subsampled samples stored in the memory 120 are retrieved by the visual display generator 124 from the controlled directions by the read address generator 122. These samples are processed by the visual display generator 124 in a manner that will be described in greater detail below, to produce the same pattern illustrated in the lower part of Figure 3. In the embodiment preferred, these samples are further processed to form respective analog signals of luminance and chrominance. These signals are then replaced by the corresponding main video luminance and chrominance signals in the multiplexer 108, during the time when the PIP image is being displayed. In a manner similar to the write address generator 118, the vertical synchronization pulse of the main video signal conditions the read address generator 122 to produce an address pointing to the beginning of the field memory 120 (or to the beginning of the buffer area in the field memory 120), which contains the subsampled samples PIP. During the lower portion 8 of the combined image, where the PIP image 4 is inserted into the combined image, the read address generator 122 controls the field memory 120 to retrieve the PIP samples from the field memory 120 in the same order in which they were written into the field memory 120 by the sub-sampler 116. Accordingly, the samples are recovered starting at the minimum address, and progressing to the maximum address, as the PIP image samples are inserted into the combined image. The read addresses generated by the read address generator 122 are represented by the fourth waveform. In the vertical synchronization pulse of the main video image, the read address generator 122 is conditioned to produce the beginning address of the field memory (or of the buffer area within the field memory). The address does not change during the first portion, 6, of the combined video image. As PIP samples are extracted from the field memory 120, the read direction is increased to the maximum direction for the end of the main video field 2. The beginning of the following main video field 1, the address generator is reset of reading 122, and the process is repeated. Figure 5 illustrates a problem that can occur with a quincunx sampling implementation in a PIP system. In Figure 5 a portion of the content of the field memory 120 is shown at a time TS1, which is presented inside the field 1 of the PIP image, as illustrated in Figure 4. Referring to Figure 5, it is illustrated a portion of the previous field of the PIP image, field 2, in the upper left portion of Figure 5, with its sampling pattern SP2 illustrated (using the same indications as in Figure 3). The dotted lines represent the lines from field 1. Field 2 is scanned from top to bottom, in a normal way, as indicated by the arrow to the left of field 2. A portion of the next succeeding field, field 1, is illustrated directly below field 2, with its SPI sampling pattern. The dotted lines represent the lines from field 2. Field 1 is also scanned from top to bottom as indicated by the arrow to the left of field 1. To the right of the images in fields 1 and 2, is the state of the portion of the memory 120 corresponding to the illustrated portions of field 1 and field 2, at time TS1. The memory 120, as illustrated in Figure 5, is written from the top down, as indicated by the arrow to the right of the memory 120. It will be understood by one skilled in the art that only sub-sampled samples are stored in the memory, "X", and not the samples that intervene "+". The patterns illustrated in the memory block 120 of Figure 5 are merely to indicate the sampling pattern in which the subsampled samples stored in the illustrated portion of the field memory 120 were taken. At the end of the PIP image field 2, the memory 120 is completely filled with subsampled samples, "X", taken from field 2, using the sampling pattern SP2. At the beginning 1, the samples from field 2 are overwritten in memory 120, with the samples subsampled from field 1, using the SPI sampling pattern, starting at the top of the memory down, as illustrated in Figure 5 In time TS1, the lower portion of the memory 120 contains samples from the field 2, as indicated by the arrow from field 2 to the lower portion of the memory 120; while the upper portion contains the samples from field 1, as indicated by the arrow from frame 1 to the upper portion of memory 120. Referring to Figure 4, a portion of the writing direction waveform PIP for field 1 of the PIP video signal, the phantom is superimposed on the PIP reading address waveform for field 2 of the main video signal. At time TSl, the PIP reading address is the same as the PIP write address. Referring to Figure 5, immediately before time TSl, line 202 is sub-sampled from field 1 of the PIP image, from the video signal PIP, and written to memory 120, at the address provided by the write address generator 118 (of Figure 2). In addition, line 202, just written in memory 120, is read from this same location in memory 120, and is displayed in the appropriate location of inserted PIP image 4 (of Figure 1). Immediately after the time TSl, the samples forming the next line 204 in the PIP image 4 (of Figure 1) are read from the memory 120, in the direction provided by the read address generator 122. However , this line has not yet been received and sub-sampled from the PIP video signal in field 1. Instead, line 204 of the displayed PIP image 4 is generated from the samples that were sub-sampled from the previous field 2.

Line 202 (and previous lines) of the displayed PIP image 4, was sampled from field 1 of the PIP image, while line 204 (and the remaining lines) was sampled from the previous field 2, which in turn, it is presented at 1/60 of a second before field 1 (in the NTSC standard of the United States). This juxtaposition in the PIP image produces what is called a temporal junction, TS, and is a known phenomenon in PIP systems that use field memories. In addition to the temporary join, in the system illustrated in Figure 5, the samples from the lower portion of the field memory 120 (e.g., from the current field 1) were taken using the SPI sampling pattern, whereas the samples of the upper portion of the field memory 120 (e.g., from the previous field 2) were taken using the SP2 sampling pattern. The difference in the horizontal locations of the samples taken between the sampling patterns, SPI and SP2, of field 1 and field 2, respectively (emphasized by the sampling patterns illustrated in the memory block 120 of Figure 5), it makes a discontinuity visible in the PIP image exhibited 4 at the junction location, termed a spatial junction in the remainder of this application. The change in the sampling patterns in the temporal union, therefore, causes a perceptible degradation of the PIP image in the temporal union. Figure 6 corresponds to Figure 5, and illustrates a solution to the problem of spatial junction in the temporal junction TSl, and its perceptible degradation of the PIP image. The beginning of field 2 is sampled using the sample pattern SP2 (as illustrated in Figure 3), which continues up to time TS2, as illustrated in the lower part of Figure 4. At time TS2, it is changed the subsampling pattern for field 2 from the sample pattern SP2 to the SPI sample pattern, and the remainder of field 2 is sampled using the SPI sample pattern. At the beginning of field 1, the sampling pattern remains SPI until time TSl. At time TSl, the sample pattern is changed to sample pattern SP2 again. This is repeated for all successive fields. The result of controlling the sampling patterns in this way is shown in the state of the memory 120 at time TSl of Figure 6. At time TSl, the lower portion of the memory 120 still contains the portion of the subsampled samples from the lower portion of field 2 (for example, below the line indicating time TS2 in field 2). These samples have been sampled using the SPI sample pattern, as described above. The upper portion of the memory 120 contains the subsampled samples from the upper portion of field 1 (e.g., above the line indicating time TSl in field 1). These samples have also been sampled using the SPI sample pattern. Accordingly, when these samples are retrieved from the memory 120 to generate the PIP image 4, the sample pattern will be consistent from top to bottom of the PIP image. There will be no perceptible spatial union at the location of the temporal junction in the main video field 1. In a similar manner, although not illustrated, all samples for the next field of the PIP image shown 4 (of Figure 1) they will have been sampled using the SP2 sample pattern, again, without producing a perceptible spatial junction at the junction location for that field. Figure 7 is a diagram, partly in the form of blocks and partly in logical form, of a sub-sampler 116, for generating the subsampled PIP samples for storage in the field memory 120 (of Figure 2). In Figure 7, the read address signal from the read address generator 122 is coupled to a first input terminal of a comparator 405, and the write address signal from the write address generator 118 is coupled with a second input terminal of the comparator 405. An output terminal of the comparator 405 is coupled with an established input terminal S of an SR 410 flip flop. A non-reversing output terminal Q of the SR 410 flip flop, is coupled with an input terminal of an inverter 420. An output terminal of the inverter 420 is coupled with a first input terminal of an OR gate (or) exclusive 430. An output terminal of the OR gate (or) exclusive 430 is coupled to a first input terminal of an AND gate (y) 435. An AND gate output terminal (y) 435 is coupled to a control input terminal of a multiplexer 450. The pulse signal of PIP vertical synchronization from the PIP time signal generator 114 is coupled to a reset input terminal R of the flip flop SR 410. A signal indicating the current PIP video signal field type (described below) is coupled with a second input terminal of gate OR (ó) exclusive 430. A signal, FREEZE *, a low active signal that indicates that a frozen frame function is going to be performed, is coupled with a second input terminal of the AND gate (y) 435. U a PIP horizontal synchronization reset signal from the PIP time signal generator 114, is coupled with a first data input terminal of the multiplexer 450, and with an input terminal of a delay circuit of three timing cycle signals PIP 4 • fsc 440. In the preferred embodiment, the horizontal synchronization reset signal PIP is a pulse having an amplitude of a single PIP cycle 4 • fsc which is presented at half of the signal of the horizontal synchronization component PIP. In an alternative way, this impulse signal may be presented at the beginning or at the end of the horizontal synchronization signal PIP, or anywhere within the horizontal synchronization signal. An output terminal of the delay circuit 440 is coupled to a second data input terminal of the multiplexer 450. An output terminal of the multiplexer 450 is coupled to a reset input terminal of a division circuit between 6, 460. timing signal output terminal of the division circuit between 6, 460, produces a PIP subsample timing signal, and is coupled with a corresponding input terminal of a subsampler 470. PIP timing signal • fsc from the generator of PIP timing signal 114, is coupled with a timing signal input terminal of the division circuit between 6, 460. The PIP video sample stream from the PIP video processor 113 is coupled to an input terminal of PIP. subsampler data 470. An output terminal of subsampler 470 produces sub-sampled data, and is coupled with field memory 120. Referring to Figure 3, you can see that the sample pattern SP2 is identical to the sample pattern SPI, but delayed by three cycles of timing signal PIP 4-fsc. In operation, the S-R 410 flip flop is reset at the beginning of each PIP field by the vertical synchronization pulse PIP. Therefore, at the beginning of each field, the signal at the output terminal Q of the flip flop S-R 410 is a logic '0' signal. The comparator 405 monitors the PIP read address and the PIP write address. When they are equal (for example, in the TS time), the comparator generates a logic '1' signal, and generates a logical '0' signal in another way. This logic '0' signal from the comparator 405 at time TS establishes the flip flop SR 410, which generates a logical '1' signal at the output terminal Q. This signal is inverted by the inverter 420, to produce a signal that is a logical '1' inside a field before time TS, and a logical '0' after time TS. The PIP field type signal is a two-state signal, which indicates the type of PIP field that is currently being received. Referring to Figure 4, a PIP field is either a type of field 1 or a type of field 2. As described above, there is no intended correspondence between the even and nones fields and field types 1 and 2. In the illustrated mode, a logical '0' signal indicates the type of field 1, and a logical '1' signal indicates the type of field 2. The exclusive OR gate (or) 430 operates to generate a signal representing the appropriate sampling pattern (for example, SPI or SP2), which will be used to sub-sample the PIP video signal. In the illustrated embodiment, when the output of the exclusive OR (or) gate 430 is a logical '1' signal, the SPI sampling pattern is used, and when it is a logical '0' signal, the SP2 sampling.

Referring again to the description of Figures 5 and 6 above, for field type 1, the sample pattern SPI is used before time TSl, and sample pattern SP2 is used after time TSl. For field type 2, sample pattern SP2 is used before time TS2, and sample pattern ST1 is used before time TS2. When the PIP field type signal is a logical '0' signal, indicating field 1, and the BEFORE TS signal is a logical '1', for example, before TSl, then the output of the OR gate (ó) Exclusive 430 is a logical '1' signal, indicating a SPI sample pattern. When the BEFORE TS signal changes to a logical '0' signal at time TSl, the output of the exclusive OR (or) gate 430 changes to a logic '0' signal, indicating the sample pattern SP2. When the PIP field type signal is a logical '1' signal, indicating field 2, and the BEFORE TS signal is a logical '1', for example, before TS2, then the output of the OR gate (ó) exclusive 430 is a logical '0' signal, which indicates the sample pattern SP2. When the BEFORE TS signal changes to a logical '0' signal at time TS2, the output of the exclusive OR gate (or) 430 changes to a logic '1' signal, indicating the SPI sample pattern. The sample selection signal from the exclusive OR (or) gate 430, SPl / * SP2, is passed through the AND gate (y) 435 via the * FREEZE signal. The * FREEZE signal, as described above, is used to indicate that a frozen PIP frame is to be made. In a frozen frame operation, PIP data writing is suspended in the field memory 120 (of FIG. 2), while the read operation continues unchanged. Because no new samples are being written to the field memory 120 in this condition, the same samples are read repeatedly from the field memory, and used to generate the inserted PIP image. This has the effect of producing a fixed or frozen inserted PIP image 4 in the visual display device. However, if the write operations are suspended at the end of a PIP field being sampled in quincunx, as described above, then the portion of the field memory 120 written before the TS time, will contain samples that were sampled with a sample pattern, while the portion of the field memory 120 written after the TS time will contain samples that were sampled with the other sample pattern. During the times when the full motion PIP image is being displayed, the control of the sampling patterns as described avoids a spatial junction in the location of the temporal junction, as described above. However, during the times when the PIP image is frozen, this same global sampling pattern will introduce a spatial junction in the PIP image at the junction location. In order to prevent the visual display of a spatial union at the location of the temporal junction in a frozen PIP image, the quincunx sampling is suspended for at least two fields before the writing of the subsampled video PIP samples is suspended in field memory 120. The inserted PIP image is sub-sampled in a rectangular pattern instead. Although this decreases the perceived horizontal resolution, it eliminates the spatial junction in the location of the temporal junction, which would result from the freezing of a signal sampled in quincunx. When the * C0NGELAR signal is a logical '1' signal, indicating that there is no imminent freezing, the SP1 / * SP2 signal is passed through the AND gate (y) 435, to the control input terminal of the multiplexer 450. When the signal of * C0NGELAR is a logical '0' signal, indicating that a freeze is imminent, then the signal SPl / * SP2 is blocked, and the output of the AND gate (y) 435 is a signal of ' 0 logical, indicating that the sample pattern SP2 will be used across all subsequent fields. This suspends the quincunx sampling pattern resulting from the simultaneous use of both SPI and SP2 sample patterns. Instead, the auxiliary image is sub-sampled in a rectangular pattern in the set of horizontal locations defined by the sample pattern SP2. This continues through two fields, under the control of other known circuits (not shown). Then, these other circuits suspend the write operations in the field memory 120. When the freeze is canceled, the * FREEZE signal is conditioned, to become a logical '1' signal, and the quincunx sampling. When the signal from the AND gate (y) 435 is a logical '1' signal, indicating that the SPI sample pattern is to be used, the multiplexer 450 is conditioned to couple the PIP horizontal synchronization reset signal directly from the PIP timing signal generator 114 to the reset input terminal of the division circuit between 6, 460. When the signal from the AND gate (y) 435 is a logical '0' signal, indicating that it is going to using the sample pattern SP2, the multiplexer 450 is conditioned to couple the delayed PIP horizontal synchronization reset pulse signal, from the three-timing delay signal circuit PIP 4 • fsc 440 to the reset input terminal of the division circuit between 6, 460. The division counter between 6 produces a sub-sampling pulse every sixth cycle of timing signal PIP 4-fsc, starting from the at which time a reset pulse is received from the multiplexer 450. When the non-delayed PIP horizontal synchronization reset pulse is received at the reset input terminal of the division circuit between 6, 460, from the multiplexer 450, the samples in the times that result in the SPI sample pattern (from Figure 3). When the PIP horizontal synchronization reset pulse delayed by three clock cycles PIP 4 • fsc is received at the input terminal of the division circuit between 6, 460, from the multiplexer 450, samples are taken at the times that result the sample pattern SP2. The sub-sampler 470 sub-samples the PIP video sample stream from the PIP video processor 113 in response to the sample signal from the division circuit between 6, 460. These sub-sampled samples are supplied to the field memory 120 (of the Figure 2) . Figure 8 is a diagram, partly in the form of blocks and partly in logical form, of a PIP inserted visual display display generator 124, for generating PIP data to be inserted into a main image. In Figure 8, the subsampled PIP samples from the field memory 120 (of Figure 2) are coupled with an input terminal of a sample recovery circuit 479. An output terminal of the sample recovery circuit 479 is coupled with an input terminal of a main timing signal cycle delay circuit • fsc 480, and with a first data input terminal of the multiplexer 490. An output terminal of the delay circuit 480 is coupled with a second terminal of data input of the multiplexer 490. An output terminal of the multiplexer 490 is coupled to the multiplexer 108 (of Figure 2). A main field type signal is coupled to a first input terminal of an AND gate (y) 485, and the * FREEZE signal (of FIG. 7) is coupled to a second input terminal of the AND gate (and 485. An output terminal of the AND gate (y) 485 is coupled to a control input terminal of the multiplexer 490. In the operation, the samples are retrieved from the field memory 120 from the locations specified by the signal of reading address, from the read address generator 122, by the sample recovery circuit 479. As described above, in a preferred embodiment, these samples each have a portion representing the luminance component of that sample, and a second portion that represents the chrominance component of that sample. The sample recovery circuit 479 retrieves a sample in a PIP timing cycle 4-fsc, and provides that sample to its output terminal. The sample recovery circuit 479 then stops that sample at its output terminal, to be repeated in the next PIP timing cycle signal 4-fsc. The next sample is then retrieved from field memory 120. This is repeated for all samples of each line in field memory 120. Referring to Figure 3, in the operation, the main field type signal provides a indication of the visual display pattern (DPI or DP2) corresponding to the sample pattern (SPI or SP2, respectively) used to sub-sample the PIP video data that is currently being retrieved from the field memory 120, in a manner similar to the PIP field type signal described above with reference to Figure 7. That is, when the SPI sample pattern has been used to sample the data that is currently being retrieved from the field memory 120, the visual display pattern is used DPI to display that data, and when the sample pattern SP2 has been used to sample the data, then the DP2 visual display pattern is used to display it. The * FREEZE signal, described above with reference to Figure 7, is a low active signal, which is asserted when a freeze function is imminent. In response to this signal, quincunx sampling is disabled. This signal is used to give gate to the main field type signal to the control input terminal of multiplexer 490. In the illustrated mode, when the main field type signal is a logical '1', then the visual display pattern DPI to display the subsampled PIP samples, and when it is a logical '0' signal, then the visual display pattern DP2 is used to display the subsampled PIP samples. When enabled by the * FREEZE signal, the main field type signal controls multiplexer 490. When the main field type signal is a logical '1' signal, indicating the visual display pattern DPI, then it is conditioned the multiplexer 490 for coupling the sampled data PIP directly from the sample recovery circuit 479 to the multiplexer 108. This provides the sub-sampled PIP samples not delayed, and produces the visual display pattern DPI, illustrated in Figure 3. When the signal of main field type is a logical '0' signal, indicating the visual display pattern DP2, then multiplexer 490 is conditioned to couple the delayed PIP sampled data from the delay circuit of a timing signal cycle • fsc 480 to multiplexer 108. The delay introduced by delay circuit 480 produces the visual display pattern DP2, illustrated in Figure 3. When a * C0NGELAR signal indicates that a frozen frame function is being performed, then the output of gate AND (y) 485 is a logical '0', indicating the visual display pattern DP2, which corresponds to the selected sampling pattern SP2 by the * FREEZE signal of Figure 7. In the PIP sampling system described above, and illustrated in the drawing, a PIP image with better horizontal resolution is provided without requiring additional samples, or a larger field memory. In addition, this system eliminates the perceptible spatial union in the location of the temporal union, which can occur in this system. Finally, this system provides a method for providing a frozen frame function without introducing a spatial union at the location of the junction in the frozen PIP image.

Claims (17)

1. An apparatus for displaying a combined image of an auxiliary image and a main image, which comprises: a source of a main image signal; a source of samples representing an auxiliary image signal; a quincunx sub-sampler, coupled with the auxiliary image sample source, for compressing the auxiliary signal by vertical filtering, and horizontally sub-sampling this vertically filtered signal to produce a quincunx pattern; and a signal combiner, coupled with the signal source of the main image and the quincunx subsampler, to combine the main image signal and the compressed and quincunx sampled signal, to generate a signal representing a combined image of the main images and assistant. The apparatus of claim 1, wherein the quincunx sub-sampler selectively subsamples the samples of the auxiliary image in one of a first sample pattern that samples in a first set of horizontal locations, and a second sample pattern that samples in a second set of horizontal locations, substantially midway between the first set of horizontal locations. The apparatus of claim 1, wherein the auxiliary image sample source comprises: a source of an auxiliary image signal, including a video component and a synchronization component; an analog-to-digital auxiliary converter, which responds to the video component of the auxiliary image signal, to generate samples representing the auxiliary video component; and an auxiliary timing signal generator, which responds to the synchronization component of the auxiliary image signal, to generate the timing signal of the auxiliary sample. 4. The apparatus of claim 3, wherein the quincunx sub-sampler further responds to a timing signal from the auxiliary timing signal generator. The apparatus of claim 4, wherein: the auxiliary timing signal generator further generates an auxiliary horizontal synchronization reset signal, and an auxiliary field type signal having a first state during the auxiliary video nons fields , and a second state during the even fields of auxiliary video; and the quincunx sub-sampler comprises: a sub-sampler, coupled with the auxiliary sample source, and responding to a sub-sample timing signal, to sub-sample the representative samples of the auxiliary video component at the times determined by the sub-sample timing signal; a timing signal divider, which responds to the auxiliary sample timing signal, and a reset signal, to produce the subsample timing signal; and a reset signal generator, which responds to the auxiliary horizontal synchronization reset signal and the auxiliary field type signal, to generate a reset signal that produces a first sampling pattern in the even auxiliary fields, and a second sampling pattern in the auxiliary fields nones. 6. The apparatus of claim 5, wherein: the timing signal divider produces a sub-sample timing signal for each previously determined number of auxiliary sample timing signals, starting at the time the signal is received from restoration; and the reset signal generator responds to the auxiliary field type signal, which has the first state to produce a simultaneous reset signal with the auxiliary horizontal synchronization reset signal, and which responds to the auxiliary field type signal having the second state to produce a reset signal which is the auxiliary horizontal synchronization reset signal delayed by half of the previously determined number of auxiliary sample timing signals. The apparatus of claim 6, wherein the reset signal generator comprises: a delay circuit, responsive to the auxiliary horizontal synchronization reset signal, to delay the auxiliary horizontal synchronization reset signal in half of the previously determined number of auxiliary sample timing signals; a multiplexer having a first data input terminal that responds to the auxiliary horizontal synchronization reset signal, a second data input terminal coupled to the delay circuit, a control input terminal that responds to the signal type auxiliary field, and an output terminal that produces the reset signal. The apparatus of claim 5, wherein: subsamples are taken in the first sampling pattern at respective times of each horizontal line, corresponding to the respective horizontal positions; and subsamples are taken in the second sampling pattern at respective times in the horizontal lines corresponding to the horizontal positions midway between the respective horizontal positions of the first sampling pattern. The apparatus of claim 1, which further comprises a main timing signal generator coupled with the main image signal source; and wherein the sample combiner comprises: a visual image display generator inserted, coupled with the quincunx sub-sampler, and responding to a timing signal from the main clock signal generator, to generate a signal representing an auxiliary image inserted; and a multiplexer, having a first data input terminal coupled with the visual display generator of the inserted image, a second data input terminal coupled with the source of the main image signal, and an output terminal producing a signal that represents the combined image. The apparatus of claim 9, wherein: the main timing signal generator further produces a selection signal having a first state when the signal from the inserted visual display generator forms the combined image, and a second state when the main image signal forms the combined image; and the multiplexer further comprises a control input terminal that responds to the selection signal, and couples the inserted image signal to its output terminal when the selection signal has the first state, and the main image signal to its terminal output when the selection signal has the second state. The apparatus of claim 10, wherein: the main timing signal generator produces a first field type signal having a first state during a main even field, and a second state during a non main field; and the inserted visual display display generator produces an image signal inserted using a first visual display pattern, when the primary field type signal has the first state, and using the second visual display pattern when the signal type of main field has the second state. The apparatus of claim 11, wherein: the main timing signal generator generates the main sample timing signal as successive timing signal pulses; and the visual display generator of the inserted image comprises: a sample recovery circuit, coupled with the quincunx subsampler, to produce visual display samples of the inserted image comprising successive pairs of samples, with a first sample of the pair being a sub-sampled auxiliary image sample in quincunx in a main timing signal pulse, and being a second sample of the pair, the first sample of the repeated pair in the next main timing signal pulse; a circuit for producing the successive pairs of samples in synchronization with the main sample timing signal, when the main field type signal has the first state, and in synchronization with the main sample clock signal delayed by one clock cycle of the main sample, when the main field type signal has the second state. The apparatus of claim 12, wherein the visual display generator of the inserted image comprises: a cycle delay circuit of the main sample timing signal, coupled with the sample recovery circuit; a multiplexer, having a first data input terminal coupled with the sample recovery circuit, a second data input terminal coupled with the delay circuit, a control input terminal that responds to the field type signal main, and an output terminal that produces the inserted image samples. The apparatus of claim 1, wherein the signal combiner comprises: a visual image display generator inserted, coupled with the quincunx subsampler; and a multiplexer, having a first data input terminal coupled to the visual display generator of the inserted image, a second data input terminal coupled to the source of the main image signal, and an output terminal that produces the representative signal of the combined image. The apparatus of claim 1, which further comprises a memory, coupled between the quincunx sub-sampler and the signal combiner, for storing a field of the subsampled samples in quincunx. The apparatus of claim 15, wherein the memory responds to a write address signal, and further comprising: a source of an auxiliary image video signal, including a synchronization component; an auxiliary timing signal generator, which responds to the auxiliary image signal synchronization component, to generate an auxiliary sample timing signal; and a write address generator, which responds to the auxiliary sample timing signal, to generate a write address signal for the memory. The apparatus of claim 15, wherein the memory responds to a read address signal, and further comprising: a source of a main image video signal, including a synchronization component; a main timing signal generator, which responds to the synchronization component of the main image signal, to generate a main sample timing signal; and a read address generator, which responds to the main sample timing signal, to generate a read address signal for the memory.