MXPA98003385A - Receiver for multiple access of cod division - Google Patents

Abstract

The present invention relates to a CDMA receiver, an A / D converter that oversamples an analog reception band base signal with a sampling clock at a frequency which is 2"times greater than a chip clock, and converts it into a digital reception band base signal A correlation circuit obtains a correlation value between the digital receive band base signal and a pilot broadcast code which is synchronous with a reception timing. phase difference obtains a phase difference between the digital receive band base signal and the receive synchronization based on the correlation value A synchronization control unit changes the reception synchronization in such a way as to eliminate the phase difference obtained by the difference detection unit of fa

Description

RECEIVER FOR MULTIPLE AFFILIATION OF CODE DIVISION FIELD OF INVENTION The present invention relates to a code division multiple access receiver (CDMA) used for a digital portable telephone or the like, or more in particular, as a synchronization tracking circuit of a CDMA receiver.

DESCRIPTION OF THE TECHNIQUE TO RFIÍACTONAPA A conventional CDMA receiver of this type is described in JP-A-9-18446, for example. In the conventional CDMA receiver, as shown in Figure 1, an analog reception signal is oversampled and converted into a digital reception signal by an A / D (analog to digital) converter 610. A correlator 620 obtains the correlation value between the digital reception signal and a broadcast code of a pilot channel (pilot spread code) according to the receiving timing of the receiver. In the process, the reception synchronization correlator 621 obtains a correlation value between the digital reception signal and the pilot broadcast code which is synchronous with a REF: 27343 current reception synchronizer. An early synchronization correlator 622 obtains a correlation value between the digital reception signal and the pilot broadcast code, which is synchronous with an early receive synchronizer having a phase in front of the present receive synchronizer. A late synchronization correlator 623 obtains a correlation value between the digital reception signal and the pilot broadcast code which is synchronous with the late reception synchronization signal having a delay phase behind the present receive synchronization. A phase difference detection unit 630 obtains the phase difference between the reception signal and the reception timing present based on the three correlation values obtained by the correlator 620. A synchronization control unit 640 synchronizes the receiver synchronization , which is used to obtain the correlation values in the correlator 620, with the reception signal by deviation from the reception synchronization so that an address is obtained to eliminate the phase difference by the difference detection unit 630 phase. In the case where the reception synchronization is intentionally deviated, the direction of the phase difference to be diverted and the angle with which it deviates are indicated to the synchronization control unit 640. With the conventional CDMA receiver mentioned above, the system configuration is restricted for selection of the sampling frequency of the 610 converter A / D However, any sampling frequency can be selected. However, an arbitrary selection of the sampling frequency makes it necessary to perform a division operation to calculate, adjust and implement a correction value of the reception synchronization when the phase difference between the reception signal and the reception synchronization is detected. to correct the reception timing. The result is that a longer time is required to calculate the correction value of the reception synchronization.

BRIEF DESCRIPTION OF THE ILVENTION An object of the present invention is to provide a CDMA receiver capable of shortening the time required to calculate a correction value of a reception timing. According to a first aspect of the present invention, a CDMA receiver is provided which comprises: an A / D converter for oversampling an analog reception baseband signal with a sampling clock having a frequency 2n times greater than that of the chip clock and to convert the base signal of analog reception band into a base signal of digital reception band; a correlation circuit to obtain a correlation value between the digital reception band base signal and a pilot broadcast code which is synchronous with the reception timing; a phase difference detecting unit for obtaining a phase difference between the digital receive band base signal and the receive synchronization based on the correlation value; and a synchronization control unit for changing the reception timing so as to eliminate the phase difference. According to a second aspect of the present invention, there is provided a CDMA receiver, wherein the synchronization control unit includes a chip phase shift unit for changing the reception timing in the chips; and a 1 / 2n chip phase shift unit to change the reception timing in l / 2p chips. According to a third aspect of the present invention, a CDMA receiver is provided, wherein the synchronization control is constituted using a synchronization circuit.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing a configuration of a conventional CDMA receiver. Figure 2 is a block diagram showing a configuration of a CDMA receiver according to a first embodiment of the present invention. Fig. 3 is a timing diagram for explaining the operation of the CDMA receiver shown in Fig. 2. Fig. 4 is a block diagram showing a configuration of a CDMA receiver, according to a second embodiment of the present invention. Figure 5 is a block diagram showing the configuration of a CDMA receiver according to a third embodiment of the present invention. Figure 6A is a diagram showing an example of an output signal from a 1/2"chip phase shift unit in the CDMA receiver of Figure 5. Figure 6B is a diagram showing an example of a output signal of a chip phase shift unit in the CDMA receiver of Figure 5.

DESCRIPTION OF (First Mode) In a CDMA receiver according to a first embodiment of the present invention, a sampling clock frequency of an A / D converter is established up to a value 2n times greater than that of the chip clock. As shown in Figure 2, the CDMA receiver according to this embodiment comprises an A / D converter 10; a correlation circuit 20, which includes a reception synchronization correlation circuit 21, an early synchronization correlation circuit 22 and a late synchronization correlation circuit 23; a phase difference detection unit 30 and a synchronization control unit 40. In the analog A / D converter, the analog reception band base signal obtained by frequency change and the orthogonal detection of a high frequency reception signal in an RF section (not shown) is oversampled with the sampling clock , the frequency of which is 23 (= 8) times greater than that of the chip clock, and becomes a base signal of digital reception band.

Each of the reception synchronization correlation circuits 21, the early synchronization correlation circuit 22 and the late synchronization correlation circuit 23 of the correlation circuit 20 is a circuit for obtaining a correlation value between the base signal of digital reception band and a pilot broadcast code (a broadcast code used for a pilot channel), and comprises a pilot broadcast code generator, a complex correlation circuit and a symbol integrator. The operation synchronizations of these three correlation circuits are controlled by the synchronization control unit 40. The receive synchronization correlation circuit 21 obtains a correlation value between the digital receive band base signal and the pilot broadcast code which is synchronous with the present receive synchronization. The early synchronization correlation circuit 22 obtains a correlation value between the digital receive band base signal and the pilot broadcast code which is synchronous with an early receive synchronization having a forward phase of the receiving synchronization present . The late synchronization correlation circuit 23 obtains a correlation value between the digital receive band base signal and the pilot broadcast code which is synchronous with the late reception synchronization having a phase delay behind the synchronization of present reception. The phase difference detecting unit 30 obtains a phase difference between the digital receive band base signal and the present receive synchronization based on three correlation values obtained from the correlation circuit 20, judges whether the reception synchronization present matches the base signal of digital reception band and in case there is no match, indicates a control amount for correcting the reception synchronization with the synchronization control unit 40. Further, in the case where the reception timing is intentionally shifted, the amount of deviation attempted from the phase difference detecting unit 30 to the synchronization control unit 40 is indicated. The synchronization control unit 40 diverts the reception timing of the receiver in accordance with the indication from the phase difference detecting unit 30. The operation of the CDMA receiver in accordance with this embodiment will be described with reference to Figure 3. The base signal of the analog reception band is oversampled with a sampling clock, the frequency of which is 23 (= 8) times greater than the of the chip clock (in FIG. 3 reference is made to a chip clock synchronization and an oversampled value), and it is converted into a digital receive band-base signal by the A / D converter 10. By establishing the assumption of that the reception timing present (the reception timing currently indicated by the synchronization control unit 40 to the correlation circuit 20) is given as a reception timing ta shown in FIG. 3, the reception synchronization correlation circuit 21 obtains the correlation value between the digital receive baseband signal and the pilot broadcast code which is synchronous with the synchronization of r eception ta. The early synchronization correlation circuit 2 obtains the correlation value between the digital reception band base signal and the pilot broadcast code which is synchronous with an early reception synchronization tx having a phase in advance of the reception synchronization ta. In addition, the late synchronization correlation circuit 23 obtains the correlation value between the digital receive band base signal and the pilot broadcast code which is synchronous with a late reception timing and having a phase delayed behind the reception timing ta. The phase difference detecting unit 30 detects the phase difference between the digital reception band base signal and the reception timing present based on the three correlation values obtained from this "nanera". synchronization diverts reception timing in such a direction as to eliminate the phase difference detected in the phase difference detecting unit 30. To bypass the reception synchronization in approximately two forward samples (in the x direction), for example, the direction and the amount of control of two samples from the phase difference detection unit 30 to the synchronization control unit 40. In the process, if the reception synchronization intentionally deviates backward (in the y direction) by three chips and one sample (one chip equal to 8 samples), the amount of deviation (three chips and one sample) is added to the amount of control (two samples) and indicated from the phase difference detection unit 30 to the synchronization control unit 40. The amount by which the reception synchronization will be diverted is given as (-2 samples) + (3 chips + 1 sample) = 2 chips + 7 samples. Therefore, the reception synchronization is deviated by two chips + 7 samples backwards. Since the sampling clock frequency of the A / D converter 10 is 23 (= 8) times greater than that of the chip clock, the amount by which the receive synchronization is bypassed is calculated by the arithmetic operation modulo-8 the which does not impose load on the processing of physical elements / programming elements. Another advantage is that, since the chip is equal to 8 (= 23) samples, similar handling is possible simply by using the carrier of the three bits and a sampling period unit, regardless of whether the reception timing is handled by the phase difference detection unit 30 in the sampling period unit alone or the sampling period plus the chip unit. The synchronization control unit 40 obtains the amount by which the reception synchronization is diverted, according to the control amount and the amount of deviation indicated from the phase difference detecting unit 30. The correlation circuit 20 diverts the reception synchronization by the amount obtained by the synchronization control unit 40 and thus obtains three correlation values, as described above. As explained above, with the CDMA receiver according to this embodiment, the phase difference detection unit 30 and the synchronization control unit 40 can be configured from an arithmetic processing means into physical elements and simple programming elements of the module-2n by setting the sampling clock frequency of the A / D converter to a value 2n times as high as the chip clock.

(Second Modality) In the CDMA receiver according to the second embodiment of the present invention, a frequency of a sampling clock of an A / D converter is set to a value 2n times as high as the chip clock, and a displacement unit is provided phase in chips and a phase shift unit in l / 2n chips (hereinafter referred to as a chip phase shift unit and a phase shift unit of l / 2n chip, respectively) in the control unit of synchronization. Specifically, the CDMA receiver according to that embodiment, as shown in Figure 4, comprises an A / D converter 310; a correlation circuit 320 including a reception synchronization correlation circuit 321, an early synchronization correlation circuit 322 and a late synchronization correlation circuit 323; a phase difference detection unit 330; and a synchronization control unit 340 including a chip phase shift unit 341, a 1/2"chip phase shift unit 343 and a coupling unit 343. The chip phase shift unit 341 is to change the reception timing in the chips, and the 1/2"phase deviation unit 342 is to change the reception timing in sampling synchronizations of the A / D converter 310. The coupling unit 343 is for combining the reception synchronization changed by the chip phase shift unit 341 with the reception timing changed by the phase deviation unit 342 of l / 2n-chips. The operations of the A / D converter 310, the correlation circuit 320 and the phase difference detector 330 of the CDMA receiver according to this embodiment are similar to those of the A / D converter 10, in correlation circuits 20 and the detector 30. of phase difference of the CDMA receiver, according to the first embodiment shown in Figure 2. Therefore, only the operation of the synchronization control unit 340 will be explained in detail below. The phase deviation quantity indication data that is supplied from the phase difference detection unit 330 to the synchronization control unit 340 indicates a quantity of phase deviation in sampling synchronization of the A / D converter 310. Assuming that the sampling clock frequency of the A / D converter 310 is 23 (= 8) times as high as that of the chip clock and the amount of phase shifted for the three chips (= 3 x 8 = 24 sampling clocks) is indicated by the phase deviation amount indication data, the phase deviation amount indication data is a total of 5 bits. In the phase deviation quantity indication data, the two higher order bits indicate the amount of phase deviation in chips, and the three lower order bits indicate a quantity of phase deviation in the sampling synchronization of the A converter / D 310. In the case where the two higher order bits of the indication of the amount of data phase shift are "00", for example, the reception synchronization is not changed by the deviation unit 341 of chip phase. In the case where the two higher order bits of the phase deviation amount indication data are "01", on the other hand, the reception timing on a chip is changed, whereas in the case where the two higher order bits of the phase deviation amount indication data are "10", the reception timing is changed by the two chips by the chip phase shift unit 341. In the case where the three lower order bits of the phase shift indication data are "000", for example, the reception synchronization is not changed by the phase shift unit 1/2"chip. In the case where the three lower order bits of the indication data of a phase shift amount are "001", the reception timing is changed by 1/23 (= 8) chips, while in the case where the three lower order bits of the phase shift quantity indication data are "011", the reception timing by 3/23 (= 3/8) chips per unit 342 phase shift of 1/2"chip Coupling unit 343 combines reception timing changed by chip phase shift unit 341 with the reception timing changed by the phase shifting unit 342 of l / 2n chip, whereby the reception timing is changed according to the phase shift amount indication data supplied from the difference detection unit 330 In the case where the phase shift amount indication data is "01011", for example, the reception timing changes on a chip in the chip phase shift unit 341, and the synchronization n reception changes by 3/8 chips in the phase shift unit 1/2"chip, which are combined with each other with the coupling unit 343, whereby a reception synchronization changed by (1) + 3/8) chips. The direction in which the phase of the reception synchronization is diverted is also indicated by the phase difference detection unit 330 to the synchronization controller unit 340. As described above, in the CDMA receiver according to this embodiment, the synchronization controller unit 340 includes the chip phase shift unit 341, the 1/2"chip phase shift unit 342 and the unit 343. Therefore, the amount of phase shift can be indicated from the phase difference detecting unit 330 to the synchronization control unit 340 in sampling synchronizations of the A / D converter 310 (ie in 1/2"chips).

(Third Mode) In a CDMA receiver according to a third embodiment of the present invention, a sampling clock frequency of an A / D converter up to 2n times as high as a chip clock is set, and a synchronization controller unit including a chip phase shift unit, a phase shift unit of 1/2"chip and a coupling unit that is constructed using synchronization circuits Specifically, the CDMA receiver according to this embodiment comprises, as shown in FIG. 5, an A / D converter 410, a correlation circuit 420 including a reception synchronization correlation circuit 421, an early synchronization correlation circuit 422 and a late synchronization correlation circuit 432, a detection unit 420 of phase difference, and a synchronization control unit 440 including a chip phase shift unit 441, a displacement unit 442 Phase I / 2n chip and a coupling unit 443. The chip phase shift unit 441 is for changing the reception timing on the chips and the outputs on the clock 444. The phase shift unit 1/2"chip is for changing the synchronization of reception in the synchronizations A / D converter sampling 410 and the outputs to a clock 445. The coupling unit 443 combines the reception timing changed by the chip phase shift unit 441, and the reception timing changed by the displacement unit 442 phase 1/2"chip based on the clocks 444 and 445. The clock 446 transmits from the coupling unit 443 functions as an activation signal for a synchronization system circuit activated in synchronization with the sampling clock of the converter A / D 410. The operations of the A / D converter 410, the correlation circuit 420 and the phase difference detection unit 430 of the CDMA receiver in accordance with that mode are similar to those of the A / D converter 10, the correlation circuit 20 and the phase difference detection unit 30 of the CDMA receiver, according to the first embodiment. Therefore, the operation of the synchronization control unit 440 will be described in detail in the following with reference to FIGS. 6A and 6B. When data of the amount of phase shift is transmitted from the phase difference detection unit 430 to the synchronization control unit 440, the phase shift unit of the 1/2"chip 442 generates the clock 445 in synchronizations that are shown in Fig. 6A In the case where the phase shift amount indication data instructs the phase to advance one clock period (one clock = 1/23 chips), for example, it is generates the clock 445 in the synchronization shown in the second line in figure 6 A. In the case where the phase shift amount indication data instructs the phase to be delayed by 6 clock periods, the clock 445 in the synchronization shown in the seventh line in figure 6A.Watch 445 in the high-level periods functions as an activation signal for a tilting circuit (synchronization system circuit) .To advance the phase a During the clock period, the activation signal is allowed in such a way that the circuit activates a longer period of time, so it advances the operation of the circuit in a clock period. By applying it to the phase shift amount indication data, the chip phase shift unit 441 generates the clock 444 in synchronizations shown in FIG. 6B. In the case where the phase shift amount indication data instructs the phase to advance a chip period, for example, the clock 444 is generated in the synchronization shown in the first line in FIG. 6B. In the case where the phase shift amount indication data instructs the phase to advance nine chip periods, the clock 444 is generated with the synchronization indicated in the ninth line of Figure 6B. The clock 444 in high-level periods functions as an activation signal for each circuit (specifically a tilting circuit (synchronization system circuit)) of the correlation circuit 420. For the phase to advance one chip period, the next one is transmitted signal activated a chip period, so the circuit operation is advanced for a period of a chip. The 443 coupling unit combines the watches 444 and 445 and transmits a clock 446 to the correlation circuit 420. The clock 446 is applied to activate a signal input terminal to the swinging circuit that operates in synchronization with the sampling clock of the A / D converter 410. In the In this case, in which the coupling unit 443 is configured as a single circuit OR (OR), the chip phase shift unit 441 and the 1/2"chip phase shift unit 442 are required to be controlled in a manner that the two watches 444 and 445 are not at the same level at the same time. In the case where the chip phase shift unit 441 and the 1/2"phase shift unit 442 have a single circuit configuration, conversely, the coupling unit 443 is required to be controlled in a such that the two clocks 444 and 445 do not assume a high level or activated at the same time.In addition, in the case in which the phase is delayed, three clocks 444 to 446 are generated in a similar manner, although the example shown in Figures 6A and 6B are configured of a module of 8 circuits with n of 3, the same applies to the case in which n assumes other values (not less than 1).

Therefore, it will be understood that the above description that, in accordance with this embodiment, a CDMA receiver is provided which has the synchronization control unit 440 configured from the synchronization circuit, and therefore can be easily implemented in physical elements. . At the same time, it has a high phase control speed and is stable against noise such as low frequency interference. It is noted that in relation to this date, the best method known by the applicant to carry out the aforementioned invention, is the conventional one for the manufacture of the objects to which it relates. Having described the invention as above, property is claimed as contained in the following:

Claims (6)

1. REIVILNDITIONS 1.
2. A code division multiple access receiver, characterized in that it comprises: an A / D (analog / digital) converter for oversampling an analog reception band base signal with a sampling clock having a frequency 2"times greater than that of a chip clock, and converting the base signal of analog reception band into a digital reception band base signal; a correlation circuit to obtain a correlation value between the base signal of digital reception band and a pilot broadcast code which is synchronous with a reception timing, a phase difference detecting unit for obtaining a phase difference between the digital receive band base signal and the receive timing based on the correlation value and a synchronization controller unit to change the reception timing so that the phase difference is eliminated. or code division multiple access, according to claim 1, characterized in that the correlation circuit includes: a reception synchronization correlation circuit to obtain a correlation value between the digital reception band base signal and a pilot broadcast code which is synchronous with a first reception synchronization; an early synchronization correlation circuit for obtaining a correlation value between the digital receive band base signal and a pilot broadcast code which is synchronous with a second reception synchronization having an advanced phase from the first reception synchronization; and a late synchronization correlation circuit to obtain a correlation value between the digital receive band base signal and a pilot broadcast code which is synchronous with a third reception synchronization having a delayed phase behind the first synchronization of reception.
3. 3. The code division multiple access receiver, according to claim i, characterized in that the synchronization control unit includes: a chip phase shift unit for changing the reception timing in chips; and a phase shift unit of 1/2"chip to change the reception timing on 1/2" chips.
4. 4. The code division multiple access receiver according to claim 3, characterized in that the correlation circuit includes: a reception synchronization correlation circuit to obtain a correlation value between the digital reception band base signal and a pilot broadcast code which is synchronous with a first reception synchronization; an early synchronization correlation circuit for obtaining a correlation value between the digital receive band base signal and a pilot broadcast code which is synchronous with a second reception synchronization having an advanced phase from the first reception synchronization; and a late synchronization correlation circuit to obtain a correlation value between the digital receive band base signal and a pilot broadcast code which is synchronous with a third reception synchronization having a delayed phase behind the first synchronization of reception.
5. 5. The code division multiple access receiver according to claim 1, characterized in that the synchronization control unit is constituted using a synchronization circuit.
6. 6. The code division multiple access receiver, according to claim 5, characterized in that the correlation circuit includes; a reception synchronization correlation circuit to obtain a correlation value between the digital reception band base signal and a pilot broadcast code which is synchronous with a first reception synchronization; an early synchronization correlation circuit for obtaining a correlation value between the digital reception band base signal and a pilot broadcast code which is synchronous with a second advanced reception synchronization in phase of the first reception synchronization; and a late synchronization correlation circuit to obtain a correlation value between the digital receive band base signal and a pilot broadcast code which is synchronous with a third reception synchronization having a phase delay behind the first reception timing.