MXPA98002208A - Interface between a channel of communications and a process - Google Patents

Abstract

An apparatus (101) and a method for communicating between a processor (103) and a communications channel (105), the processor having in the data terminal equipment (102), such as a computer, an application program to the communications for providing the transmission and reception of data on a communication channel (105), using the computer processor without the additional or redundant digital signal processor or microprocessor components. The apparatus and method provide for the transfer of data between the interface apparatus (101) and the communication channel (105) to a first determined frequency corresponding to a specific data rate. The apparatus and method provide the transfer of data between the interface apparatus (101) and the processor (103) to a second undetermined frequency and provide interim storage of data in the memory (115) between the data transmission (or reception of data). data) and data processing, such as demodulation modulation, by the computer processor (103). The apparatus and method also provide the generation of an interrupt signal to the processor to indicate the presence of data received for processing and the absence of digital data for transmission.

Description

INTERFACE BETWEEN A CHANNEL OF COMMUNICATIONS AND A PROCESSOR Cross Reference to the Related Request This application is a continuation in part of the application Series No. 08 / 521,717, filed on August 31, 1995, now abandoned, with priority claimed for all the material of the subject commonly exposed. FIELD OF THE INVENTION The invention relates in general to data communication devices, and more particularly, to a method and apparatus for communicating between a processor and a communication channel for the transmission and reception of data. BACKGROUND OF THE INVENTION Computer-controlled, programmable data terminal equipment ("DTEs"), such as personal computers, workstations, and data terminals, are increasingly common through schools, work sites and society in general. In addition, processor capacity has been increasingly significant, using increasingly faster and more powerful processors in computers, such as Motorola's PowerPC® processor and Pentium® processor.

Intel. These processors can be programmed to perform a variety of functions.

Data communications devices ("DCDs") such as analog and digital modems, ISDN terminal adapters, and computer network interconnection devices have generally been used to transfer data between various DTEs over channels of communications, such as the Public Switched Telephone Network ("PSTN") or the Integrated Services Digital Network ("ISDN"). Such DCDs have typically been separate devices, such as desktop modems, cabinet-mounted modems, PCMCIA cards, or separate circuit boards (cards) used within a computer enclosure. Furthermore, in the prior art, such DCDs also contain several processors, such as a digital signal processor ("DSP") and a microprocessor, or a unitary processor that combines the functions of both the DSP and the microprocessor. The DCDs have tended to require processing capacity separately because the DCDs are computationally and mathematically intensive, performing functions such as modulation, demodulation, coding, decoding, data compression, error correction, precoding, matching, cascade connection with the DTE, and other control functions. In addition, DCDs have performed at even faster transmission speeds, such as 28.8 kbps available under the V.34 standard of the International Telecommunication Union ("ITU"), and with data compression and error correction protocols available under the rules V.42 and V.42 bis. Such computationally intensive processing has tended to require more processor capacity and more processing time than generally available or desirable from a more general purpose multiprocessor processor used in a DTE. With the advent of increasing processor capacity in the general purpose multi-purpose processors in the DTEs, such as that available in the PowerPC® and Pentium® processors, the additional and separate processing capability available in the DCDs may no longer be necessary and it can be redundant. Provided such increased processing capacity is available in the DTEs, it can be more efficient and economical to provide a single processor, with the appropriate hardware and software, capable of carrying out both functions of the various applications programs of the computer, such such as word processing, mathematical calculations and graphs, and the functions of a DCD, such as modulation, demodulation, and data compression. Such a combined modem processor was exposed at Blacwell and Co. US Patent No. 4,965,641, "Processor Modem", issued October 23, 1990 and incorporated herein by reference. With the increasing data transmission speeds and other complex functions now required for DCDs that must be compatible with V.34 and V.42 bis, implementations of a processor modem can be complicated or difficult and may have increasing and potentially incompatible performance requirements. For example, a difficulty with the implementation of a processor modem is related to the high processing speeds available with the new general-purpose computer processors, which are capable of processing data for transmission at much faster speeds than those typically available. for the current transmission of data on a channel. For example, the computer's processor may be capable of processing data at speeds in the megahertz or gigahertz range, which are several orders of magnitude higher than typical data transmission speeds, such as 28.8 kbps for V.34 or 64 to 128 kbps for ISDN. Correspondingly, the data can arrive from a communications channel in a continuous manner, at a specific and predetermined data transmission rate, which is typically much slower than the processor speed of the computer, and the which may not effectively use the entire processing capacity of the computer's processor. For example, it would be an inefficient use of the processor's capacity of the computer to have the processor waiting for data reception at 28.8 or 14.4 kbps, when the processor could perform other application functions simultaneously. This inequality or interface problem between data transmission speeds and data processing speeds tends to create a "bottleneck" problem, either with too much data available in the processor for transmission (given the transmission speed of data), or too little data available in the channel for its subsequent processing (given the processing capacity of the computer). In addition, although the processor performs other application functions, the processor may also need to respond periodically or continuously to various requirements of data transmission protocols, such as transmission recognition signals after reception of packets or structures. of data. Accordingly, there remains a need for a more efficient apparatus and method for connecting to the general-purpose computer processor and transmitting and receiving data on a communication channel, in order to provide both efficient data transfer and efficient use of the data. processor capacity. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram that illustrates a first embodiment of an apparatus according to the present invention. Figure 2 is a block diagram showing a second embodiment of the apparatus according to the present invention. Figure 3 is a detailed block diagram illustrating a preferred embodiment of an apparatus according to the present invention. Fig. 4 is a block diagram illustrating an alternative embodiment of an interface apparatus, in accordance with the present invention, for connecting in cascade with a digital network. Figure 5 is a detailed block diagram illustrating an interface apparatus according to the invention, coupled to a computer having a modem application software program. Figure 6 is a flow diagram illustrating the method of receiving data interface according to the present invention. Figure 7 is a flow chart illustrating the transmission data interface method according to the present invention. DETAILED DESCRIPTION OF THE INVENTION As mentioned above, a significant difficulty that may be encountered, in a current implementation of a modem processor having a modem software application, refers to the different speeds or frequencies of data transmission compared to the speeds or frequencies of computer processing. These different speeds or frequencies can create a bottleneck problem that may not effectively utilize or optimize the available processing capacity of the computer, either with too much data available in the processor for transmission (given the speed of data transmission), or too little data available in the channel for its subsequent processing (given the processing capacity). In the prior art, this problem did not arise because, at least one dedicated processor (in the DCD) processed the input data, to directly create a complete file in memory or accessible to the DTE, for its subsequent processing by the second dedicated computer processor. Now, the apparatus and method of the present invention addresses this issue of incompatibility when a processor is about to perform both functions, simultaneously and in real time. Second, as discussed in more detail below, the apparatus and method of interface according to the invention directs and communicates both the deterministic aspects of data transmission, as well as the more indeterminate aspects of computer processing, in order to Simultaneously optimize the data transmission functions and other application functions of the computer processor. For example, data transmission protocols, such as V.34 and V.32 bis, typically require specific and determined transmission rates, with very deterministic sampling rates, to provide an accurate representation of the transmitted or received signal. Similarly, digital transmission protocols, such as for ISDN, also have specific and deterministic transmission rates, with timing and synchronization between and mixed with the various B and D channels (for ISDN) or DSOs (for systems). IT or El). Conversely, a computer processor may operate several programs or functions simultaneously, and each may have different processing requirements, resulting in the processor operating periodically with each program at a more indeterminate frequency, such as at a necessary frequency or specified by the user. Third, the apparatus and method of the invention provides means for a computer to direct data transmission or network protocol requirements, while performing other functions simultaneously. Fourth, the apparatus and method provides various mechanisms for the recovery of various problems of the processor or the computer. Fifth, as discussed in detail below, the apparatus and method of the invention provides the basis for directing any latency in the processor response time that may occur as a result of either the operating system or the simultaneous operation of the processor. various programs or functions. For example, the apparatus and method of the invention generates an interrupt signal to the processor to indicate either the presence of input data for processing or the absence of output data for its processing. • transmission, or both. Depending on how fast the processor may or may not respond to an interrupt request from an external device or card, such as a read / write request to read in the processor the input data to process and write to the interface apparatus the data output for transmission, the apparatus and method provides a mechanism to avoid a less than normal amount of data, from insufficient data available for transmission, and to avoid data overflows, from excess data available for its processing. Finally, also as discussed in more detail below, the apparatus and method of the present invention provides an interruption signal generation at a dynamically variable frequency, to provide a faster response that may be required during portions of data transmission protocols, such as V.32 and V.32 bis. Referring to Figure 1, Figure 1 is a total block diagram illustrating a first embodiment of an interface apparatus 101 according to the present invention. Figure 1 illustrates a DTE 102, such as a personal computer, a file server, or a workstation, that contains a processor 103, such as a PowerPC® or Pentium® processor. The processor, via lines, cable or a bus 104, is connected to the interface apparatus 101, which is further connected to a communications channel (or "channel") 105 for data transmission and reception. The lines, cable or bus 104 may be any type of installation suitable for connection to a computer, such as an ISA or PCI bus or a compatible standard PCMCIA slot. The interface apparatus 101 is discussed in detail below with reference to FIGS. 3 and 4, and performs such functions, typically found in a modem, of pulse call sound detection and tone selection, and analog conversion. digital The processor 103, which contains or operates under a communications application program, such as a modem application program, typically performs other modem functions such as orientation, equalization, mixing, encoding, decoding, echo cancellation, and precoding By using the interface apparatus 101 to connect in tandem to the communications channel 105, the processor 103 may contain or operate under other communications application programs, such as telephone answering and speech or speech recognition or processing. If coupled to a digital communications channel such as an ISDN, the processor 103 may contain or operate under other communications application programs, such as one for an ISDN terminal adapter. Figure 2 is a block diagram illustrating a second embodiment of an interface apparatus 101 according to the present invention. As shown in Figure 2, the interface apparatus 101, according to the present invention, has been incorporated into the DTE 102. For example, the interface apparatus 101 can be incorporated as a circuit board, an ISA card, a PCMCIA card, or an integrated circuit. As in Figure 1, the interface apparatus 101 is also connected or coupled to the processor 103 of the DTE 102, by the use of any appropriate installation, such as an ISA bus, PCI bus, or PCMCIA slot. Continuing the reference to Figure 2, the interface apparatus 101 is also connected to the communications channel 105 for data transmission and reception. In a manner similar to FIG. 1, the interface apparatus 101 (also discussed below in detail with reference to FIGS. 3 and 4) performs such functions, typically found in a modem, of sound detection, pulse and tone selection. , and analog-digital conversion. Similarly, processor 103, which contains or operates under a communications application program, such as a modem application program, typically performs other modem functions such as training, matching, mixing, encoding, decoding, echo cancellation and precoding. Figure 3 is a detailed block diagram illustrating a preferred embodiment of an interface apparatus 101 according to the present invention. As shown in Figure 3, an interface apparatus 101 is coupled to or connected within a DTE 102, such as a computer, through a bus 107, such as an ISA or PCI bus, and coupled to a communication channel 105, for the transmission and reception of data. Within the interface apparatus 101, a channel interface circuit 106 receives a data signal transmitted on the channel 105, such as the PSTN. The channel interface circuit 106 may be, for example, a dial-up access facility (or data) known as a "DAA", which are known in the prior art and may be made from a variety of discrete components , including analog multiplexers, resistors, capacitors, hybrid circuitry and operational amplifiers, or can be incorporated in full or in parts as an integrated circuit, and perform functions such as impedance comparison, power level adjustment, and interconversion of four to two wired connections. The use of a DAA for the channel interface circuit 106 would be appropriate for its connection to a similar line, such as a telephone line, and in that case, the data signal transmitted and received in the channel would be a similar signal. As discussed with reference to Figure 4, the channel interface circuit 106 may also be other devices, such as a digital interface circuit, suitable for connection to digital lines or channels, including S / T interface and interfaces in U used for connection to digital services such as ISDN, and which performs functions such as digital data formatting. In that case, the data signal transmitted and received to be paired from the channel would be a digital signal. For the transmission of an analog signal on the channel 105, typically connected to the channel interface circuit 106 is the encoder-decoder ("code") 108 or, equivalently, an analog-to-digital and digital-to-analog converter, referred to herein as an analog-digital converter ("A / D") (such as a Thompson SGS ST 7544 or ST 7545). The decoder (or A / D converter) 108 samples and converts a data signal (such as an analog signal) received from the channel 105 (through the channel interface circuit 106) to a digital form, and converts the digital information in a data signal (such as an analog signal) for transmission over the channel 105. Due to the exchange or equivalence capability of an A / D converter and an encoder-decoder in the invention, the reference to Either an encoder-decoder or an A / D converter must be understood to mean and include the other. In an ISDN or other digital environment, the A / D converter or codec 108, and other portions of the interface circuit 101, are typically not required, because the channel interface circuit 106 for the ISDN will directly accept the digital data.

In addition, a processor 103, such as a Motorola MC68302 multi-protocol integrated processor, typically contains serial communication controllers that will be converted into processor-formatted data, parallel to the serial data for transmission over the channel 105; in such a case, 103 bus portions 107 and interface 120 may be contained within the processor, along with the memory 115 such as the transmit sample FIFO 114 and the receive sample FIFO 116. Continuing the reference to FIG. 3, the interface apparatus 101 includes a memory 115 illustrated, in the preferred embodiment, as the hook FIFO (first inputs, first outputs) 110, the ringing sound FIFO 112, the transmission sample FIFO 114, and the sample FIFO Reception 116. Memory 115 may be incorporated in any form, such as random access memory, and shown as having separate FIFOs in Figure 3 for ease of illustration only. In addition, the memory may have formats other than the memory of first entries, first outputs illustrated, provided that the memory has the capacity to keep the data stored in an orderly or sequential manner, such as in the form of a sequence of digital data. The memory portion of the call sound FIFO 112 is also coupled to a bit quantizer 118, which is coupled to the channel interface circuit 106, while the hook FIFO is shown directly connected to the interface circuit of channel 106. The transmission sample FIFO 114 and the reception sample FIFO 116 is also coupled to the encoder-decoder (or A / D converter) 108. Each of the FIFO memory circuits is connected to an electromagnetic interface 120. , such as an ISA, PCI or PCMCIA interface, which typically includes a configuration, line or connection 122 to direct the selection and a configuration, line or connection 124 for the selection of IRQ, for its proper operation within the DTE 102, or it could alternatively include a "plug and play" type chip or other such integrated circuit. The electromechanical interface 120, such as an ISA interface, PCI interface, or PCMCIA interface, is connected to the bus 107, such as a corresponding ISA, PCI or PCMCIA bus, for connection to a processor, such as the processor 103 in the DTE 102 in FIGS. 1 and 2. Each of the FIFO memory circuits is also coupled via the status line (or bus) 126 to the functional block 138, for status monitoring. The function block 138 contains a clock generator (also referred to as a clock or as timing or synchronization circuitry) 134, an interrupt generator 128, and a status detector 136. These various clock, interrupt and status configurations also can be implemented separately or as integrated components, they can be combined within other functional blocks and included within a functional block 138 only for ease of illustration. The clock signal generator 134, the interrupt generator 128 and the status detector 136, contained within the functional block 138, are also coupled to the encoder-decoder (or A / D converter) 108 through the line 132, to the channel interface circuit 106 through the line 130 and to the electromechanical interface 120 through the line (or bus) 140. The clock generator (or clock) 134 may also be contained within the processor 103. The generator The clock signal 134 is used to generate a stable clock signal for the encoder-decoder (or A / D converter) 108, so that the decoder (or A / D converter) 108 can sample a signal of input data at regular intervals, defined, determined or otherwise predetermined, referred to as a first frequency or as a certain frequency, to obtain an accurate digital representation of the received signal consisting of a Continuously of digital values, and in addition to accurately form an output data signal (such as an analog signal) for transmission from a direct current of digital values. Continuing the reference to Figure 3, the interface apparatus 101 functions to receive an input signal (such as a data signal) through the channel interface circuit 106, which is sampled and converted to a digital form by the encoder-decoder (or A / D converter) 108 at a frequency, first or determined, and for transmitting an output signal (such as a data signal) on the channel 105 generated by the codec (or the converter). A / D) 108 from digital data, also at a frequency, first or determined. The digital samples of the received signal are transferred to and stored in the receiving sample FIFO 116. As monitored by the status detector 136 via the status line (or bus) 126, when a status sample has been transferred and stored. Sufficient or predetermined number of samples in the receiving sample FIFO 116, the interrupt generator 128 generates an interruption signal (or first interrupt signal) to the processor 103, which is transmitted to the processor 103 through the interface (or electromechanical interface) 120 and the bus 107. The first interrupt signal, or any other equivalent signal, serves to indicate to the processor 103, as programmed or incorporated into the communications application program and / or the operating system, that the processor 103 should read, in the memory of the processor, the samples contained in the receiving sample FIFO 116, within a predetermined period of time. In response to the first interrupt signal, the processor 103 is programmed to recognize the first interrupt signal and to read the samples in the processor memory from the receiving sample FIFO 116. The receiving sample FIFO 116 is it has then emptied and can be re-filled by new input data from the decoder (or A / D converter) 108. If the memory is incorporated in a form other than the FIFO, then the information stored in the memory can be written over or revised in another way through the new input data. Simultaneously during the same interruption cycle (i.e., in response to the same first interrupt signal), the processor 103 can write digital data to the transmission sample FIFO 114, transmitted through the interface 120. The data digital signals from the processor are stored in the transmit sample FIFO 114 for conversion into an output data signal (such as an analog signal) by the decoder (or A / D converter) 108, at a frequency, first or determined, for the transmission of data. As the encoder-decoder (or A / D converter) 108 generates an output data signal from the digital data stored in the transmission sample FIFO, the transmission sample FIFO is emptied, and may become to fill during the next interruption cycle by the processor 103. Alternatively, the sequence of the steps of writing and storing digital data and forming an output data signal may be in response to a second interrupt signal, which may or may not have the same shape as or be identical to the first interruption signal. For example, in various embodiments, it may be desirable to control the data transmission process separately and independently of the data reception process, in which case the second interrupt signal must be distinguishable in some way from the first interrupt signal. . In the preferred embodiment, for the variant portion of the training states or training procedures preceding the transmission and reception of data, the transmission sample FIFO 114 and the receiving sample FIFO 116 each have a capacity for store at least 18 samples, determined on the basis of a symbol transmission speed V.32 bis of 2400 Hz, a sampling clock of 7200 Hz for three samples per symbol, at a transmission speed of six symbols per interruption (or interruption cycle), resulting in eighteen samples per interruption. The interruption speed is then below 1 kHz at 400 Hz. Each of the various parameters can be modified depending on the symbol transmission rate, the sampling rate, the protocol or data transmission standard desired (such as V.32, V.32 bis, or V.34), any desired interruption speed and any desired implementation (as in ASICs). In addition, the storage capacity in memory should be increased or decreased depending on the desired level of protection against potential data overflow or data insufficiency conditions. For example, a larger interval between the interruption signals would tend to require transmission and reception memory circuits having a capacity greater than 18 samples, to avoid overflow and insufficient data conditions. In the preferred embodiment, for transmission of continuous state data, the transmit sample FIFO 114 and the receive sample FIFO 116 each have a capacity to store at least 90 samples and as many as 256 samples, with a interruption rate resulting from 80 Hz, to avoid data overflow (if the processor does not respond fast enough to the interrupt signal and the input data continues to accumulate) and to avoid data insufficiencies (if the processor does not respond fast enough to the interruption signal and the output data starts to run out). The preferred embodiment of the present invention also provides a dynamically variable frequency (or speed) for the generation of interrupt signals, and for a dynamically variable memory capacity having, for example, the transmission sample FIFO 114 and the sample FIFO of reception 116, each, a capacity that varies between a capacity to contain 18 to 256 samples. Empirical studies and simulations have indicated that in a multi-tasking environment, with other real-time applications such as video and sound reproduction making all simultaneous demands on the availability of the processor 103, the latency of interruption can be significantly increased with, for example, a Pentium class processor, and can be found in the order of 5-7 msecs. In order to operate concurrently in this environment, a software modem (or other data communication device) implemented in the processor 103 must use an interruption frequency having a period with a duration long enough to cover the delay of the latency. However, with a slow interruption frequency, there may be insufficient synchronization resolution for the appropriate responses during the initial training phases of the various modulation modes, such as V.32, V.32 bis, and V.34, which may require, for example, transfer validation responses within 2 - 5 msecs for echo calculations from the far end and orientation of the equalizer. According to the above, in the preferred embodiment, the frequency of the generation of interruption signals varies dynamically in a range between a first frequency and a second frequency. More specifically, during portions of the initial training phase, the interruption frequency (or speed) changes dynamically, of a first frequency, such as an initially lower speed for the data transmission mode (or data mode), at a second frequency, such as a temporarily faster rate for portions of the training phase, followed by the change of the interruption frequency back to the first frequency, such as the lower transmission rate for the continuous state data mode . If any retraining is indicated, in the preferred embodiment, the interruption rate will change dynamically again at the second frequency, the fastest rate, for appropriate portions of the retraining states or procedures. During these transitions between the interruption frequencies, first and second, such as from slower to faster interruption frequencies and from faster to slower, the capacity of the memory 115 (such as the size or capacity of the FIFO (of the transmission FIFO 114 and of the receiving FIFO 116)) must also vary dynamically to avoid overflow or insufficient data conditions. For example, during a mode having a slower interruption speed, such as the continuous state data transmission mode, the transmission FIFO 114 must be large enough to have sufficient data available for transmission (in order to avoid data inadequacies in the transmission), and the receiving FIFO 116 must have sufficient capacity to receive input data (in order to avoid overflows in the reception), during the period between the interruption signals, including any period of time involved in latent states of interruption. As a consequence, in the transition from a slower to a faster interruption rate, the transmit FIFO 114 may still contain data for its transmission that had not yet been transmitted at a deterministic rate, and the receiving FIFO 116 can still contain received data that had not yet been read (by processor 103) at an unspecified speed. During this time, no new data must be added for transmission to the transmission FIFO 114 or received by the receiving FIFO 116 until, respectively through the transmission at a deterministic speed and the reading by the processor 103, they have " drained "and only contain the amounts of data that can be transmitted or read respectively at a higher interruption rate. This can be accomplished by disabling the transmission portion of the software program operating on the processor 103, followed by rehabilitation when the transmission FIFO 114 only contains sufficient data for transmission at the highest interruption rate. Because the processor 103 may have the ability to read all the data contained in the receiving FIFO 116 even at a faster interruption rate, it may not be necessary to additional steps for this transition in interrupting frequencies for the reception of data, and that it may not be necessary to alter or interrupt the reception of data. Similar considerations also apply to the transition from a faster interruption frequency to a slower, continuous interruption frequency. For a slower speed, additional data is needed to fill the transmission FIFO 114, so that in the next interruption signal (slower speed), there are data in the transmission FIFO 114 available for transmission, in order to avoid a condition of insufficient data, with a potential loss of a network connection. According to the above, for this transition, the transmission FIFO 114 is (filled in) with additional data, for example, the transmission FIFO 114 is filled in advance with the following sequential samples to be transmitted. The receiving FIFO 116 will be filled or automatically filled as the input data arrives. Furthermore, in the preferred embodiment, these capacity transitions of the various FIFOs and changes in the interruption frequency may also potentially impact the empirical determinations made during the training procedures. For example, depending on how fast various signals are detected and responded by the processor 103, given the variable speed of the interruption signal, a transmission device at a remote location, such as another modem, can derive a wrong calculation for the Round trip delay used in far-end echo calculation for your equalizer. As a consequence, in the preferred embodiment, during the equalizer training, the slower continuous state interruption speed may be used instead of the faster speed for other training procedures. Similar considerations can also be applied to the near end echo calculations carried out by the processor 103 due to the variable size of the FIFO. In consecuense, the possible delay caused by a higher or lower FIFO capacity can also be measured, determined empirically or otherwise considered in the calculations made during the training of the equalizer. A dynamically varying memory capacity and dynamically varying interruption frequencies may also be applicable in ISDN or other digital network environments. For example, such variant memory capacity and varying interruption frequencies may be desirable in "transfer validation" or other initialization procedures or modes typically used in digital communications networks. The preferred embodiment of the present invention also incorporates various safeguard or recovery mechanisms to counteract situations or problems that may be encountered due to the use of a processor (such as processor 103) or a computer (such as DTE 102) for transmission or reception of data. For example, occasionally several programs within a computer interfere with each other, causing failures in the communications system or failures in the computer system such as, for example, causing the computer to not respond to external stimuli such as the keyboard or the computer. mouse, or cause the computer to have a general protection failure, "total stop" or lockout, and may require the reset or reinitialization of the operating system. (As used herein, "communication system" is the combination of processor 103 (or DTE 102) operating with or under a communications program or other communications software, in conjunction with an interface apparatus 101, and may considered a part or subset of a computer system or total processor). In the case of any failure of the communication system or other "catastrophic" occurrence, in the preferred embodiment, the status detector 136 monitors the status of the transmission sample FIFO 114 and the receiving sample FIFO 116, via the status line 126, to determine if the processor 103 has responded to the interruption signals and has been read from the receiving sample FIFO 116 and / or written to the transmission sample FIFO 114 within a predetermined time period. If the status detector 136 has determined or detected that no such activity has existed for a predetermined period of time, such as for three seconds, the status detector 136 determines that a fault has occurred in the communications system and generates a status signal on line 130 to the channel interface circuit 106, the status signal indicating that the channel interface circuit 106 should drop the line and terminate communication, for example, to cause a delay when opening, hooking , and drop the line or call. By also using the status line 126, in the preferred embodiment, the status detector 136 also determines whether a data overflow condition may exist in the receiving sample FIFO 116 and whether a condition of insufficient data in the FIFO may exist. of transmission sample 114. If there is such a condition of insufficient data, data overflow condition or other data error condition (individually and collectively referred to as "data capacity conditions"), or if these data capacity conditions they persist for a predetermined period of time or exceed a predetermined threshold, the status detector 136 will generate a status signal to indicate an error condition, in order to reset the receiving sample FIFO 116 and the transmission sample FIFO 114, and to re-tether the communications system (e.g., the communications system being the interface apparatus 101 when operating in together with a DTE 102 having a communication program, such as a modem application program). Such restoration and re-training of the communication system may be necessary when a coherent data modulation process is used due to, for example, to the loss of the appropriate sequence and synchronization under conditions of insufficient data or the potential loss of data under conditions of data overflow. In the preferred embodiment, the state detector 136 causes re-establishment and re-training and does so without loss of communication, such as without falling of the communication line. Continuing the reference to Figure 3, the calling FIFO 112 and a one-bit quantizer 118 are used in the detection of an incoming call signal for data reception. A typical call signal may have a frequency of, for example, between 20 and 60 Hz, with a particular rate (on and off sequence), and a fairly high voltage. For an input call signal, the bit quantizer 118 samples the signal at a rate of 1 kHz in the preferred mode, and generates a digit 1 (one) if the input signal has a value greater than a predetermined threshold, such as 30 V in the preferred embodiment, and generates a digit 0 (zero) if the input signal has a value less than or equal to the predetermined threshold. The bit quantizer 118 generates a stream of bits, which are transferred and stored in the call sound FIFO 112 of the memory portion 115. In the preferred embodiment, the call sound FIFO 112 has a capacity of 32. bits, to store 32 msecs of information. When the call sound FIFO 112 has reached a predetermined capacity, such as 32 bits, a status signal is generated from the call sound FIFO 112 to the interrupt generator 128 through the status line 126 Alternatively, the status detector 136 may otherwise monitor the state of the sound FIFO called 112 at predetermined intervals, such as every 10 msec, and determine whether the call sound FIFO 112 has reached a predetermined capacity. When the call sound FIFO 112 has reached a predetermined capacity, as determined by either a status signal or other detection or status monitoring, the interrupt generator 128 generates an interrupt signal which is transmitted to the processor 103 through of the interface (or electromechanical interface) 120 and the bus 107. The interruption signal may be different, equal or similar to the first interrupt signal (and / or the second interrupt signal). According to the above, depending on the desired implementation, the interrupt signal indicating the state of the call sound FIFO 112 may be referred to as a first, second or third interruption signal. The processor 103, which uses a modem or other communication application software, then processes the bitstream to detect a valid input call sound signal. For example, a valid input call sound signal must have a sequence of digital ls, followed by a sequence of digital Os, and so on, indicating the particular rate and voltage of a valid input call sound signal. For the output dialing, the interface apparatus 101 may use dual tone multifrequency ("DTMF") or pulse dialing. For DTMF, dialing can be carried out by transmitting the appropriate digital dialing information from the processor 103 to the transmit sample FIFO 114 for processing to an output signal (such as an analog output signal) by the encoder-decoder or A / D converter 108. In the preferred embodiment, the pulse dialing is carried out by the transmission of appropriate digital information from the processor 103 to the hook FIFO 110, whose information would indicate the action of picking up and contains the appropriate pulse dialing sequence. For example, a particular predefined bit stream of ls and digital Os would indicate the action of picking up by opening and closing an appropriate relay in the channel interface circuit 106. Pulse dialing is carried out by transmission of a particular sequence of predefined bits to indicate the desired dialing rate, for example, 3 hanging / hanging sequences followed by stillness, followed by 2 hanging / hanging sequences. In typical impulse dialing, the relay closes normally, resulting in a high voltage (logic one). In the preferred embodiment, the hook FIFO 110 will cause it to be opened by default, by cutting the call, if the processor has not written the data in the hook FIFO 110 for more than 32 msecs, to avoid conversation on the channel 105. Continuing the reference to Figure 3, depending on the desired implementation, the electromechanical interface 120 will typically contain a line or IRQ selection setting 124 and a line or address selection configuration 122, for proper interconnection to the host processor or computer. The address selection line or configuration 124 represents various addresses for items such as the transmission sample FIFO 114 and the reception sample FIFO 116. The IRQ selection line or configuration 122 provides a single interrupt line to the processor or computer, to avoid potential conflict with other cards or panels. Both the address selection configuration 122 and the IRQ selection configuration 124 are typically carried out through switches in the card or panel interface. Equivalently, these configurations can be implemented through the presently known integrated circuits, such as "connect and use" chip. Figure 4 is a block diagram illustrating another embodiment of an interface apparatus, in accordance with the present invention, for communicating with a digital network. Operating in virtually identical manner to the above-discussed interface apparatus 101, instead of having a channel interface circuit 106 (such as a DAA) to communicate with an analog network such as the PSTN, the interface apparatus 150 of FIG. 4 it includes a digital interface circuit 140, such as an S / T interface or a U-interface, for the transmission of data in digital form over a digital channel, such as the ISDN. In this way, the interface apparatus of the present invention can also operate as an ISDN terminal adapter or carry out other communications functions over digital channels, such as operating as an analogue or digital modem or as a telephone answering machine. According to the foregoing, as used herein, it is to be understood that a channel interface circuit 106 means and refers to, and includes within its scope, its various analogous or digital modes or counterparts, such as the apparatus of digital interface (for connection to a digital channel), such as an S / T or a U-interface, or an analog interface device, such as a DAA. As mentioned above, in a digital environment, the analog sampling and digital conversion functions of an encoder-decoder 108 as illustrated in FIG. 3 are unnecessary and, consequently, such an encoder-decoder is not illustrated in FIG. 4. Rather, the digital interface circuit 140, in conjunction with the processor 103, performs any digital structuring, signaling or other digital transmission function. Figure 5 is a detailed block diagram illustrating an interface apparatus 101, according to the invention, coupled to a computer 200 having a modem or other software application program for communications in block 210, for the purpose of to illustrate the operations of the computer or the processor corresponding to the operations of the interface apparatus 101. The modem or other block of application software to the communications 210 receives the digital data from a file in the memory in the input line of the device. data 211, in response to an interruption signal that can indicate the data necessary for its transmission and performs various modem or communications functions such as precoding, data compression, filtering, interpolation, mixing and encoding, converting the digital data into processed digital data having a suitable shape for any further processing by the A / D converter or decoder 108 and the channel interface circuit 106 or by digital interface circuit 140. This processed digital data is transmitted to an output buffer 215. In the preferred embodiment, software block 210, which operates as modem software during the variant portion of training procedures, would process six information symbols, and output buffer 215 would also store correspondingly 18 samples, and during transmission of continuous state data would process thirty information symbols, and output buffer 215 would also correspondingly store 90 samples. The software input / output driver 220 then transfers the processed digital data to the bus 107 of the interface apparatus 101 for storage in the transmission sample FIFO 114 and for processing by the encoder-decoder (or A / D converter). 108 (or the digital interface circuit 140) and its transmission on the channel 105. Similarly, the sampled digital data received from the receiving sample FIFO 116 can also be processed by the computer 200 (or processor 103). ), in response to an interruption signal indicating that the input data is available for processing. The software input / output driver 220 obtains the sampled digital data, received from the receiving sample FIFO 116, emptying the receiving sample FIFO 116, and stores the sampled, received data for processing in the memory intermediate input 225, for processing by the software block 210. In the preferred embodiment, the input buffer 225 also has the capacity to store 18 to 90 samples. The software block 210, which operates as a modem software, performs various modem functions on the received samples, such as echo cancellation, synchronization and equalization of the carrier frequency offset, other channel equalization, filtering, demodulation, decoding and deciphering, to generate digital data emitted on the data output line 212 to a file in memory. The software block 210 may also include V.42, V.42 bis or other data, video or multimedia protocol capabilities for data compression and error correction. Following the reference to FIG. 5, the procedures for detecting ringing sound and pulse dialing can be carried out correspondingly by software block 210. From the call sound FIFO 112, the input drive / software output 220 obtains the sampled data from the call sound FIFO 112, and stores the data in the call sound detection buffer 230 for processing by the software block 210. The data for dialing pulse is transferred from the software block 210 to the pulse dialing buffer 235, for transfer by the software input / output driver 220 to the hook FIFO 110.

In summary, Figures 3-5 disclose an apparatus for communicating between a processor 103 and a communications channel 105 for transmitting and receiving data, the processor 103 operable in the data terminal equipment 102 having an application program to the communications, such as a modem or terminal adapter application program. The interface apparatus 101 comprises, first, a channel interface circuit 106 coupled to the communications channel 105 so that the reception of a data signal forms an input data signal and for the transmission of a data signal to form a signal. output data signal; second, a memory 115 coupled to the channel interface circuit 106 for storing a plurality of digital data sequences; third, an encoder-decoder 108 coupled to the memory 115 and further coupled to the channel interface circuit 106 to periodically sample the input data signal at a first frequency (which is usually a certain frequency) to form a data stream sampled input and to transfer the sampled data stream of input to memory 115, and to receive a sequence of digital output data from memory 115 and to convert the digital output data stream to the data signal of departure; fourth, an interrupt signal generator 128 coupled to the memory 115 to generate a first interrupt signal and to transmit the first interrupt signal to the processor 103; and fifth, an interface circuit 120 coupled to the memory 115 and the interrupt signal generator 128, the interface circuit 120 further engageable to the processor 103 for data transfer between the processor 103 and the memory 115 and for the transmission of data. the first interrupt signal to the processor 103. The interrupt signal generator 128 may also respond in order to generate the first interrupt signal to indicate a presence of a first predetermined amount of digital data for processing, and / or to indicate an absence of a second predetermined amount of digital data for transmission. The interrupt signal generator 128 may also respond in order to generate a second interrupt signal (which may or may not be identical to the first interrupt signal) to indicate a presence of a sound signal called input, in which In this case, the interface circuit 120 is further coupled to the processor for transmitting the second interrupt signal to the processor. The various interruption signals, first and second, are typically generated at a second frequency, which is usually an undetermined or variable frequency.

The preferred embodiment may also include a state detector 136 coupled to the memory 115 and the interrupt signal generator 128, further coupled to the channel interface circuit 106, the status detector responding to the detection of a data capacity condition in memory 115, and in response to the detection of a data capacity condition in memory 115, state detector 136 generates a status signal for resetting memory 115 and for instituting retraining procedures for the communication system. The state detector 136 can also respond to the detection of a fault in the communication system, and after such detection, respond in order to generate a status signal to terminate a connection with the communications channel 105. Also in the modality preferred of the interface apparatus 101, the interrupt signal generator 128 further responds in order to generate the first interrupt signal at a first interrupting frequency during a first portion of a training mode, such as the variant portions, to generate the first interruption signal at a second interruption frequency during a second portion of the training mode, such as the remaining portions of the training states or procedures, and for generating the first interrupt signal at the second interruption frequency during a data mode, such as during the transmission of continuous state data. Further, in the preferred embodiment, the capacity of the memory 115 varies as a function of an interruption frequency. More specifically, the capacity of the memory may vary between a first capacity and a second capacity, with the first capacity occurring when the interruption signal is generated at a first interruption frequency, and the second capacity occurring when the interruption signal is generated at a second interruption frequency. Figure 6 is a flow diagram illustrating the method of receiving data interface according to the present invention. The process begins with the received data signal, start stage 300, analogous to the processing carried out by the channel interface circuit 106 in FIG. 3. The received data signal is then periodically sampled at a predetermined or predetermined first frequency. and it is converted to a digital form, as sampled digital data, by forming a sequence of received sampled data, step 305, analogous to the processing provided by the decoder (or A / D converter) 108 in Figure 3. This step 305 it can be omitted for the reception of data on a digital network, since the input data is already in a digital format and does not require additional conversion. The sequence of digital data, sampled, received, is then stored in the memory, step 310, such as the reception sample FIFO 116 of FIG. 3. The method then determines whether the memory has reached a predetermined capacity, such as or 90 samples, step 315, and if the memory capacity has been reached an interrupt signal is generated and transmitted to the processor, step 320, as in the processing provided by the state detector 136 and the interrupt generator 128 in Figure 3. If in step 315 the memory capacity has not been reached, the method is repeated and returns to step 305 to sample and convert the received signal to a digital form, and store the sampled, received digital data. in the memory, step 310. Again, in a digital network environment, the method would also be repeated but would return to step 310 to store the digital data received in the memory. During this process, the method can also quantify the received signal for the detection of an input call sound signal, step 325, and the quantized data is also stored in the memory, step 330, in a manner analogous to the processing carried performed by the one-bit quantizer 118 and the ringing sound FIFO 112. The method determines whether the incoming call sound memory, such as the call sound FIFO 112, has reached a predetermined capacity, step 335, and if so, an interrupt signal is also generated, step 320. If the incoming call sound memory has not reached a predetermined capacity, the process is repeated, returning to step 325. Proceeding from step 320 when it has been generated an interruption signal, the process transfers, at a second and normally undetermined frequency, the sampled digital data or the quantized input call sound information, to the proc It can be used for processing, such as demodulation, decoding, equalization, error correction, and other modem operations or communication functions. The process determines whether the input signal has ceased, ie the end of the input signal has been reached, such as a predetermined sequence of bits indicating the end of the transmission and that no further information will be received, step 345. If the end of the transmission has not been reached, that is, more information is being received, in step 345, the process is repeated and returned to step 305 (or step 310 for digital communication systems). If the end of the transmission has been reached, in such a way that no further information is received, in step 345, the process ends, step 350. Also as illustrated in figure 6 (and correspondingly in figure 7) , during the process of receiving data in the preferred embodiment, various state detection processes also occur, analogous to the processing carried out by the state detector 136 in FIG. 3. The process monitors a fault in the communications system or another catastrophic event, and monitor data capacity conditions (overflow and failure), step 355. If a communication system failure or other catastrophic event has occurred, step 360, the method terminates communication, step 365, and ends the process, step 350. If a data capacity condition has occurred, or any other event that may cause a loss of sequence or synchronization, step 370, the process provides the memory setup and retraining of the communications system, step 375, and return to the reception data process, step 305, (or step 310 for digital communication systems). Figure 7 is a flow chart illustrating the transmission data interphase method according to the present invention. The method begins with the reception of a sequence of digital data from the processor, normally at an indeterminate or variable speed or frequency, start step 400. The digital data stream is stored in the memory, step 410, such as in the FIFO Transmission sample 114 in Figure 3. The sequence of digital data is converted (usually at a certain frequency) into an output data signal, such as an analog signal, step 415, and transmitted over the channel, step 420 , analogous to the processing carried out by the encoder-decoder (or A / D converter) 108 and the channel interface circuit 106 of FIG. 3, or by the digital interface circuit 140 of FIG. 4. The process also determines whether the pulse dialing information has been received a. from the processor, and if so, the pulse dialing information is stored in the memory and transmitted over the channel, step 425, as in the processing carried out with the hook FIFO 110. The process continues with the step 435, in which the method determines whether more digital data is stored in memory and is available for transmission over the channel. If more digital data is stored and available for transmission in step 435, the process is repeated and returned to step 415, converting the digital data stream into an output data signal for transmission. If no more digital data is stored or available for transmission in step 435, then the process determines whether the last received digital data indicated an end of the transmission, step 440. If the last information received from the processor did not indicate an end of the transmission in step 440, the method proceeds to generate an interruption signal so that the processor receives more digital data for transmission, step 450, and the process is repeated, returning to step 410. If the last information received from the processor indicated an end of the transmission in step 440, then the process ends, step 460. As illustrated correspondingly in figure 6 for the reception of data, figure 7 is also illustrated, in the embodiment preferred, various state detection processes that occur during the transmission data process, analogous to the processing carried out by the status detector 136 in Figure 3. The process monitors a failure in the communications system or other catastrophic event, and monitors the data capacity conditions, step 465. If a failure in the communications system or other catastrophic event has occurred, step 470, the method terminates the communication, step 475, and the process ends, step 460. If Once a data capacity condition has occurred, or any other event that may cause a loss of sequence or synchronization, step 480, the process provides memory restoration and retraining of the communication system, step 485, and returns to the process of transmission data, step 410, data being received from the processor and stored in the memory. As mentioned above, the data reception and data transmission aspects of the invention can operate independently. Not illustrated in Figures 6 and 7, the data transmission and data reception functions may also operate in tandem or some other related manner, such as simultaneously in a full-duplex modem or a terminal adapter operation. To summarize such a double operation, the present invention includes a method for intercommunicating between a processor and a communication channel for the transmission and reception of data, the processor operable in the data terminal equipment having an application program for communications. The method comprises, first, (a) receiving a data signal from the communications channel to form a received data signal, step 300; (b) periodically sampling the received data signal at a first frequency to form a sequence of sampled data received, step 305; (c) storing the sequence of sampled data received in a memory, step 310; and (d) periodically transferring to a second frequency the sampled data received from the memory to the processor, step 340; and second, (e) periodically transferring to the second frequency a sequence of digital data from the processor to a memory, step 340; (f) storing the sequence of digital data in the memory, step 410; (g) periodically transferring to the first frequency the sequence of digital data to an encoder-decoder to generate an output data signal, step 415; (h) transmitting the output data signal on the communication channel, step 420; e (i) generating an interrupt signal for the processor, steps 320 and 450. Further the method may include the step of (j) receiving and detecting an incoming call sound signal from the communications channel, including (1) quantizing a voltage level of the incoming call sound signal received from the communication channel to form digital call sound information, step 325; (2) storing the digital call sound information in a memory, step 330; (3) periodically transferring to the second frequency the digital call sound information from the memory to the processor in response to the interrupt signal, steps 320 and 340. The transmission aspect of the invention may include the stage of (k) detecting whether the digital data sequence is pulse dialing information, and in the case where the digital data sequence is pulse dialing information, transmit corresponding dialing pulses on the channel, step 425. The transmission and reception method may including the step of (1) repeating steps (a) to (d), and step (i), inclusive, until the received data signal has ceased; and step (m) of repeating steps (e) through (i), inclusive, until a sequence of terminating digital data transferred from the processor has been transferred to memory. When both data reception and data transmission occur, then steps (a) to (d), inclusive, occur simultaneously with steps (e) through (i) inclusive. Finally, the transmission and reception method may include the step of (n) detecting a data capacity condition and, after such detection, generating a status signal to restore memory and to institute retraining procedures for the communications system; and the step (o) detecting a failure in the communication system and, after such detection, generating a status signal to terminate a connection with the communication channel. As indicated above, the apparatus and interface method of the present invention recognizes the data transmission rate and the processing speed comparison error, and provides a mechanism for responding to a corresponding bottleneck type problem. In response to an interruption signal indicating that data is required for transmission, the processor may transmit for short-term storage, to the transmission sample FIFO 114, at the higher processor speed or frequency, more data than the which are currently transmitted at the typically lower data rate. Correspondingly, the input data received at the lower data rate will have been stored in the receiving sample FIFO 116 and subsequently processed in its entirety by the processor at the higher or faster processor speed or frequency. Furthermore, during this time, neither the processor nor the interface device is required to delay or wait for the other to perform its functions, optimizing through this the total performance. For example, during the time required for the receiving sample FIFO 116 to be filled with the input samples, the processor can perform other application functions. Correspondingly, for data transmission, the processor can quickly fill the transmit sample FIFO 114, which then stores the information for transmission at the lower data rate. While the data is being transmitted, the processor can also carry out other application programs, and a bottleneck situation does not result from too little data received for processing or too much processed data available for transmission. The apparatus and method of the present invention also provides various mechanisms for recovering from failures in the communications system and for recovering from various conditions of data capacity or other data error conditions. From the foregoing, it will be noted that numerous variations and modifications may be made without departing from the spirit and scope of the novel concept of the invention. It should be understood that no limitation is attempted or inferred with respect to the specific methods and apparatus illustrated herein. Of course, it is intended to cover, by the appended claims, all such modifications that fall within the scope of the claims. The invention is further defined by the following claims.

Claims (10)

1. NOVELTY OF THE INVENTION Having described the present invention, it is considered as a novelty and therefore the property described in the following claims is claimed as property. An interface apparatus for communicating between a processor and a communication channel, the processor operable in the data terminal equipment having an application program for communications capable of carrying out modem training, equalization, coding and decoding, the application program responding to communications to the interrupt signals from the interface apparatus, the interface apparatus comprises: a channel interface circuit coupled to the communication channel to receive an input data signal and to transmit a output data signal; a memory; an encoder-decoder connected to the memory and further coupled to the channel interface circuit to periodically sample the input data signal at a given first frequency to form a sequence of input sampled data and to transfer the sequence of input sampled data to memory, and to receive a sequence of digital output data from the memory and to convert the sequence of digital output data into the output data signal; an interrupt signal generator that responds to the conditions of the data in the memory to generate a first interrupt signal and to transmit the first interrupt signal to the processor, the first interrupt signal indicating one of a data condition, first and second. second, the first condition being a presence in the memory of a first predetermined amount of digital data for processing by the application program to the communications and the second condition being an absence of a second predetermined amount of digital data stored in the memory for its transmission on the channel, in such a way that the program of application to the communications can respond to the first condition by means of the withdrawal of the data of the memory to carry out functions of modem in the same one and can respond to the second condition by means of the writing of data in the memory, having processed the data by means of func modem ions in the application program to communications; and an interface circuit coupled to the memory, to the interrupt signal generator and to the processor for the transfer of data between the processor and the memory and for the transmission of the first interrupt signal to the processor. The interface apparatus according to claim 1, characterized in that the interruption signal generator also responds to generate and send to the processor a second interruption signal to indicate the presence of an incoming call sound signal in the communications channel . The interface apparatus according to claim 1, characterized in that the first interrupt signal is generated by the interrupt signal generator at a second undetermined frequency that is different from the first frequency. The interface apparatus according to claim 2, characterized in that it further comprises: a one-bit quantizer coupled to the channel interface circuit for the detection of an incoming call sound signal. The interface apparatus according to claim 4, characterized in that the memory includes a call sound FIFO for receiving the sampled input data which is detected as an incoming call sound signal. The interface device according to claim 1, characterized in that the memory has a variable memory capacity, the memory capacity varying between a first capacity and a second capacity, the first capacity occurring when the interruption signal is generated to a first interruption frequency, and the second capacity occurring when the interruption signal is generated at a second interruption frequency. 7. The interface apparatus according to claim 6, characterized in that the interruption signal generator includes means for generating interruptions to one of a first and a second velocity, the first velocity being a lower velocity in relation to the second velocity, and wherein the interruption signal generator responds to a training event in such a way that interrupts are generated at the first speed during a data transmission mode of the training event and during a continuous state mode and in such a way that interruptions are generated at a second speed during a training phase and wherein the variable memory capacity changes from a first capacity to a second capacity when the generation of the interruption signal changes from a lower frequency to a higher frequency and where the transfer and storage of additional sequences of digital data in the memory are suspended until the digital data streams previously transmitted and stored in memory reach the level of the second capacity. The interface apparatus according to claim 7, characterized in that the interrupt signal generator also responds to generate the first interrupt signal at a first interrupt frequency during a portion of an initialization mode, and to generate the first interrupt signal. interruption to a second interruption frequency during a data mode. The interface apparatus according to claim 7, characterized in that the variable memory is capable of containing between 90 and 256 data samples from the processor to be transmitted as an output data signal sequence when the interrupt signal generator is found. generating interrupts at the first speed for the continuous state mode. The interface apparatus according to claim 7, characterized in that during a transition between the generation of interrupts at the first velocity and the generation of interrupts at the second velocity, the memory is not capable of receiving additional data until sufficient samples are read contained in it that have not been read for transmission to the channel, so that the remaining unread data can be read at the second speed. SUMMARY An apparatus (101) and a method for communicating between a processor (103) and a communication channel (105), the processor operable in the data terminal equipment (102), such as a computer, an application program to communications to provide transmission and reception of data over a communication channel (105), using the computer's processor without the additional or redundant digital signal processor or microprocessor components. The apparatus and method provide for the transfer of data between the interface apparatus (101) and the communication channel (105) to a first determined frequency corresponding to a specific data rate. The apparatus and method provide the transfer of data between the interface apparatus (101) and the processor (103) to an undetermined second frequency and provide the interim storage of data in the memory (115) between the data transmission (or reception of data). data) and data processing, such as modulation and demodulation, by the computer processor (103). The apparatus and method further provide for the generation of an interrupt signal to the processor to indicate the presence of data received for processing and the absence of digital data for transmission.