MXPA97004896A - Method and device for completing data lzw using an asociat memory - Google Patents

Abstract

The present invention relates to a method for data compression, to compress an input stream of data character signals to a stream of compressed code signals, the data character signals belong to an alphabet of data character signals containing (A) characters, characterized in that the method comprises: (a) the use of an associative memory having a plurality of locations for storing strings of data character signals, each location having a pre-fixed code field and a character field, each location has a division associated with it, the address provides a compressed code signal for a stored string, (b) the initialization of the memory to contain (A) strings of simple characters from that alphabet, by canceling the pre-fixed code field of (A) memory locations, and inserting alphabet data character signals into the character field of the (A) locations, respectively, (c) the use of a record that has a code field and a character field, (d) the cancellation of the code field of the record and the insertion of a character of an entry data within the character field of said register, (e) the associative comparison of the contents of the record with the contents of the locations, of the memory, to determine a correspondence with it, (f) if a correspondence is determined, it is inserts the division associated with the correspondence location within the code field of the record, and a next data character is inserted into the input stream into the character field of the record, (g) steps (a) and (f) until no correspondence is determined, which is the longest stored string in memory, corresponding to the input stream, (h) when no correspondence is determined in step (e), it is provided The contents of the register code field are displayed as a compressed code signal, thereby providing the compressed code signal of the longer correspondence stored string, (i) the contents of the code field and field are written of characters of the record within the pre-fixed code field and the character field, respectively, of a next empty location in the memory, whereby an extended string comprising the stored string of correspondence is inserted into the memory, more long, extended by the next signal of data characters in the input stream, the address of the next empty location provides the compressed code signal for the extended string, inserted into said memory, (j) the code field is canceled of the record after inserting the extended string into the memory, and (k) repeating steps (e) through (j) until no input current is available additional data character signals that will be compressed

Description

METHOD AND DEVICE FOR COMPRESSING LZW DATA USING AN ASSOCIATIVE MEMORY BACKGROUND OF THE INVENTION 1.- Field of the Invention The invention relates to compression and decompression of data. 2.- Description of the Previous Technique LZW is a ubiquitously popular process for compressing and decompressing data and is used, for example in applications such as the CCITT V.42bis standard for modem communication. LZW is described in U.S. Pat. No. 4,558,302 issued on December 10, 1985 to Terry A. Welc entitled "High Speed Data Compression and Descompression Apparatus And Method" (Apparatus and Method for Compression and Decompression of High Speed Data). Said Patent of the U.S.A. Do not. 4,558,302 is incorporated herein by reference and was granted to the assignee of the present invention. LZW data compression uses a dictionary to store strings of data characters found in the feed and looks for the feed string by comparing the feed stream to the strings stored in the dictionary, to determine the longest correspondence. The dictionary is increased by storing an extended string comprising the longest correspondence that spans the next data character fed following the longest REF: 24985 correspondence. Traditionally, the data compression dictionary is implemented by random access memory storage (RAM). Welch suggests in Patent 4,558,302 (column 52, lines 30-34) that an associative or addressable memory per content can be used instead of RAM, which would reduce the control complexity. Welch, however, does not describe in any way how this can be achieved. It is considered that to date in the prior art an associative memory modality of the LZW compression algorithm has not been provided. On the other hand, the Patent of the U.S.A. No. 4,366,551, granted on December 28, 1982 to Klaus E. Holtz, entitled "Associativß Memory Search SystemM (System of Search for Associative Memory) describes a storage and search system that uses an associative memory. 4,366,551, however does not describe or suggest an associative memory modality of the LZW algorithm, said US Patent No. 4,366,551 is cited and exceeded in a re-examination of US Patent No. 4,558,302 under the re-examination certificate. B 4,558,302 issued January 4, 1994. CQMPENPIQ pe THE INVENTION A stream of data character signals is compressed into a stream of compressed code signals by comparing the contents of the register that maintains a character pair, pre-fixed code to the contents of character pairs with pre-fixed code that stores associative memory The character position of the register sequentially maintains the data character signals as They absorb from the power supply of signals of data characters. If the comparison results in a hit (Hit), the hit address is replaced by the pre-fixed code in the record and the next signal and data character is replaced by the character in the record. The process is repeated until a fault occurs (Miss) at which time the pre-fixed code in the register is transmitted as the compressed code signal. An address counter provides the address of the next available empty location in the associative memory. The contents of the record are stored in this site and the address counter is incremented. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic block diagram of a data compressor i in accordance with the invention. Figure 2 is a schematic block diagram of a data decompressor to decompress the output of the Figure 1. .... . 4 DESCRIPTION PE THE PREFERRED MODALITIES Modalities of the present invention can operate either with dictionaries that are initialized to contain all strings of single characters or are initialized to contain only the null string. First, the simple character string mode initialized will be described. With reference to Figure 1, a data compressor 10, configured in accordance with the present invention, is illustrated. The data compressor 10 includes an addressable memory ds content 11 having N locations, each having a field 12 for storing a pre-fixed code and a field 13 for storing a character. The memory 11 further includes an address section 14 to denote the addresses of the memory locations. The compressor 10 compresses a stream of data character signals onto an alphabet having [A] characters. For example, an alphabet with a size of 256 is used in ASCII coded representations. In the initialized mode of single character string of the data compressor 10, the first [A] locations of the memory 11 are initialized to contain the [A] strings of simple characters. The pre-fixed code in field 12 of a location that stores a single string of characters is set to 0 and its field 13 stores the character in binary form. For example, in ASCII code, the character field 13 is 8 bits wide. The prefix code field 12 contains sufficient bits to accommodate the N locations of the memory 11.

The locations of the memory 11 begin with. The location [A] are initialized by resetting all character fields 13 to an arbitrary bit pattern that is not recognized as any of the characters of the alphabet. The data compressor 10 also includes a register having a field 21 for storing a code and a field 22 for storing a character. The memory 11 operates in an associative or reading mode in which the contents of the register 20 are compared with the contents of the memory 11. This operation is denoted by the reference number 23. If the contents of register 20 correspond to the contents of a location in the memory 11, a hit signal is indicated in a hit / miss output 24. The address of the location in which the hit is found is provided from the address section 14 in an output 25. The output 25 provides a power to the code field 21 of the register 20. If the contents of register 20 are not in the memory 11, a fault is indicated in the output 24. The memory 11 also operates in a write mode where the The contents of the code field 21 and the character field 22 of the register 20 are written in the pre-fixed code field 12 and the character field 13 respectively of the memory 11 in a site designated by a direct address supply. 26. The memory addresses are provided in the address feed 26 from an address counter 31.

The code, character feeds to the memory 11 in the write mode, are indicated by reference numbers 27 and 28 respectively. The write / read node of the memory 11 is selected by a feed 30. The character feed data stream to be compressed is applied to a feed 32 through a feed data register 33 to the character field 22 of the register 20. The compressed code from the data compressor 10 is provided through an output block 34 from the code field 21 of the register 20. A supply of null code 40 is used to zero the code field 21 of the register 20. The control logic 41 provides feeds to all the components of the data compressor 10, as indicated at 42. The control logic 41 receives the hit / miss signal at the memory output 24 and provides the write / read control to the memory 11 by means of the memory supply 30. In operation, in the initialized mode of single character string of the data compressor 10, the first [A] memory locations oria are initialized to store all strings of single characters possible. In those initialized locations, the pre-fixed code fields 12 are set to zero and the character fields 13 conform to the binary representation of the respective characters of the alphabet. The counter from address 31 is set to [A] +1. The feed character stream when compressed is supplied in feed 32 and buffered in the feed data register 33. A cycle of the data compressor 10 occurs as follows. The code field 21 of the register 20 is set to 0 by the null code 40. The character field 22 stores the character that resulted in a failure indication at the output 24 of the previous cycle. However, if the data compressor 10 begins its first cycle, the first character in the feed stream is placed in the character field 22 from the feed data register 33. The control logic 41 controls the memory 11 by feeding 30 to operate in the associative mode. The contents of the register 20 are compared with the contents of the memory 11 through the path 23 and if it is located, a hit at the output 24 is registered to the control logic 41. The direction in which the success occurs is loaded in the code field 21 of register 20 and the next character fed is loaded into the field of character 22. This procedure is repeated until a fault is registered at output 24 to control logic 41. When this occurs, the resident code in the field 21 of the register 20 is provided through the output block 34 as the compressed code output for the cycle.

The control logic 41 then controls the memory 11 to operate in its write mode by the control feed 30 to describe the code from the feed 27 and the character of the feed 28 to the pre-set code field 12 and the character 13 from the location directed by the address counter 31. The address counter 31 is then incremented by one and the code field 21 is zeroed by the null code 40. The compression cycle is then completed and the compressor Data 10 is ready to perform the next cycle. The control logic 41 provides control signals to all. blocks of the data compressor 10 to control the operations described above. The control logic 41 can be conveniently implemented by a conventional state machine. For the above-described operating cycle, a string of character feeds in the feed stream has been absorbed by the data compressor 10 and compared to the contents of the memory 11 until the longer correspondence with the feed is achieved. The prefix code of this longer correspondence is sent out and the memory is updated by storing an extended string in the memory 11 which comprises the longest correspondence extending by the next successive character in the feed stream. In this way, the data compressor 10 performs LZW compression without the general search load of the RAM normally associated with this type of compression. On the contrary, the addressable content compression of the content of the register 20 with the contents of memory 11 is performed. With reference to Figure 2, a data decompressor 50 for decompressing the compressed code output of the data compressor 10 of Figure 1 is illustrated. The data decompressor 50 receives the compressed code output from the output block 34 of the Figure 1 and retrieve the corresponding stream of data characters. The decompressor 50 uses a RAM 51 in a manner similar to that described in U.S. Pat. No. 4,558,302. The decompressor 50 is structured and operated in a manner similar to that of Figure 5 of U.S. Pat. No. 4,558,302. The compressed code is received in a feed 52 and maintained in a power code register 53. The registration power code 53 is applied to a RAM address register 54 to access the RAM 51 in the location represented by the compressed code in the register d) RAM address 54. Each location of the RAM 51 includes a prefix code field 55 and a character field 56.

In a manner similar to that described above with respect to Figure 1, RAM 51 is initialized to contain all strings of single characters. In this way, the first [A] locations of the RAM 51 are initialized such that the prefix code fields 55 store zero and the character fields 56 store the binary representations of the respective characters of the alphabet. The decompressor 50 also includes an address counter 60 which at the start of the decompression operation is initialized to [A] +1. The address counter output 60 provides power to the RAM address register 54 to access the RAM 51. The RAM 51 contains N locations corresponding to the N locations of the content addressable memory 11 of Figure 1. The RAM 51 is operated in a read mode when a string of characters is retrieved and in a write mode when the RAM 51 is updated. In the reading mode, the prefix code in the location accorded by the address register RAM 54 is applied in a path 61 and the character of the accessed location is applied to a last-put stack 62 by way of path 63. The prefix code in the path 61 is applied as a feed to the RAM address register 54. The stack 62 is used to maintain the characters of a retrieved string that are sequentially output to an output 64. In a RAM write mode 51, the code that is provided from a previous code register 70 by a path 61 is written in the pre-fixed field field 55 of the location accessed by the d-register address RAM 54. The stack 62 provides a character by means of a power supply. 72 that will be written in the field of character 56 of this accessed location. When the decompression cycle is complete, the code in the power code register 53 is transferred to the previous code register 70. The decompressor 50 further includes logic control d 73 to provide control feeds to all components of the decompressor 50, co or is indicated by the reference number 74. A zero detector 75 detects when the prefix code output 61 of the RAM 51 is set to zero and provides this indication to the control line 73 via a path 76. In order d provide exceptional MCaso processing "to be described, decompressor 50 includes a comparator 80 that compares the code in the feed code register 53 with the contents of counter dβ address 60 and provides an indication to control logic 73 by a path 81, when these quantities are equal.

• In operation, the decompressor 50 performs a decompression cycle for each compressed code that is received in the feed 52 to recover and provide in the output 64 the string of characters corresponding to the code. Decompression cycles usually occur as follows. The power code in the register 53 is applied to the RAM address register 54 to access the RAM 51. The control logic 73 controls the RAM to the read mode. The character stored in the acclimated location is read out at the output 63 and pushed into the stack 62. The prefix code of the accessed location is read on the output 61 and applied to the RAM address register 54 to address the next accessed location. This process continues until the zero detector 75 detects that the read prefix code is zero. When this occurs, the string of characters pushed into the stack 62 is put in inverted order at the output 64 to provide the retrieved string corresponding to the compressed code that is received in the feed 52. The control logic 73 then controls the RAM 51 to write mode and write the contents of the previous code register 70 to the RAM location accessed by the address counter 60. The character at the top of the stack 62 is written to the character field 56 of this location accessed by stack output 72. The character written in character field 56 is the first character of the string currently retrieved and is the extension character of the extended string that is stored. At the end of the decompression cycle, the address counter 60 is incremented by the unit and the code in the power code register 53 is transferred to the previous code register 70. The decompressor 50 is then ready to receive the following code. In the first cycle of the decompressor 50, the writing operation is not performed since there is no previous code at this time and in the previous code register 70. Additionally, the address counter 60 does not increase during this cycle. An "exception case" occurs when the compressor of Figure 1 outputs the code of a string that was stored in the previous compressor cycle. The compressed code that is received by the decompressor in this case will not be recognized since the decompressor has not yet stored this string. The exception case occurs when the compressed power code received in the register 53 is equal to the contents of the address counter 60. The exception case processing is then performed as follows. The code in the previous code register 70 is transferred to the RAM address register 54 via a path 90. The stack 62 is of the type described in the '425 patent, when the last character removed from the stack still resides in the upper stack register. In normal processing, this character provides the extension character and is subsequently overwritten when characters are received in the feed 63. In exception case processing, this character is pushed to the stack followed by characters retrieved from the code now resident in the record RAM address 54. This string is then removed from the stack 62 to provide the string retrieved at the output 64. The address counter 60 now accesses the RAM 51 by the RAM address register 54 and the character now in the upper part in the stack 62 is written in the character field 56 of the accessed location. The code now in the pre-code register 70 is written over the prefix code field 55. The code in the feed code register 53 is then transferred to the previous code register 70 and the counter d? Address 60 is incremented to complete the code. exception case cycle. The foregoing is appreciated, that a similar way to that described in the patent of the U.S.A. No. 4,558,302, the string is retrieved, in reverse order from the RAM 51 in response to a power code. The stack 62 is used to then reverse the order of the retrieved string that provides its characters in the correct sequence. In the embodiment of the invention described above, it is explained in terms of initializing the memory 11 of Figure 1 and the RAM 51 of Figure 2 with all strings of simple characters. It is appreciated that the invention can also be applied to a modality initialized with the null string. In this modality, all memories 11 and 51 are released and address counters 31 and 60 start in a unit account. Processing occurs in a manner similar to that described above, except that when a character is encountered for the first time it is transmitted uncompressed in such a way that the decompressor can remain in synchrony with the compressor. This can be achieved by the compressor 10 transmitting a zero code followed by the character which can then be recognized and recovered by the decompressor 50. In this mode, the zero code is detected in the power code register 53 with a zero detector. This transmission of character and zero code can be achieved with a path from the character field 22 of the register 20 to the output block 34. The output block 34 will assemble the code zero of the field 21 and the character of the field 22 of the register 20 to provide its output transmission. Additionally, the power code register 53 of Figure 2 will be modified to provide simple character transmission to the output 64 via the stack 62. The character will be stored in the RAM 51 with a zero pre-fixed code. The address counter 60 will be increased appropriately to accommodate these differences with respect to the initialized mode by simple character string described above. The modalities described above can be implemented in software, programs recorded in unalterable memory, logic, physical equipment and the like or combinations thereof. While the invention has been described in its preferred embodiments, it should be understood that the words that have been employed are words of description rather than limitation and that changes may be made within the scope of the appended claims without departing from the scope and real spirit of the invention. the invention in its broader aspects. It is noted that in relation to this date, the best method known to the applicant to carry out the aforementioned invention, is that which is clear from the present description of the invention. Having described the invention as above, property is claimed as contained in the following:

Claims (12)

1. CLAIMS l.- Method for data compression, for compressing a stream of data signals of power data in a stream of compressed code signals, characterized in that it comprises: (a) using an associative memory having a plurality of locations, each location has a pre-fixed code field and a character field, each location has an address associated with it, (b) using a record that has a code field and a character field, (c) comparing associatively the contents of the record with the contents of the locations of the memory, to determine a correspondence, (d) if a correspondence is determined, insert the address associated with the correspondence location in the registration code field and insert a following data character fed to the character field of the record, (e) repeating steps (c) and (d) until no correspondence is determined, (f) when not determined correspo ndence in step (c), providing the contents of the register code field as a compressed code signal, and (g) writing the contents of the code field and the character field of the record in the prefix code field and the character field respectively of a next empty location in memory.
2. 2. - The method according to claim 1, characterized in that it further comprises: nullifying the code field of the register and repeating steps (c) to (g).
3. 3. The method according to claim 1, further comprising: nullifying the code field of the register and inserting a feed data character in the character field of the record before step (c).
4. 4. The method according to claim 1, characterized in that the realization character signals belong to an alphabet of data character signals that contain [A] characters, the method further comprising initializing the memory to contain [A] strings of simple characters of the alphabet.
5. 5. The method according to claim 4, characterized in that the initialization stage comprises: nullifying the pre-fixed dβ code field [A] memory locations and inserting the alphabet data character signals- to the character fields of the [A] of locations, respectively.
6. 6. The method according to claim 1, characterized in that it also includes assigning sequential addresses to access empty memory sequence locations to provide the next empty location of the step (g).
7. 7. - Apparatus for data compression, for compressing a stream of data signals of power data in a signal stream of compressed codes, characterized in that it comprises: (a) an associative memory having a plurality of locations, each location has a field of pre-fixed code and a character field, each location has an associated address, (b) a record that has a dß code field and a character field, and (c) control means coupled to memory and registration to operate the memory to compare in an associative way the contents of the record with the contents of the locations of the memory to determine a correspondence; (d) the control means are operative, if a new correspondence is determined, to cause the address associated with the correspondence location is inserted into the registration code field and to cause a next feed data character to be inserted into the field of character of the record, (e) the control means are operative to repeat steps (c) and (d) until correspondence is not determined, (f) the control means are additionally operative, when no correspondence is determined in the stage (c), to provide the contents of the register code field as a compressed code signal, and to operate the memory to write the contents of the code field and the character field of the register in the prefix code field and the character field respectively of an empty location in memory.
8. 8. The apparatus according to claim 7, characterized in that it also comprises: means for nullifying the code field of the register, the control means are operative to repeat steps (c) and (f).
9. 9. The apparatus according to claim 7, characterized in that it also includes: means for nullifying the code field of the register, the control means are operative to insert a character of power data in the character field of the record and cause that (c) and (f) are made.
10. 10. The apparatus according to claim 7, characterized in that the feed data character signals belong to an alphabet of data character signals containing [A] characters, the apparatus further comprises means for initializing the memory to contain [A] strings of simple characters of the alphabet.
11. The apparatus according to claim 10, characterized in that the initialization means comprise: means for nullifying the field dβ code dβ prefix of [A] locations in the memory and means for inserting the character data signals of the alphabet to the character fields of the [A] of locations, respectively.
12. 12. - The apparatus according to claim 7, characterized in that it also includes an address counter for assigning sequential addresses to access sequential empty locations of the memory to provide the next empty location.