MXPA97004757A - Apparatus and method to demodulate a deniveles multip signal - Google Patents

Abstract

The present invention relates to a multi-level signal demodulation apparatus, comprising: means for converting an analog input signal having a multiple level into a digital signal, a means for discriminating the level of the digital signal, comparing the digital signal with multiple threshold data corresponding to the multiple levels of the analog input signal, a means for averaging first digital signals corresponding to a first level of the multiple levels of the analog input signal to produce a first digital signal averaged means for averaging second digital signals corresponding to a second level of the multiple levels of the analog input signal to produce a second averaged digital signal, a means for determining whether the level of the digital signal that was discriminated by the discriminating means , as the first level, the first digital signal averaged and the level of the digital signal that was discriminated by the discrimination means as the second level, the second averaged signal was diverted, and a means to adjust the discrimination means, so that a first deviation between the level of the digital signal was discriminated by the discriminating means as the first level and the first averaged digital signal and a second deviation between the level of the digital signal that was discriminated by the discriminating means as the second level and the second averaged digital signal, are compensated for when the means of discrimination discriminates that the level of the digital signal that was discriminated by the discrimination medium as the first level deviated from the first averaged digital signal, and so that the level of the digital signal that was discriminated by the discrimination medium as the second level, deviate from the second average signal

Description

"DEVICE AND METHOD TO DEMODULATE A SIGNAL OF MULTIPLE LEVELS" TECHNICAL FIELD The present invention relates to an apparatus and method for demodulating a multi-level signal of which the amplitude is modulated by a multiple level.

ANTECEDENTS OF THE TECHNIQUE Recently, in the field of radio communication, a multiple carrier modulation system is used to increase a rate of data transmission. For example, in Japan in a radiolocation system that is standardized as "RCR STD-43", a four-level FSK (Frequency Shift Keying) is adopted as a signal modulation system. Furthermore, in case the data is written to a recording medium, such as an optical disc and so on, the multiple carrier modulation system is used to record the data with high density. In order to demodulate a modulated signal from multiple carriers into a digital data, a multi-carrier modulated signal is usually converted into a multi-level voltage signal, ie, a PAM (Pulse Amplitude Modulation) signal using a frequency discriminator and so on. Then the voltage signal is compared to the multiple threshold voltages. For example, there are the following two well-known methods for demodulating a four-level FSK modulated signal. In accordance with a first method, a four-level analog signal of a four-level FSK signal is played using a frequency discriminator. The reproduced signal is compared to three threshold voltages that are previously set to demodulate to a four-level digital data. A second method is basically similar to the first method in which the reproduced four-level analog signal is compared to three threshold voltages to be demodulated into a four-level digital data. Where the three threshold voltages are not fixed voltages but variable voltages that are intertwined to a received signal. According to the second method, more specifically, a maximum data voltage and a minimum data voltage are detected by a detector between the four-level analog signals reproduced by the frequency discriminator, and the voltages detected in both levels are send Between two voltage output terminals of the detector, that is, one output terminal for the maximum data voltage and the other output terminal for the minimum data voltage, four resistors are connected in series. The voltages of 17 percent, 50 percent and 83 percent of a potential difference between the maximum data voltage and the minimum data voltage are taken from the connection points of four resistors. Where these three intermediate voltages are defined as the three threshold voltages. In accordance with the first method, the three threshold voltages are set respectively. In this way, when a local oscillator includes an off-center, that is, when the frequency of a received signal and a reproduced signal are not matched to that of the local oscillator, or when there are variations and so on of the characteristics of the elements of the oscillator. circuit that make up a frequency discriminator etc., there is a problem that a multilevel signal can not be demodulated correctly. That is, the four-level analog signal must be reproduced by the frequency discriminator in such a way that the four levels of the signal are placed by an equal interval and just an intermediate point between adjacent threshold levels as shown in Figure A . However, in case there is a local decentering, there is a problem that a total value of the reproduced signal is shifted to the high level side or the low level. For example, when the total value is greatly shifted to the high level side, as shown in Figure IB, all signal levels become higher than a third threshold level. The signals that must inherently be demodulated to "10", "01" and "00" are demodulated with "11", "10" and "01", so that the data can not be demodulated correctly. In addition, when there is variation, etc., of the characteristics of the circuit elements, an amplitude of the reproduced analog signal of four levels (regenerated) is totally or partially deformed. Figure 1C shows an example in one case that an amplitude of the four-level analog signal is totally deformed. In this case, the data that must be inherently modulated up to "11" and "00", is modulated up to "10" and "01" so that the data can not be demodulated correctly. Figure ID shows an example in a case where an amplitude of the four-level analog signal is partially deformed. In this case, the data that must be inherently demodulated to "00" is demodulated to "01" so that the data can not be demodulated correctly. In accordance with the second method mentioned above, the threshold voltages are interleaved to a received signal that is to be varied. Therefore, theoretically, in any case where there is a local decentering and an amplitude distortion, it is possible to demodulate a multi-level signal correctly. However, an element used to obtain the three threshold voltages is a resistance. Since it is not avoidable that each resistor has more or less distortion of a resistance value, in fact, it is almost impossible to obtain voltages of 17 percent, 50 percent and 83 percent of a potential difference between the maximum data voltage and the minimum data voltage for the three threshold voltages. Accordingly, it is assumed that there is an unbalanced amplitude distortion of the four-level analog signal reproduced by the frequency discriminator. Since a first unbent voltage and a third threshold voltage tend to suffer from an effect due to a variation of a resistance value, the first and third threshold voltages are less than a second level of a received signal or greater than a third level of the received signal. Figure 1E shows an example in a case where the third threshold voltage is shifted to the high level side as illustrated by a dotted line and dashes. In this case, the case that must be inherently demodulated until "01" is demodulated to "00", so that the data can not be demodulated correctly.

Correspondingly, an object of the present invention is to provide an apparatus and method for demodulating a multi-level signal which can correctly demodulate a multi-level signal without suffering from an effect due to a variation of the characteristics of the circuit elements. A related object of the present invention is to provide an apparatus and method for demodulating a multi-level signal that is as resistant to an amplitude path as for correctly demodulating a multi-level signal without displacing a level, even when there is a uniform distortion or unbalanced of an amplitude.

EXHIBITION OF THE INVENTION According to a first aspect of the present invention, a multilevel signal demodulation apparatus comprises: means for converting an analog input signal, of which the amplitude is modulated by a multiple level in a digital signal; a means for storing the digital signal obtained by this means of conversion; means for calculating the multiple data threshold in accordance with the digital signal that is stored in the storage medium; and means for demodulating the digital signal that is obtained by the conversion means, in accordance with the threshold multiple data, calculated by the calculation means in a signal in accordance with a level of the digital signal. In accordance with this modulation apparatus, the analog input signal of which the amplitude is modulated by a multiple level, is converted into a digital signal according to the level of the analog signal. Therefore, it is possible to correctly demodulate a multi-level signal without suffering from an effect due to a variation of the characteristics of the elements of the circuit. It is also possible to demodulate correctly without moving a level even when there is a uniform or unbalanced distortion. According to a second aspect of the present invention, a multi-level signal demodulation apparatus comprises: means for converting an analog input signal of which the amplitude is modulated by a multiple level in a digital signal; a means for storing the digital signal, which is obtained by the conversion means, wherein a predetermined requirement is satisfied; a means for calculating the threshold multiple data to judge a level of the digual signal in accordance with the digital signal that is stored in the storage medium; and means for demodulating a newer digital signal that is obtained by the conversion means, in accordance with the multiple data threshold calculated by the calculation means in a signal in accordance with a digital signal level, the demodulation means judges that the predetermined requirement is satisfied when the digital signal is at a higher level than a maximum threshold data or at a lower level than a minimum threshold data between the multiple threshold data, so that it is possible to correct the digital signal stored in the medium of storage, using the newest digital signal. Correspondingly, the analog input signal of which the amplitude is modulated by a multiple level is demodulated according to the level of the analog signal after converting the analog signal into a digital signal. In addition, when the level of the digital signal is higher than the maximum threshold or lower than the minimum threshold, the level of the digital signal is discriminated.

Therefore, it is possible to demodulate correctly without suffering from an effect due to a variation of the characteristics of the elements of the circuit. It is also possible to demodulate correctly without moving a level even when there is a uniform or unbalanced distortion. According to a third aspect of the present invention, there is an apparatus according to the second aspect wherein the storage means stores multiple prior digital signals that satisfy the predetermined requirement. According to the third aspect, multiple prior multiple digital signal thresholds having a level higher than the maximum threshold or a level lower than the minimum umbarl are obtained. Therefore, it is possible to demodulate correctly without suffering from an effect due to a variation of the characteristics of the circuit elements. In addition, it is possible to demodulate correctly without moving a level, even when there is a uniform or unbalanced distortion. According to a fourth aspect of the present invention, a multi-level signal demodulation method comprises the following steps: converting an analog input signal of which the amplitude is modulated by a multiple level, into a digital signal; store the digital signal that is obtained through the conversion step; calculating the multiple threshold data in accordance with the digital signal that is stored by the storage step; and demodulating the digital signal obtained by the conversion step, in accordance with the multiple data threshold calculated by the step of computing a signal in accordance with a level of the digital signal. Correspondingly, the analog input signal from which the amplitude is modulated by a multiple level is demodulated according to the level of the signal after converting the analog signal into a digital signal. Therefore, it is possible to demodulate correctly without suffering from an effect due to a variation of the characteristics of the circuit elements. In addition, it is possible to demodulate correctly without moving a level, even when there is a uniform or unbalanced distortion. According to a fifth aspect of the present invention, a multi-level signal demodulation method comprises the following steps: converting an analog input signal of which the amplitude is modulated by a multiple level, into a digital signal; storing the digital signal that is obtained by the conversion step where a predetermined requirement is satisfied; calculate the threshold multiple data to judge a level of the digital signal, in accordance with the digital signal that is stored by the storage step; and demodulating a newer digital signal that is obtained by the conversion step, in accordance with the multiple data threshold calculated by the computing step, in a signal conforming to a level of the digital signal, the demodulation step judges to be has met the predetermined requirement when the digital signal is at a higher level than a maximum threshold data or at a lower level than a minimum threshold level, between multiple threshold data so that it is possible to correct the digital signal stored by the step of storage, using the newest digital signal. Accordingly, the analog input signal from which the amplitude is modulated by a multiple level is demodulated in accordance with the level of the signal after converting the analog signal into the digital signal. Furthermore, when a level of the digital signal is higher than the maximum threshold or lower than the minimum threshold, the level of the digital signal is discriminated. Therefore, it is possible to demodulate correctly without suffering from an effect due to a variation of the characteristics of the circuit elements. In addition, it is possible to demodulate correctly without moving a level, even when there is a uniform or unbalanced distortion. According to a sixth aspect of the present invention, there is a method according to the fifth aspect wherein the storage step comprises a sub-step for storing the multiple previous digital signals that fill the predetermined requirement. According to the sixth aspect, multiple threshold values are obtained from multiple previous digital signals having a level higher than the maximum threshold or a level lower than the minimum threshold. Therefore, it is possible to demodulate correctly without suffering from a defect due to a variation of the characteristics of the circuit elements. In addition, it is possible to demodulate correctly without moving a level even when there is a uniform or unbalanced distortion. Additional objects and advantages of the present invention will be pointed out in the description that follows, and in part will be apparent from the description or may be learned by practicing the present invention. The objects and advantages of the present invention can be obtained and realized by means of the instruments and combinations indicated with particularity in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate the presently preferred embodiments of the present invention and, together with the general description provided above and the detailed description of the preferred embodiments. which will be provided below, serve to explain the principles of the present invention, wherein: Figures 1A-1E show a relationship between a normal waveform of a received signal and a waveform having a local offset or distortion of amplitude; Figure 2 is a functional diagram showing an example of a radio receiver including a multi-level signal demodulation apparatus of the present invention; Figure 3 is a functional diagram showing a structure of a demodulator portion of the multi-level signal demodulation apparatus according to the first embodiment of the present invention; Figure 4 shows a relationship between a reproduced data, and the first, second and third threshold levels of a multi-level signal demodulation apparatus, in accordance with a second embodiment of the present invention; Figure 5 is a functional diagram showing a structure of a demodulator portion of the multi-level signal demodulation apparatus according to the second embodiment of the present invention; Figure 6 is a functional diagram showing a structure of a demodulator portion of a multi-level signal demodulation apparatus according to a third embodiment of the present invention; and Figure 7 is a functional diagram showing a structure of a demodulator portion of a multi-level signal demodulation apparatus, in accordance with a fourth embodiment of the present invention.

BEST WAY TO CARRY OUT THE INVENTION A preferred embodiment of a multi-level signal demodulation apparatus in accordance with the present invention will now be described with reference to the accompanying drawings. [First Mode] Figure 2 is a functional diagram showing a modality of a radio receiver that includes a multi-level signal demodulation apparatus of the present invention. A radio receiver 1 has a function for receiving a message that is used, for example, in a radiolocation system. The radio receiver 1 comprises an antenna 10, a receiver portion 11, an A / D converter 12, a portion 13 of the demodulator, a CPU 14, a presentation portion 15, an alarm portion 16, an input portion 17 of key, a message memory 18, a battery 19, a portion 20 of the battery economizer and so on. The antenna 10 receives a radio signal supplied from a base station of a radiolocation service company, etc., (not shown) and sends the received signal to the receiver portion 11. The radio signal of the base station is a radio signal that is modulated with the digital data, for example, a four-level FSK signal. The portion 11 of the receiver includes a frequency discriminator etc. so that a FSK signal of four received levels can reproduce on a four-level analog data signal, that is, a four-level PAM signal (Pulse Amplitude Modulation) that is supplied to an A / A converter 12 D. The A / D converter 12 digitizes the output of the four-level analog data signal from a portion 11 of the receiver and supplies the digitized signal to the portion 13 of the demodulator. In accordance with the first embodiment, the four-level analog data signal is converted into an 8-bit digital data signal to be sent. Portion 13 of the demodulator compares the 8-bit digital data signal output from an A / D converter 12, with three threshold levels (first, second and third threshold levels as will be described below). In this way, the demodulated data is obtained in a di-bit form (2-bit unit) and sent to the CPU 14. In addition, the demodulator portion 13 is also controlled by the CPU 14. The CPU 14 is a unit, such as a microcomputer etc. to control an operation of the peripheral circuits in accordance with a program that is stored in an internal ROM. The CPU 14 includes a character generating ROM for sending a character code (a character pattern for presentation) corresponding to a character, a number, a symbol, etc. and a RAM used as a work area in addition to the ROM mentioned above. The display portion 15 comprises, for example, a liquid crystal display panel, a presentation buffer, an impeller, etc. to present information such as a message, etc. in the liquid crystal presentation panel. The alarm portion 16 issues a user an alarm, an input signal. The alarm portion 16 comprises, for example, a LED (Light Emitting Diode) that is turned on or blasted to send the alarm, in the input signal, a loudspeaker that sounds the alarm, a vibrator that vibrates to send an alarm , and so on. The input portion 17 of the key comprises an input means such as a power source switch, an operation key and so on. The message memory 18 is a memory for storing a received message data, wherein the CPU 14 controls writing and reading the message data. The battery saving portion 20 controls a power supply from the battery 19 to the receiver portion 11, in accordance with a signal provided from the CPU 14 to economize the battery 19 or to reduce a power consumption of the battery 19. example, in a case of a radio receiver in the radiolocation system that is adapted to receive only one signal supplied from the base station and having the address thereof, the battery saving portion 20 is operated to supply a power source for the receiver portion 11 only during the signal having the address thereof that can be supplied from the radio base station. Figure 3 is a functional diagram showing a detailed structure of the portion 13 of the demodulator shown in Figure 2. The portion 13 of the demodulator shown in Figure 3 is a modality of a level signal demodulation apparatus. multiple according to the present invention. The portion 13 of the demodulator comprises the displacement registers 102 and 103, the averagers 104, 105 and 106, a differential circuit 107, a divider unit 108, a subtraction unit 109, an adder 110, the comparators 111, 112 and 113, a discriminator 114, and the selectors 115 and 116. The shift register 102 is a register for storing M (e.g., M = 8) prior reproduced data, i.e., the data that is determined as a maximum value between the output of the data reproduced from the 12 A / D converter by the discriminator 114 (to be described later) In the first mode, eight 8-bit latch circuits are connected in series The shift register 102 is connected to the A / A converter 12 D and the CPU 14, through the selector 115. The selector 115 sends the data of an appropriate level corresponding to a maximum value from the CPU 14, when the power source of the radio receiver 1 is switched on or when the b ateria 19. The selector 115 is positioned so that the maximum data is pre-graduated in each step of the displacement register 102, that is, in eight bolt circuits. Accordingly, the shift register 102 is usually connected to the A / D converter 12 through the selector 115. In addition, the shift register 102 is operated to shift through the PS1 output of pulse signals from the discriminator 114., when the reproduced data of the A / D converter 12 is determined as being of a maximum value. Accordingly, the reproduced data of the A / D converter 12 is admitted (or is input to it) as a newest MAXRD maximum reproduced data, and then an older maximum reproduced MAXRD data is shifted (moved). The shift register 103 is a register for storing M (for example, M = 8) data reproduced earlier, that is, the data determined as a minimum value between the output of the data reproduced from the A / D converter 12 by means of discriminator 114. In the first mode, eight 8-bit latch circuits are connected in series. The shift register 103 is connected to the A / D converter 12 and the CPU 14, via the selector 116. The selector 116 sends the data of an appropriate level corresponding to a minimum value from the CPU 14, when it is connected a power source of the radio receiver 1 or when the battery 19 is exchanged. The selector 116 is positioned so that the minimum data is pre-graduated at each step of the shift register 103, that is, on eight latch circuits. Accordingly, the shift register 103 is usually connected to the A / D converter 12 through the selector 116. In addition, the shift register 103 is operated to travel through the pulse signal output PS2 from the discriminator 114, when the data reproduced from the A / D converter 12 is determined as being of a minimum value. Accordingly, the reproduced data of the A / D converter 12 is admitted (or is input to it) as a newest MINRD reproduced minimum data and then an older minimum reproduced data MINRD is erased (moved). The averager 104 is a circuit for averaging eight previous maximum reproduced MAXRD data stored in the shift register 102 in order to obtain the average MD data. The resulting data is supplied to the subtraction unit 109, the differential circuit 107 and the averager 106. The averager 105 is a circuit for averaging 8 previous minimum reproduced MINRD data stored in the shift register 103, in order to obtain the LD data. average. The resulting data is supplied to the differential circuit 107, the averager 106, and the adder 110. The differential circuit 107 is a circuit for obtaining a difference between the average MD data from the averager 104, and the average LD data from the averager 105, in order to obtain the differential MLD data. The resulting data is supplied to the division unit 108. The division unit 108 is a circuit in which the differential data MLD from the differential circuit 107 is divided by a constant "6" that is previously graded to obtain the data ND divided. The resulting data is supplied to the subtraction unit 109 and the adder 110. The subtraction unit 109 is a circuit for subtracting the data ND divided from the division unit 108 from the average MD data from the averager 104, in order to obtain a first data SD1 threshold. The resulting data is provided by the comparator 111. The averager 106 is a circuit for averaging the average MD data from the averager 104, and the average LD data from the averager 105 to obtain a second threshold data SD2. The resulting data is supplied to the comparator 112. The adder 110 is a circuit for adding the data ND divided from the division unit 108 to the average data LD from the averager 105, in order to obtain a third threshold data SD3. The resulting data is supplied to the comparator 113. The comparator 111 is a circuit for comparing the present reproduced RD data of the A / D converter 12 with the first threshold data SD1 from the subtraction unit 109 for sending the comparison data Cl. where, the comparison data Cl indicates whether the present reproduced RD data is higher than the first threshold data SD1 or not. The comparison data Cl is supplied to the discriminator 114. The comparator 112 is a circuit for comparing the reproduced RD data present from the A / D converter 12, with the second threshold data SD2 from the averager 106 for sending the comparison data C2. Wherein, the comparison data C2 indicates whether the present reproduced RD data is higher than the second threshold data SD2 or not. The comparison data C2 is supplied to the discriminator 114. The comparator 113 is a circuit for comparing the reproduced RD data present from the A / D converter 12, with the third threshold data SD3 from the adder 110 for sending the comparison data C3 . Wherein, the comparison data C3 indicates whether the present reproduced RD data is higher than the third threshold data SD3 or not. The comparison data C3 is supplied to the discriminator 114. The discriminator 114 is a circuit for judging which level of the presently reproduced RD data corresponds to in accordance with each of the comparison data Cl, C2 and C3 from comparators 111, 112 and 113. Next, an operation will be explained. A radio signal received by the antenna 10 is converted into a four-level data signal in the receiver portion 11. The data signal is further converted into an 8-bit digital data signal in the A / D converter 12, to be supplied to the demodulator portion 13 shown in Figure 3. In the 13th portion of the demodulator, it is calculated three threshold levels SD1-SD3 according to the eight MAXRD maximum reproduced data that have been previously stored in the shift register 102, and the eight MINRD minimum reproduced data that have been previously stored in the shift register 103. The first threshold data SDl is supplied to the comparator 111 from the subtraction unit 109. The second threshold data SD2 is supplied to the comparator 112 from the averager 106. The third threshold data SD3 is supplied to the comparator 113 of the adder 110. Accordingly, each digital data signal (the reproduced data admitted from the A / D converter 12 is compared to the threshold levels SDl, SD2 and SD3 by the corresponding comparators 111, 112 and 113, respectively, each comparator 111, 112 and 113 sends each comparison data Cl, C2 and C3, respectively, to the discriminator 114. In the discriminator 114, when all the comparison data Cl, C2 and C3 are "1", that is, when the reproduced data present RD is a maximum data plus When the first threshold data SD1 is raised, the data bit 11 of the bit is supplied to the CPU 14 as a demodulation data and the pulse signal PS1 is sent. The pulse signal PS1 is supplied to the shift register 102 as an imp ulso displacement, as will be described in detail below. In the discriminator 114, when the comparison data Cl is "0", and the comparison data C2 and C3 are "1", that is, when the reproduced data present RD is less than the first threshold data SDl and greater than the second threshold data SD2, the di-bit data "10" is supplied to the CPU 14 as the demodulation data. Further, when the comparison data Cl and C2 are "0", and the comparison data C3 is "1", that is, when the data reproduced present RD is lower than the second threshold data SD2 and higher than the third data. data threshold SD3, the data bit "01" is supplied to the CPU 14 as the demodulation data. Likewise, when all the comparison data Cl, C2 and C3 are "0", that is, when the reproduced data present RD is a minimum data lower than the third threshold data SD3, the data bit "00" is supplied to the CPU 14 as the demodulation data and the pulse signal PS2 is sent. The pulse signal PS2 is supplied to the shift register 103 as a displacement pulse. An operation in the case where the pulse signals PS1 and PS2 are sent from the discriminator 114 and are now explained. As described above, when the reproduced data present RD from the A / D converter 12 is higher than the first threshold data SDl, the discriminator 114 sends the pulse signal PS1 having a function as a displacement pulse. of the displacement register 102. When the reproduced data present RD from the A / D converter 12 is lower than the third threshold data SD3, the discriminator 114 sends the pulse signal PS2 having a function as a displacement pulse of the shift register 103. When the shift register 102 is supplied with the pulse signal PS1, the storage data stored in each latch is shifted by one. Therefore, the reproduced data RD that is sent from the A / D converter 12 and that is determined as being the data higher than the first threshold data SDl by the discriminator 114, is taken in the first lock of the register 102 of offset as the maximum or newest MAXRD data. At the same time, the oldest maximum data stored in the eighth lock of the scroll register 102 is shifted to be erased. That is, the eight maximum reproduced MAXRD data that is sent from the offset register 102 to the averager 104 is updated. In this way, the average MD data sent from the averager 104 to the subtraction unit 109, the differential circuit 107, and the averager 106 is changed. The first threshold data SDl sent from the subtraction unit 109, the second threshold data SD2 sent from the averager 106 and the third threshold data SD3 sent from the adder 110 are corrected, respectively. These three corrected threshold data SDl, SD2 and SD3 are defined as the threshold level when the level of the next reproduced data is determined. Similarly, when the shift register 103 is supplied with the pulse signal PS2, the storage data stored in each latch is displaced by one. In this way, the reproduced data RD that is sent from the A / D converter 12 and determined as being the data lower than the third threshold data SD3 by the discriminator 114, is admitted in the first lock of the shift register 103 as the newest minimum data. At the same time, the oldest minimum data stored in the eighth lock of the scroll register 103 is shifted to be erased. That is, the eight minimum reproducing data MINRD that are sent from the shift register 103 to the averager 105 are updated. Therefore, an average LD data sent from the averager 105 to the differential circuit 107, the averager 106, and the adder 110, is changed. The first threshold data SDl sent from the subtraction unit 109, the second threshold data SD2 sent from the averager 106 and the third threshold data SD3 sent from the adder 110 are corrected, respectively. These three corrected threshold data SDl, SD2 and SD3 are defined as a threshold level when a level of the next reproduced data is determined. In this manner, in accordance with the first embodiment described above, a signal modulated in amplitude of multiple levels such as a 4PAM signal etc. it is demodulated after the signal is digitized. Furthermore, in the following two cases, the first, second and third threshold values are corrected according to the RD data reproduced, more specifically, eight previous maximum and minimum data including the reproduced RD data. A case is one in which the level of RD data reproduced is higher than the first threshold level (maximum threshold level). The other case is that in which the level of the reproduced RD data is lower than the third threshold level (minimum threshold level). Accordingly, it is possible to correctly demodulate the multi-level modulated signal without suffering from an effect due to a variation of the characteristics of the elements of the circuit. Furthermore, it is possible to correctly demodulate the multi-level modulated signal without moving a level even when there is a uniform or unbalanced amplitude distortion. [Second Mode] In accordance with the first embodiment described above, certain circuits 104-110 of arithmetic operation and three comparators 111-113 are necessary to demodulate the data. Therefore, a circuit construction is more or less complicated. According to the second modality, a complete adder and multiple registers are used to demodulate the data. Figure 4 is a functional diagram showing a detailed structure of a portion of the demodulator according to the second embodiment of the present invention. In Figure 4, a demodulator comprises, for example, a controller 201, the registers 202, 203, 204, 206, 207 and 208, a shift register 205, a data selector 209, a code inverter 210, an adder 211 complete, a displacer 212 of tubular body, a discriminator 213 and the selectors 214, 215 and 216. The demodulator is adaptable to the receiver 1 shown in Figure 2. In this case, that is, in the case of adapting the demodulator to the receiver 1 shown in Figure 2, similarly to the portion 13 of the demodulator, the demodulator shown in Figure 4 is connected between the A / D converter 12 and the CPU 14. In order to easily understand a demodulation operation, a principle of the second modality will be explained first. As explained in the background of the invention, when there is a local decentering, all the levels in a four-level analog signal reproduced by the frequency discriminator, etc. they move towards the high level or low level side. When there is a variation of the characteristics of the circuit elements forming the frequency discriminator, etc., an amplitude of a reproduced four-level analog signal is partially or totally distorted. According to the first embodiment, to solve these problems, three threshold levels are obtained in accordance with the maximum and minimum data in the outputs of the data reproduced from the A / D converter 12. The level of the output of the data reproduced from the A / D converter 12 is determined in accordance with these three threshold levels. Unlike the first mode, according to the second mode, the output of the data reproduced from the A / D converter 12 is normalized before the demodulation. That is, the output of the data reproduced from the A / D converter 12 is re-graded so that an average of the maximum value and an average of the minimum value are "EO" and "20", respectively, by hexadecimal notation. . Figure 5 shows a relationship between a distribution of the level of the reproduced data that is sent from the A / D converter 12, the normalized values thereof and three threshold levels. The data RD is reproduced of 8 bits is observed by means of the graduation 256 from OOjj to FFfj (where H means a hexa-decimal annotation). Figure 5 shows an example of the 4PAM signal so that the distribution of levels includes four levels. Therefore, the three threshold levels for discriminating the level of the reproduced data are the same as those used in the first modality. If the average of the maximum data is represented by m and the average of the minimum data is represented by 1, the three threshold data (the first, second and third threshold data) SL1, SL2 and SL3 are represented as follows: DP (m - l) / 6 (1) SL1 = m - DP (5m + l) / 6 (2) SL2 = (m + l) / 2 (3) SL3 = 1 + DP (m + 51) / 6 (4) Since the reproduction data RD is normalized so that an average of the maximum value and an average of the minimum value are "EO" and "20", respectively, by the hexadecimal notation, from the first to the third threshold data Normalized SL1, SL2 and SL3 are represented as "CO", "80" and "40" by hexadecimal notation. After normalization, a lower virtual value VS (= OOjj) that is less than the average 1 of the data reproduced from the A / D converter 12 by a DP level is represented as follows: VS = 1 - DP ( 71 - m) / 6 (5) The reproduced RD data normalized, that is, the re-graduated SCL data is represented as follows: SCL = (RDL - VS) / 8 • DP (RDL - (71 - m) / 6) / 8 ((m - l) / 6) (6RDL - 71 + m) / 8 (m - 1) (6) In accordance with the second mode, the RD data reproduced from the A / D converter 12 it is processed according to the aforementioned equation (6). The portion of the demodulator shown in Figure 4 for carrying out the aforementioned operation is explained in detail. The portion 200 of the demodulator comprises a controller 201, the registers 202, 203, 204, 206, 207 and 208, a shift register 205, a data selector 209, a code inverter 210, a full adder 211, a displacer 212 of tubular body, a discriminator 213 and the selectors 214 and 215. In order to simplify an arithmetic operation, the averages of the maximum values and minimum values are not calculated during an operation, but the total values thereof are used. In accordance with the aforementioned construction, the controller 201 controls the entire portion of the demodulator. That is, the controller 201 controls each circuit in accordance with a control signal CS from the CPU 14, a maximum value detection signal MDTCT and a minimum value detecting signal LDTCT from the discriminator 213. The registers 212 and 213 are displacement registers storing each of them M maximum reproduced data MAXRD (similar to the first modality, m = 8) and m minimum reproduced data MINRD. Each input of the scroll registers 202 and 203 is connected to the data selectors 214 and 215. Similar to the first embodiment, an appropriate level corresponding to the maximum value and the minimum value is pregraduated in the shift registers 102 and 103 by the CPU 14 when a power source of the radio receiver 1 is switched on or when it is exchanged. the battery 19. The selectors 214 and 215 are connected to the output terminal of the A / D converter 12. The registers 202 and 203 supply the outputs thereof to the data selector 209. The register 204 is a shift register for storing the first threshold data SDl, the second threshold data SD2 and the third threshold data SD3. The first to the third threshold data SDl, SD2 and SD3 are pre-recorded by the CPU 14 and sent to the data selector 209 when the reproduced data of the A / D converter 12 is discriminated. The first to the third threshold data of SDl, SD2 and SD3 are typically "C0", "80" and "40" in the hexadecimal notation, but can be determined for each receiver based on the measured data. The shift register 205 stores a normalized data, that is, an input data (reproduced data) from the A / D converter 12 which is operated as will be described below. The shift register input terminal 205 is connected to a carrier output terminal CY of the complete adder 211.

The input terminal of the shift register 205 is an inversion input. The registers 206, 207 and 208 are registers for an arithmetic operation, each connected with an output of the tubular body displacer 212. The outputs (12-bit, 11-bit and 11-bit) of the registers 206, 207 and 208 are connected to the data selector 209. The output of the register 206 also connects to the complete adder 211. An input of the data selector 209 is connected to an output of the A / D converter 12, and each output of the registers 202, 203, 204, 206, 207 and 208, and the shift register 205. A 12-bit output data to be supplied to the code inverter 210 is selected by means of the data selector 209 under the control and the controller 201. A code of the output data from the data selector 209 is inverted or remains as it is and then it is supplied to the complete adder 211. The complete adder 211 is a circuit for receiving a 12-bit output data from the register 206 and a 12-bit output data from the code inverter 210 to add them together. The adder 211 can perform a subtraction operation if the code inverter 210 inverts the input data. The output of the entire adder 211 is connected to a tubular body displacer 212 and the shift register 205. The data resulting from the operation (carrier output) CY (1-bit) is supplied to the tubular body displacer 212, the shift register 205 and the discriminator 213. The carrier output is shown if an operation has been completed or not. A data resulting from the operation (12-bit) is supplied to the displacer 212 of tubular body. The tubular body displacer 212 is a circuit for dividing an output of the entire adder 211, that is, the data of the resulting division or subtraction by 21 and to multiply the output of the complete adder 211 by 2i in a simple manner. The tubular body register 212 is connected to an output of the complete adder 211. A resulting addition or subtraction data is sent as it is or after descending according to the mode. That is, the tubular body shifter 212 is scaled to a shift mode or to the usual mode by the controller 201. In the case of the shift mode, the data resulting from the operation is shifted downwards by i bit (where since m is 8 (= 2-3), i = 3). In the case of the usual mode, the output data of the complete adder 211 is sent as it is. The discriminator 213 is a circuit for judging a level and the data reproduced according to the data resulting from operation CY. Similarly to the first mode, the 2-bit demodulation data "00", "01", "10" and "11" are obtained corresponding to levels 0, 1, 2 and 3. A maximum detection signal MSTCT and a minimum detection signal LDTCT are supplied to the controller 201, corresponding to the detection of the maximum and minimum values. An operation of the second mode is explained. In the demodulator portion shown in Figure 4, eight maximum reproduced data MAXRD and minimum reproduced data MINRD from the A / D converter 12 are stored in each register 202 and 203, respectively. The first, second and third threshold data SDl, SD2 and SD3 are stored in the register 204. The controller 201 first graduates a mode of the tubular body displacer 212 in the usual way. The addition operation is implemented to add eight MINRD minimum reproduced data stored in register 203. In addition, the addition operation is also implemented to add eight maximum reproduced MINRD data stored in register 202. More specifically, in case of adding minimum value, the first minimum reproduced data MINRD from register 203 is supplied to full adder 211, through data selector 209 and code inverter 210 (which does not reverse the code). In addition, the first minimum reproduced data MINRD supplied to the complete adder 211 is supplied to the spreader 212 of the tubular body. In this way, the minimum reproduced data MINRD is stored in the register 206. When the minimum reproduced data MINRD stored in the register 206 sends to the complete adder 211, the following minimum reproduced data MINRD is supplied from the register 203 to the adder 211 complete through the data selector 209 and the code inverter 210 (which does not reverse the code). In the complete adder 211, the first minimum value (the minimum reproduced data MINRD) is added to the next minimum value (minimum reproduced data MINRD). The result (resulting addition data) is supplied to the tubular body displacer 212. In this way, the minimum reproduced data MINRD is read from the register 203 to be added to the resulting addition data, in stages so that a total value of eight previous minimum values is obtained. The total value of the minimum values is sent from the tubular body displacer 212 to the register 208. That is, the register 208 stores the total value of the minimum value. The eight previous maximum reproduced data MAXRD stored in the register 202 are obtained in a similar manner by an addition operation by the full adder 211. The total value obtained from the maximum value is sent from the tubular body displacer 212 to the register 207. That is, the register 207 stores the total value of the maximum values. Any operation to obtain the total value of the maximum values of operation to obtain the total value of minimum values can be implemented previously. The total value of the maximum values stored in the register 207 is supplied to the code inverter 210 (which does not reverse the code) by means of the data selector 209. The total value is supplied to the register 206 through the complete adder 211 and the tubular body displacer 212. The total value of the maximum values stored in register 206 is supplied back to full adder 211. At the same time the total value of the minimum values stored in the register 208 is supplied to the code inverter 210 by the data selector 209. The code inverter 210 inverts the code and supplies the inverted data to the complete adder 211. In the complete adder 211, the code of the total value of the minimum values is inverted, so that the total value of the minimum values is subtracted from the total value of the maximum values. A total subtraction value is supplied to register 207. That is, register 207 stores the total value of the subtraction. The controller 201 moves the tubular body displacer 212 mode from the usual mode to the displacement mode. Since i = 3 (m = 8), the displacement mode is a mode to scroll down through three bits. Therefore, after moving from the usual mode to the shift mode, the total value of the maximum values that have already been stored in the register 206 is added to the total value of the minimum values stored in the register 208 by the summing machine 211 complete The resulting addition data is supplied to the tubular body displacer 211 where the data is shifted downward by 3 bits and sent to the register 206. The resulting addition data stored in the register 206 that is moved downward by 3-bit is the average data for the total value (additional value) of all -eight previous maximum and minimum values. The controller 201 shifts the mode of the tubular body shifter 212 from the shift mode to the usual mode. The average data stored in register 206 is read to be supplied to full adder 211. At the same time, the total value of the minimum values stored in the register 208 is raised, to be supplied to the complete adder 211 through the data selector 209 and the code inverter 210 (which inverts the code). The complete adder 211 subtracts the total value of the minimum values from the average data.

The resulting subtraction data is sent from the tubular body displacer 212 to the register 206. That is, the register 206 stores the data resulting from the subtraction. At the time of completion of the aforementioned operation, the storage content of registers 206, 207 and 208 is as follows. Record 206: DR = (8M-7 • 8L) / 8 (7) Record 207: DT = (8M -8L) (8) Record 208: MINT 8L (9) where DR is the resulting subtraction data, DT is the total value of the subtraction and MINT is the total value of the minimum values. Then, an output from the A / D converter 12 (reproduced RD data) is added six times to the resulting subtraction data DR stored in register 206. More specifically, the resulting subtraction data DR stored in register 206 is supplied to full adder 211. Meanwhile, the RD data reproduced from the A / D converter 12 is sent from the data selector 209 to the code inverter 210 that does not reverse the data. In this way the reproduced RD data is supplied to the complete adder 211 as it is. The complete adder 211 implements the first operation to add the resulting RD data of subtraction and the RD data reproduced. The resulting addition data is sent from the tubular body displacer 212 to the register 206. Since the reproduced RD data is added six times, the first addition data is sent from the register 206 to the complete adder 211, so that the RD data reproduced is added to the first addition data. The resulting addition data is again stored in register 206, then similarly, the reproduced RD data is repeatedly added six times. Thus, after the six-fold vision is completed, the last addition data stored in the record 206 is represented as follows: Record 206: AR = 6RD + (8M-7 • 8L) / 8 (10) where AR is the resulting addition data. Then, the resulting addition data (resultant addition data AR stored in register 206) is divided by the total value of subtraction stored in register 207. This is an arithmetic operation shown in equation (6) above. More specifically, the following operations (a) and (b) are repeated p times determined (p is a natural number). (a) First, the resulting addition data AR is read from register 206 to be sent to full adder 211 and data selector 209. The resulting addition data AR sent to the data selector 209 is supplied to the full adder 211 through the code inverter 210 (which does not reverse the code). The entire adder 211 is operated to add the same data, ie, the two resulting addition data AR so that the added data is sent to the register 206 by the tubular body displacer 212. The tubular body displacer 206 stores the resulting duplicate addition data AR (which will be referred to as the resulting addition data AR2, below). (b) Second, the resulting addition data AR2 stored in register 206 is supplied to the adder 211 complete. Meanwhile, the total value of subtraction DT stored in register 207 is read to be sent to data selector 209 and code inverter 210 (which inverts the code). The output of the code inverter 210 is supplied to the complete adder 211. The entire adder 211 is operated so that the total subtraction DT value is subtracted from the resulting addition data AR2. The resulting subtraction data obtained by the above operation is supplied to the register 206 by the tubular body displacer 212 in case a correct operation is completed without borrowing. In this way, in the case of the correct operation, the register 206 stores the data resulting from the operation. On the other hand, when the correct operation is not implemented because a loan has occurred, the data resulting from the operation is not stored in register 206. The resulting addition data AR2 is currently stored in register 206 is retained so that the data CY resulting from the operation (= "1", 1-bit) sends to the shift register 205. The shift register 205 inverts an entry so that "0" is stored when the data CY resulting from the operation is "1". The predetermined times (p) mentioned above are according to a multiplicity of a signal that must be demodulated. In the case of demodulation of four levels, it is possible to set the predetermined times (p) arbitrarily, if the multiplicity is not less than 2. In practice, preferably, the predetermined times (p) correspond to the number of output bits of the A / D converter 12 (m = 8 in this case). The data resulting from the previous eight operation stored in the shift register 205, that is, the normalized reproduced RD data of the A / D converter 12 is read to be supplied to the register 206 through the data selector 209, the inverter 210 of code (which does not reverse the code), complete adder 211, and displacer 212 of tubular body. In addition, the normalized eight-bit data is read from register 206 to be supplied to full adder 211. Meanwhile, the third threshold data SD3 is read from the register 204 to be supplied to the full adder 211 via the data selector 209 and the code inverter 210 (which inverts the code). In the adder 211 complete, the third data SD3 threshold is inverted so that the third data SD3 threshold is subtracted from the normalized data. The data CY resulting from the operation representing the result of the supply operation to the discriminator 213. Similarly, the second and the first threshold data RD2 and RD1 are read from the register 204 to subtract from the normalized data. In any result, the data resulting from the operation is supplied to the discriminator 213. In the discriminator 213, it is determined that the level of the normalized data is in any of the levels 0 to 3 by comparing the input data CY, that is, the levels threshold. It is assumed that CYO is the result of the comparison compared to the third threshold level, CYl is the comparison result compared to the second threshold level and CY2 is the result of the comparison compared to the first threshold level. A relationship between CYO, CYL and CY "and the value of the level is as follows: When CYO = 0, CYL = 0, and CY2 = 0, the level is 0 (minimum level), when CYO = 1, CYL = 0, and CY2 = 0, the level is 1, when CYO = 1, CYL = 1, and CY2 = 0, the level is 2, and when CYO = 1, CYl = 1, and CY2 = 1, the level is 3 (maximum level) When the maximum level is detected, ie, the discriminator 213 determines that the present reproduced RD data is higher than the first SDl threshold data, the 2 bit data whose maximum detection data of 1-bit MDTCT and the minimum detection data of 1-bit LDTCT are "1" and "0", respectively, is supplied to the controller 201. The data Present reproduced RD that produces this result is stored in register 202 as MAXRD data reproduced maximum by controller 201. Since register 202 stores the maximum reproduced MAXRD input data again, the oldest maximum reproduced MAXRD data is cleared. When the minimum level is detected, that is, the discriminator 213 determines that the reproduced RD data present is lower than the third threshold data SD3, the 2 bit data whose maximum detection data of 1 MDTCT bit and the minimum detection data 1-bit LDTCT are "0" and "1", respectively, is supplied to controller 201. The reproduced RD data present producing this result is stored in register 202 as a reproducing data manumisor MINRD via controller 201. Since the register 202 stores the minimum reproduced data of the MINRD input again, the oldest minima reproduced data MINRD is erased. Thus, in accordance with the second embodiment described above, the circuit of the arithmetic operation comprises only one full adder 211. Therefore, it is possible to simplify the arithmetic operation circuit in comparison with the first mode. Furthermore, by using the register, the data can be retained for division and comparison by displacement, it is possible to correctly demodulate the multi-level signal whose linearity is incorrect by shifting the level of the signal. It is possible to replace the registers 202, 203, and 204 as the shift register by means of RAM to omit a space for the registers. The controller 201 is obtained by means of a random gate. However, the controller 201 may comprise a ROM so that it is possible to demodulate a multilevel multiplied signal in addition to the 4-level signal.

According to the second embodiment, described above, the data resulting from the 8-bit operation stored in the shift register 205 is compared with the first, second and third threshold data SDl, SD2 and SD3. However, the higher bit values (2 bit or 3-bit) of the shift register 205 can be supplied directly to the discriminator 213 for judging. That is, it is assumed that the first to the third threshold data are "CO", "80" and "40". If the upper 2-bit is "11", the level of the demodulated signal is 3. If the upper 2-bit is "10", the level of the demodulated signal is 2. If the 2-bit is " 01", the level of the demodulated signal is 1. If the upper 2-bit is" 00", the level of the demodulated signal is 0. In the second mode mentioned above, as an example, eight previous maximum reproduced data are used MAXRD and eight minimum reproduced data MINRD. Correspondingly, the displacer 211 of the tubular body moves downwards by means of 3-bit to obtain the average data thereof, in the case of the displacement mode. In the case of the four previous data MAXRD and MINRD, where i = 2, the displacer 211 of the tubular body is displaced downwards by 2 bits. It is possible to correct the first, second and third threshold data RD1, RD2 and RD3 stored in the register 204, interleaving with the data entry reproduced RD from the A / D converter 12. That is, when the register data 202 or 203 is updated, the first, second and third threshold data RD1, RD2 and RD3 stored in register 204 are changed or corrected by an arithmetic operation. This modification will be explained below. First, second and third threshold data are defined as RD1 ', RD2' and RD3 ', respectively. The first, second and third threshold data RD1 ', RD2' and RD3 'are represented as follows: RD1' = (5 • 8M + 8L) / (8x6) (5 • 8M + 8L) / (16x3) ( 11) RD2 '= (8M + 8L) / (8x2) (8M + 8L) / 16 (12) RD3' = (8M + 5 • (8L) / (8x6) (8M + 5 • (16x3) (13) It is assumed that the eight minimum reproduced data MINRD stored in register 203 have been transferred to register 206, when the maximum reproduced data MAXRD stored in register 202 is updated, Similarly to the second mode described above, register 208 and the complete adder 211 adds the maximum reproduced data MAXRD in the updated register 202. The maximum value of the resulting addition is stored in the register 207.

In order to obtain the second threshold data RD2 ', the addition data resulting from the maximum value stored in the register 207 is transferred to the register 206. In this case, the controller 201 sets the tubular body displacer 212 to the displacement mode of 4. bit. The 4-bit offset corresponds to the division by a denominator (= 16) shown in the aforementioned equation (12). In this way, the addition data resulting from the maximum value stored in the register 206 is added to the addition data resulting from the minimum value stored in the register 208 through the complete adder 211. The resulting addition data is shifted by 4 bits in the tubular body shifter 212 so that the resulting addition data is stored as the second threshold data RD2 'in the register 204. Then, the controller 201 shifts the body shifter 212 tubular in the usual way. In order to obtain the first threshold data RDl ', the resulting addition data of maximum value stored in register 207 is transferred to register 206. The same addition data resulting from the maximum value stored in registers 206 and 207 are added in the complete adder 211. The resulting addition data is sent to register 206. The resulting addition data stored in register 206 is added to the resulting addition data stored in register 207 in full adder 211. The resulting addition data is stored in register 206. The operations mentioned above are repeated three times. Further, after the controller 201 moves the tubular body shifter 212 to the 4-bit shift mode, the resulting addition data by a 5 • 8M operation stored in the register 206 is added to the addition data resulting from the value minimum stored in register 208 in full adder 211. The resulting addition data is supplied to the tubular body displacer 211 so that an operation corresponding to 5 • 8M + 8L is completed. The resulting addition data sent to the tubular body displacer 211 is shifted down by 4 bits according to the 4 bit shift mode to be sent to the register 206. In this way, an operation corresponding to (5 • 8M + is completed) 8L) / 16. The controller 201 resets the tubular body displacer 212 to the usual mode. In addition, the resulting addition data stored in register 206 is divided by three so that an operation (5 • 8M + 8L) / (16X3) corresponding to equation (11) is completed. More specifically, after the following operations (A) and (B) are repeated at the predetermined times, an operation (C) is implemented so that the aforementioned operation is completed. That is, (A) the significant bit representing three is subtracted from the most significant bit of the resulting addition data stored in register 206 (the initial value: (5 • 8M + 8L) / 16), which corresponds to three subtraction of the resulting addition data. If a correct subtraction has been made or not, it is determined whether or not there is a loan to be requested. Without a loan having occurred, it is considered as having undergone a correct subtraction. When the data resulting from the operation of 1-bit CY (= "1") is sent to the register 205, the resulting subtraction data is transferred from the displacer 212 of the tubular body to the register 206. When a loan has occurred, when the data CY resulting from the 1-bit operation (= "0") is sent to register 205, the data that is currently stored in register 206 is retained. Then, (B) the data stored in the register 206 sends directly to the complete adder 211 as well as the data stored in the register 206 that is sent indirectly to the complete adder 211 through the data selector 209 and the code inverter 210 (that does not reverse the code). The complete adder 211 adds this data to send the resulting addition data to record 206. In this way, the resulting addition data stored in the record 206 is updated to be the original duplicate data stored in the record 206. The number of repeat operations (A) and (B) is graded according to the multiplicity of a signal that goes to demodulate. In case of modulating the multilevel signal of four levels, when the multiplicity is not less than 2, the operation is repeated arbitrarily. In practice, preferably, the repetition number corresponds to the output bit number of the A / D converter 12. (C) Finally, the data resulting from the 8-bit operation stored in register 205 is sent to register 204, so that the first threshold data RD 'can be corrected. The third threshold data RD3 'is similar to the first threshold data RD1' described above. The resulting addition of the minimum value stored in register 208 is implemented for the operation corresponding to 5 • 8L, using register 206 and full adder 211. In this way, the resulting addition data is stored in register 206. In addition, the resulting addition data (8M) of the value, maximum stored in register 207 is added to the resulting addition data (5 • 8L) of the minimum value stored in register 206. The resulting addition data is stored in register 206 so that the operation corresponding to 8M + 5 • 8L is completed. Then, the tubular body shifter 212 is changed to 4-bit shifting mode so that the resulting addition data (8M + 5 • 8L) stored in register 206 is shifted downward by 4 bits to store the resulting addition data in record 206. In this way, the operation corresponding to (8M + 5 • 8L) / 16 is completed. The operation corresponding to equation (13) is implemented so that the last data ((8M + 5 • 8L) / 16) was stored in register 206 divided by three. The operations (A), (B), and (C) to obtain the first threshold data RDl 'are adopted to obtain the result of the operation by means of equation (13) in register 206. Therefore, the resulting data of the 8 bit operation stored in the register 205 is transferred to the register 204, as the third threshold data RD3 '. Even when the first, second and third threshold data are corrected by interlacing with the change of the maximum or minimum value, it is possible to obtain the same effect as the second modality described above. [Third Mode] In accordance with the second modality described above, when the discrimination result is either the maximum value and the minimum value, the data in register 202 or 203 or register 207 or 208 is not updated. It is possible to use an intermediate level to update the threshold level. In addition, according to the second mode, the data, except the threshold data, is changed when it is demodulated. On the other hand, according to the third embodiment, the threshold data is changed after the demodulation. The entire construction of the third embodiment is similar to the construction in Figure 2. The portion of the demodulator according to the second embodiment shown in Figure 4 is partially changed. Accordingly, the same circuit elements as the circuit elements in Figure 4 have the same reference numbers and the explanation thereof is omitted. Figure 6 is a functional diagram showing a structure of a portion of the demodulator according to the third embodiment. A portion of the demodulator in Figure 6 is adopted to receiver 1 shown in Figure 2. Similarly to Figure 13 of the demolulator in Figure 2, the demodulator portion is connected to the A / D converter 12 and the CPU 14. The demodulator portion comprises, for example, registers 202, 203, 206, 207 and 208, a shift register 205, a data selector 209, a code inverter 210, a full adder 211, a displacer 212 of tubular body, data selectors 214 and 215, a controller 216, a register 217, a discriminator 218, and a threshold generator 219. In a circuit different from the circuit in Figure 4, the controller 216 not only controls one operation of each circuit in Figure 6, but also controls a change operation based on the total data JRD resulting from the judgment of the discriminator 218. In a manner similar to the register 204 described above, the register 217 stores the first, second and third threshold data RD1, RD2 and RD3 so that its input is connects to the threshold generator 219. Similarly, to the aforementioned discriminator 213, the discriminator 218 determines the level of the reproduced data present RD according to the value of the data CY resulting from the operation. The data JRD resulting from the total judgment is supplied to the controller 216. The threshold generator 219 comprises a memory for storing the three threshold data to be pre-installed in the shift register 217 as the initial data, a memory for storing respectively the four normalized levels, and a portion of the arithmetic operation to obtain the average of the two data. The input and output of the threshold generator 219 are connected to the shift register 205 and the register 217, respectively. The threshold generator 219 generates three threshold data, that is, the first threshold data SDl ", the second threshold data SD2", and the third threshold data SD3"in the order of a higher level, then an operation will be explained. The modulation portion shown in Figure 6 is similar to the modulation portion shown in Figure 4. When each data resulting from the operation CYO, CY1 and CY2 is supplied to the discriminator 218, that is, when the result of the discrimination, the normalized 8-bit data stored in the shift register 205 is provided by the threshold generator 219. The data is stored in a corresponding area of the memory which is divided into four areas based on the levels. , (which corresponds to the non-receiver period in a communication receiver such as a radiolocation receiver, etc.), the portion of the arithmetic operation in the threshold generator 219 calculates the average gave the normalized data stored in each area of the memory. The average includes a maximum average data corresponding to level 3, a first intermediate average data corresponding to level 2, a second intermediate average data corresponding to level 1, and a minimum average data corresponding to level 0.

In the portion of the aforementioned arithmetic operation, a third intermediate average data is calculated between the maximum average data and the first intermediate average data, a fourth intermediate average data between the first and second intermediate average data, a fifth intermediate average data between the second intermediate average data and the minimum average data. These third, fourth and fifth intermediate data are sent to register 217 respectively as the first threshold data SDl ", the second threshold data SD2", and the third threshold data SD3. "Registry 217 corrects the threshold data based on these first to third data threshold SDl "to SD3." In this way, according to the third mode, it is possible to correct the threshold value, such as the intermediate threshold value between the maximum value and the minimum value. tracing characteristics to the variation of a received multi-level signal It is possible to allow the tracking characteristic to be duplicated for example in the case of the four-level signal.The tracing characteristic can obtain (nl) more times in the case of the n-level signal (n> 2) It should be noted that the memory of the threshold generator 219 can be divided into respective portions corresponding to the levels, or memories are provided multiples for the respective levels. The normalized data in each of the four levels is stored in the memory of the threshold generator 219 in the previous description. However, it is possible to store the normalized data of the second and third levels, that is, the first and second intermediate average data. In this case, the respective averages of the first and second intermediate data are calculated first and then the average of these two averages is calculated, that is, the average of the first and the second intermediate data. The resulting average data is the second threshold data. The average is calculated from the difference between the first and second intermediate average data. The resulting average data (referred to as U below) is added to the first intermediate average data. The resulting data is the first threshold data. In addition, the average U data is subtracted from the second intermediate average data. The resulting data is the third threshold data. In this way, the first, second and third threshold data are stored in the register 217 so that the correction of the threshold value is completed. [Fourth Mode] In accordance with the third embodiment, the circuit is constructed so that registers 202 and 203 are used to store the eight maximum reproduced MAXRD data and the eight minimum reproduced MINRD data. According to the fourth embodiment which will be described below, these registers 202 and 203 are omitted. According to the fourth mode, the data is changed after being demodulated. The entire construction of the fourth embodiment is similar to that of the first embodiment shown in Figure 2. The portion of the demodulator according to the third embodiment shown in the Figure 6 is partially changed. Accordingly, the same circuit elements as the circuit elements in the Figure 6 have the same reference numbers and the explanation of them is omitted. Figure 7 is a functional diagram showing a structure of a portion of the demodulator according to the fourth embodiment. A portion of the demodulator shown in Figure 7 is adopted to receiver 1 in Figure 2. Similarly to the portion 13 of the demodulator, the demodulator portion of the fourth mode is connected to the A / D converter 12 and the CPU 14. The portion of the demodulator shown in the Figure 7 comprises, for example, registers 206, 207 and 208, a shift register 205, a code inverter 210, a full adder 211, a tubular body displacer 212, a controller 216, a register 217, a discriminator 218, a threshold generator 219, a selector 220 of data and selectors 221 and 222. In a circuit different from the circuit in Figure 6, since there are no registers 202 and 203, the input of the data selector 220 is connected to the outputs of the A / D converter 12, the registers 206, 207, 208 and 217, and the shift register 205. The selector 221 stores the total value of the eight previous minimum reproduced data NIMRD which is pre-set in the register 208. The selector 222 stores the total value of eight previous maximum reproduced data MAXRD which is pre-set in the register 207. After presetting the data initial in registers 207 and 208, the selectors 221 and 222 are changed to the tubular body displacer 212. Next, an operation of the fourth mode is explained. It is assumed that the addition data resulting from eight previous maximal reproduced data MAXRD and the addition data resulting from eight previous minimum reproduced data MINRD are respectively stored in registers 207 and 208. This state is the same as a state in the second mode in where the additions of the eight previous minimum reproduced data MINRD stored in the registers 203, and the eight maximum reproduced data MAXRD previous stored in the register 202 are completed.

Similar to the second embodiment, discriminator 218 discriminates four levels. The 2-bit demodulation data is obtained using the data resulting from the operation CYO, CY1 and CY2. The total subtraction data DT is stored in the register 207. The total minimum data MINT is stored in the register 208. The total subtraction data DT is read from the register 207 to be supplied to the register 206 through the data selector 220, the code inverter 210, complete adder 211 and displacer 212 of tubular body. In this way, the total subtraction data is stored in the register 206. In addition, the total minimum data MINT is read from the register 208 to be supplied to the complete adder 211 through the data selector 220 and the code inverter 210 (which does not reverse the code). Since the total subtraction data of register 206 is supplied to full adder 211, the addition operation such as DT + MINT is implemented. The resulting addition data is sent from the tubular body displacer 212 to the register 207. In this way, the resulting addition data (DT + MINT) is stored in the register 207. The data stored in the registers 207 and 208 are changed to 8 M and 8L, respectively. Since the discriminator 218 supplies the JRD data resulting from the total judgment to the controller 216, the controller 216 controls an operation in accordance with the level. The JRD data resulting from the trial is the 2-bit data "00", "01", "10", or "11" according to level 0 (minimum), level 1, level 2, level 3 ( maximum) . For example, when the judgment result of the discriminator 218 is the maximum value, the controller 216 performs a following operation according to the JRD data resulting from the total judgment. First, the tubular body displacer 212 moves to the shift mode to read the total value 8 M of the maximum value stored in the register 207. This reading data is inverted in the code inverter 210 so that the data is displaced Descendingly by 3 bits in the tubular body displacer 212. In the tubular body displacer 212, the total value of the maximum value is divided by eight. The resulting division data is sent to register 206. Again, the total value 8M of the maximum value is read from register 207 so that the total value 8M is added to the resulting division data stored in register 206. The addition data The resulting result is stored in the register 206. Next, the addition data resulting from the record 206 is read so that the resulting addition data is added to the input of the reproduced RD data present from the A / D converter 12 in the adder 211 complete. The resulting addition data is supplied to the register 207 through the displacer 212 of the tubular body. The resulting addition data stored in register 207 is changed to RD (present reproduced data) + 7M. In case the result of the judgment by discriminator 218 is the minimum value, the controller 216 carries out the following operation according to the JRD data resulting from the total judgment. First, the tubular body shifter 212 is moved to the shift mode to read the total value 8L of the minimum value stored in the register 208. The read data is inverted in the code inverter 210 so that the data is shifted downwardly by means of 3. bit on displacer 212 of the tubular body. In the tubular body displacer 212, the total value of the minimum value is divided by eight. The resulting division data is sent to register 206. Again, the total value 8L of the minimum value is read from register 207 so that the total value 8L is added to the data resulting from the division stored in register 206. The data The resulting addition data is stored in the register 206. Then, the resulting addition data is read from the register 206 so that the resulting addition data is added to the input of the reproduced RD data present from the A / D converter 12 in the Adder 211 complete. The resulting addition data is supplied to the register 207 through the tubular body displacer 212. The resulting addition data stored in register 208 is changed to RD (the data reproduced present) + 7L. When the result of the judgment by the discriminator 218 is neither the maximum nor minimum value, no operation is implemented so that the data in each record remains as it is. Therefore, the content of records 207 and 208 is changed according to any case where the outcome of the trial is the maximum value, the minimum value or is not the maximum or minimum value. Since the correction of the first, second and third threshold data stored in the register 217 is the same as that of the third mode, the explanation of this is omitted. Therefore, according to the fourth embodiment, the same effect as in the third embodiment can be obtained. Industrial Applicability In accordance with a first aspect of the present invention, the analog input signal of which the amplitude is modulated by a multiple level is converted into the digital signal according to the level of the analog signal. Therefore, it is possible to correctly demodulate a multi-level signal without suffering from an effect due to a variation of the characteristics of the circuit elements. In addition, it is possible to demodulate correctly without moving a level even when there is a uniform or unbalanced distortion. According to a second aspect of the present invention, the analog input signal of which the amplitude is demodulated by a multiple level is demodulated according to the level of the analog signal after converting the analog signal into a digital signal. In addition, when the level of the digital signal is higher than the maximum threshold or less than the minimum threshold, the level of the digital signal is discriminated. Therefore it is possible to demodulate correctly without suffering from an effect due to a variation of the characteristics of the elements of the circuit. In addition, it is possible to demodulate correctly without moving a level even when there is a uniform or unbalanced distortion. In accordance with a third aspect of the present invention, multiple prior thresholds of the multiple digital signals having a level higher than the maximum threshold or a level less than the minimum threshold are obtained. Therefore, it is possible to demodulate correctly without suffering from an effect due to a variation of the characteristics of the circuit elements. In addition, it is possible to demodulate correctly without moving a level even when there is a uniform or unbalanced distortion. According to a fourth aspect of the present invention, the analog input signal of which the amplitude is modulated by a multiple level is demodulated according to the level of the signal after converting the analog signal into a digital signal. Therefore, it is possible to demodulate correctly without suffering from an effect due to a variation of the characteristics of the circuit elements. In addition, it is possible to demodulate correctly without moving a level even when there is a uniform or unbalanced distortion. According to a fifth aspect of the present invention, the analog input signal of which the amplitude is modulated by a multiple level is demodulated according to the level of the signal after converting the analog signal into the digital signal. In addition, when a level of the digital signal is higher, than the maximum threshold or less than the minimum threshold, the level of the digital signal is discriminated. Therefore, it is possible to demodulate correctly without suffering from an effect due to a variation of the characteristics of the circuit elements. It is also possible to demodulate correctly without moving a level even when there is a uniform or unbalanced distortion. In accordance with a sixth aspect of the present invention, multiple threshold values of multiple previous digital signals having a level higher than the maximum threshold or a level lower than the minimum threshold are obtained. Therefore, it is possible to demodulate correctly without suffering from an effect due to a variation of the characteristics of the circuit elements. In addition, it is possible to demodulate correctly without moving a level even when there is a uniform or unbalanced distortion. Additional advantages and modifications will occur to those skilled in the art. Therefore, the present invention in its broader aspects is not limited to the specific details, representative devices, and illustrated examples shown and described herein. Correspondingly, various modifications may be made without departing from the spirit or scope of the concept of the general invention as defined by the appended claims and their equivalents.

Claims (6)

CLAIMS:

1. A multi-level signal demodulation apparatus comprising: means for converting an analog input signal of which the amplitude is modulated by a multiple level in a digital signal; means for storing the digital signal that is obtained by the conversion means; means for calculating the multiple threshold data in accordance with the digital signal that is stored in the storage medium; and means for demodulating the digital signal that is obtained by the conversion means in accordance with the multiple threshold data calculated by the means of computing in a signal according to a level of the digital signal.

2. A multi-level signal demodulation apparatus comprising: means for converting an analog input signal of which the amplitude is modulated by a multiple level in a digital signal; means for storing the digital signal that is obtained by the conversion means, wherein a predetermined requirement is satisfied; means for calculating the multiple threshold data for judging a level of the digital signal in accordance with the digital signal that is stored in the storage medium; and a means for demodulating a newer digital signal that is obtained by the conversion means, in accordance with the multiple threshold data calculated by the means of computing in a signal according to a level of the digital signal, the demodulation means judging that the predetermined requirement has been satisfied when the digital signal is at a higher level of a maximum threshold data or at a lower level than the minimum threshold data between the multiple threshold data, so that it is possible to correct the digital signal stored in the storage medium using the newest digital signal.

3. An apparatus according to claim 2, wherein the storage means stores the multiple previous digital signals that have filled the determined requirement.

4. A multi-level signal demodulation method comprising the following steps: converting an analog input signal of which the amplitude is modulated by a multiple level, into a digital signal; store the digital signal that is obtained through the conversion step; calculate the multiple threshold data in accordance with the digital signal that is stored by the storage step; and demodulating the digital signal that is obtained by the conversion step in accordance with the multiple threshold data calculated by the step of computing in a signal according to a level of the digital signal.

5. A multilevel signal demodulation method comprising the following steps: converting an analog input signal of which the amplitude is modulated by a multiple level in a digital signal; storing the digital signal that is obtained by the conversion step where a predetermined requirement is satisfied; calculating the multiple threshold data to judge a level of the digital signal in accordance with the digital signal that is stored by the storage step; And demodulating a newer digital signal that is obtained by the conversion step in accordance with the multiple threshold data calculated by the step of calculating in a signal according to a level of the digital signal, the demodulation step judges to be satisfied the predetermined requirement when the digital signal is at a higher level than a maximum threshold data or at a lower level than a minimum threshold data between the multiple threshold data, so that it is possible to correct the digital signal stored by the storage step, using the newest digital signal.

6. A method according to claim 5, wherein the storage step comprises a sub-step of storing the multiple previous digital signals that have filled the predetermined requirement.