MXPA96004356A - Improvements in an apparatus and method of use of radiofrequency identification tags - Google Patents

Abstract

A radiofrequency identification tag integrated circuit is provided with an antifuse circuit (10) for field programmability at high speed and low power using transient radiofrequency pulses, a self-calibration circuit (38, 40, 44, 46, 48, 50) for calibrating a receiver oscillator (34) with an external calibration reference signal, a communications bit and frame synchronization circuit (72, 74) for recognizing a received unique pattern violating an error detection code check, a carrier signal modulation (80, 82, 84) scheme for remotely supplying data and power to the tag, and a power supply rectifier including Schottky diodes (96, 98, 100, 102) fabricated on sapphire (106) or a passivated surface (122) for inter-diode isolation and isolation from other circuits.

Description

IMPROVEMENTS IN AN APPARATUS AND METHOD OF USING LABELS FOR IDENTIFYING RADIO FREQUENCIES BACKGROUND OF THE INVENTION 1. Field of the Invention The invention relates to radio frequency identification devices used to tag or identify objects and, in particular, devices for identification of radio frequencies. radio frequencies that can be programmed transiently, self-calibrated remotely, switched on remotely during data communication and implemented using a high frequency isolated monolithic rectified. 2. Description of the Prior Art RFID Memory Low Power Antifusers An apparatus or label for radio frequency identification (hereinafter referred to in this description as an "RFID tag") is a device that can be attached or attached to another object, that the RFD3 tag used to identify when required remotely by an interrogating circuit. The RFID tag is programmed as such or can be programmed after association with the object to return a signal to the interrogator circuit to provide selected information related to the attached object that is within the area of the interrogator circuit. More simply, a small electronic label is attached to an object and the label is read by a reader. New data can be added to the label by the programmed and the data received from the label can be read on a display screen, stored or subsequently uploaded to a personal computer or linked directly to a computer system.

RFID tags have an advantage over bar codes and bar code readers that perform similar functions in that the RFTD tag can be embedded within the object and still be read whenever the material enters the RFID tag and the Reader is not a driver. Therefore, a line of sight for an RFID tag is not required, which is required in any other bar code reader. This allows the RFID tag to work in very difficult environments. In addition, the RFID tag has the ability to have digital data added after being attached to the object, has a greater data capacity and can be read at much greater distances than those reachable by optical bar code readers.

To date, the cost of RFID tags, however, has limited penetration of the market by the device due to the high cost associated with these RFID tags.

Ishihara et al., "Antifusible memory apparatus with method for establishing capacitor with switches" US Patent 5,299,152 (1994) discloses a condensed-loaded pumping circuit in which signals are applied to doors for pumping a capacitor element with the purpose of subjecting an antifusible coupled to the capacitor for a dielectric interruption for programming purposes. The pumping load is certainly not transient and requires considerable energy, which makes the circuits and methodology impractical for most RFID tags.

Therefore, what is needed is an RFID tag that can be manufactured at low "Cost, program and run with little energy, program in the field and still retain each of the advantages of RFID tags on bar codes as presented above.

Auto Synchronization Calibration for an RFTD Tag. A persistent problem with low energy RFD3 tags is the remote calibration of the circuit to allow information sent to the RFID tag to be properly decoded. If the clock signals or discrimination levels are properly calibrated on the RFID tag appropriately or if such calibration is not maintained as the environmental circumstances of the tag change, then the transfer of information from and to the tag is It becomes unreliable. Consider first some self-calibration schemes of the prior art used in other applications.

Goffin, II, "Method and Apparatus for a Calibrated Electronic Synchronization Circuit" US Patent 5,117,756 (1992) sets an internal oscillator by comparing its output with a control signal. A precision calibration pulse is applied to the timing circuit that counts the output cycles of a variable frequency oscillator during the pulse period. This account is stored and compared to the reference account to produce an error account. The error count is combined with a previously stored reference account to produce a new control signal that drives the outputs of the oscillator to a new frequency.

The calibration circuit of Goffin, II, is used in a time delay circuit , calibrated for the extended ignition of explosive products. The application is to minimize the effects of explosions on nearby structures by reducing the peak-to-peak amplitude of the earth vibration frequency produced by the explosion by coordinating the ignition of a plurality of explosive charges. Goffin achieves the above with an on-board calibration pulse derived from a time reference and then calibrates the detonation timing circuit with it to compensate for fluctuations, ambient temperature, humidity and pressure that could cause a variation in the local oscillator rhythm . Goffin is not interested in a remote communication circuit, but rather with the calibration of a plurality of detonator circuits with each one, all connected by hard wires.

Weaver, "Electronic Frequency Control for Radio Receivers" US Patent 2,501,883 (1950), also generally describes a circuit that adjusts an internal oscillator by comparing its output with a control signal. Weaver's goal is to provide a local rhythm frequency and appropriate frequency ratio with a carrier. In particular, Weaver seeks to maintain a local oscillator set to generate a wave that has substantially the same frequency relationship with the received carrier as that which existed prior to the fading of the carrier. Weaver achieves this by combining a wave derived from the received carrier with a locally generated reference wave to produce a control voltage whose magnitude and polarity are determined by the sum or difference of vectors of the combined waves. A ballast tube is connected to control the frequency generated by the oscillator. The filter of the reactance tube is coupled to two polarization circuits, which in turn are driven by the control voltage.

The information transmitted to an RFID tag is decoded either by detecting to the amplification the variation in the amplitude (AM) or frequency or equivalently the phase change or time delay (FM) of the carrier signal, depending on the communication protocol that is have chosen as standard. Changes in the amplitude of the carrier signal are economically detected in conventional RFID tag receivers, but are susceptible to noise interference. In the transmission of digital information, the loss of only a part of data can, if inappropriate, cause catastrophic consequences.

The detection of a frequency change is less susceptible to sound interference but requires that the RFID tag receiver be able to detect changes in the carrier signal as opposed to the calibrated standard. RFID tag receivers typically rely on some type of internally tuned circuit to compare the input signal with the standard to detect the frequency variation. However, the RFID tag receiver depends on the incoming bearer signal as a reference itself, as is almost always the case with RFD3 tags, it is inherently impossible to detect changes in the incoming signal using standard FM techniques.

Therefore, what is needed is a method by which a label circuit RFD3 remote can calibrate itself with respect to an input signal that allows the information to be decoded after finishing the calibration, such decoding would not have been possible before the calibration.

Synchronization of Bits and Frames It is also well known that in all communication protocols some means are required to determine which bit is the first data in a digital data transmission. This determination process becomes more difficult in wireless devices. Since the transmitting apparatus can be at one end of a range of operations, since the escape of noise and signals makes the reliable detection of digital data difficult, as well as the validation of synchronization at both bit levels and data frames.

Wireless devices usually move in and out of range quickly. Therefore, it is an advantage if the bit synchronization is achieved in a minimum of time so that the wireless apparatus can start looking for frame synchronization as soon as possible. Normally, the ability of the wireless device to do the above makes a critical difference in whether the communication is successful or not.

In some RFJD tags a "normal" data protocol violation is used to identify the beginning of a data frame. Milheiser, U.S. Patent 4,730,188 teaches that the use of Manchester codes defines a protocol that has a change of state in each bit time. The data box includes a frame maker that contains a preamble with a specific bit pattern followed by a violation of the Manchester bit synchronization protocol in which the rate of change of state is decreased to 1 Vi times for intervals of 3 bits, followed by the identification of the data in which the rhythm of the bits is restored. This type of bit synchronization is useful in the Milheiser application where the label transmits to a reader, but the RFID tag does not receive encoded data.

Even in Milheiser's application, there are some disadvantages. Since Milheiser must first achieve bit synchronization, the use of the closed phase cycle is necessary, which uses feedback from a received frequency transition to adjust a rhythm to be in sync. If the protocol violation occurs at that moment of time, the cycle in closed phase will try to synchronize at a lower 1/3 rate. The result is that the synchronicity of the bits is delayed in a frame that could be read but it is not.

The prior art has also devised an alternative approach that is not subject to the disadvantages of the Milheiser protocol. According to this alternative approach, a unique data value is assigned as a frame maker, it is then forbidden to use said unique value as a data pattern. This approach allows all or a part of the data frame to be used for bit synchronization. The unique data pattern should not be a pattern that the user may want to use, since it is forbidden to prevent ambiguity. If the data pattern is required, an alias is created which is then translated back to the prohibited value at a later time. This creation of an alias and its subsequent translation is an uncomfortable solution in most applications.

This approach also leads the user to choose a value that is all 1 0 all 0 for the unique pattern. Such a pattern is not a practical option since the memory in most of the devices of the request is usually initialized either to value 1 or 0 in any case.

Lee, "Fix for Fault or Error Detection", US Patent 4429,391 (1 84), describes a fault and error detection arrangement for detecting transmission and routing errors made in a central data transmitter and receiver in communication with peripheral circuits in which the parity bits of certain data words are transmitted by the central data transmitter after being intentionally inverted by the central parity inverter to a known sequence. The purpose of the investment every predetermined number of tables is used for synchronization. In particular, the central parity inverter inverts the parity bits every nine data words in response to the parity control signals transmitted by the sequence generator.

Thus, Lee seeks the violation of repetitive parity on a periodic basis to establish coordination. The disadvantage, however, is in cases where there is signal fading, which is common in RFID tag devices, an insufficient number of synchronization parity violations can be received to reliably establish the pattern or that the The pattern can be transmitted in an unreliable manner, thus leading to substantial errors in synchronization.

Terrab et al, "Method and Apparatus for Ensuring the Generation of CRC Errors by a Data Communication Station Experiencing Exceptions in the Transmitter", US Pat. No. 5,195,093 (1993), shows a scheme of generation of unique codes that uses a change of parity. Each byte of serial bit stream is transmitted sequentially. If an exception occurs in the transmitter, the byte before the exception transmits normally. However, only the first seven bits of the last byte are transmitted. The parity bit is sent as an eighth bit of the last byte ^ securing a parity non for the previous bit stream. Thereafter, an even parity of bytes is sent to ensure that the entire message has parity non. A receiving station interprets two consecutive bytes having the default data pattern as the CRC, thus ensuring that the receiving station will reject the frame.

Thereafter, what is needed is some kind of method to achieve the synchronization of bits and frames in digital signals transmitted between radio frequency identification labels and readers in a way that is very simple and yet efficient to implement in an integrated circuit.

Data communication and Energy Normally RFID systems transmit a carrier signal and then divide the carrier frequency into the tag to use the signal as an internal clock. The information stored in the label is then transmitted sequentially from the label. A label that operates in this way is a read tag only. The information on the label can be entered during the manufacturing of the label by making direct electrical contact with the external connectors or having a charged battery or capacitor physically connected to the label.

There is a recognized need to be able to add information within the RFID tag remotely in the field instead of having the information loaded inside the tag only during its manufacture. Remote programming and wireless programming without making any physical contact with the label can only be achieved if energy and information are supplied to the label at the same time. Programming the label requires substantially more energy than simply reading the label. The methods of the prior art for remote programming depend on the AM modulation of the signal or the FM modulation of the frequency to communicate with the tag. Again AM is susceptible to noise interference and FM requires significant sensing or detection circuits built into the label.

Consider first how the previous technique has transmitted data and energy in carrier signals. Kobayashi et al., "Apparatus for Digitally Transmitted Remote Control", US Pat. No. 4,914,428 (1990), describes the use of a time alteration between signal synchronization. The transmitted digital encoded instruction is composed of a sequence of synchronization pulses having a predetermined period and data pulses that are inserted between successive synchronization pulses at predetermined positions depending on whether the data pulses represent a 0 or 1 bit. receiver circuit distinguishes between bits 1 or 0 by detecting the length of the interval between the leading end of a synchronization pulse and the leading end of an adjacent data pulse and determines the existence of noise, if more than one data pulse is detected between successive synchronization pulses. The length of each data word that is sent is constant regardless of the numbers of I s and 0's in the word so that the detection of more than one data pulse between successive synchronization pulses of a constant period is interpreted as noise. Kobayashi thus uses the delay to distinguish between 0's and binary l's of a periodic synchronization pulse.

Stobbe et al., "Microchip for Portable Field Programmable Detection" Patent US Pat. No. 5,218,343 (1993) shows a system for transmitting energy and information to a remote circuit at the same time using external load capacitors, an internal oscillator, an AM signal from the chip and a periodic variation to distinguish between 0's and binary l's. The chip of the RFID tag in the Stobbe discovery is provided with a charge capacitor capable of storing electrical energy of the RF signal so that the microchip on the tag has power during the pauses of the pulses of the RF signal. The microchip includes a memory circuit for storing the identification code of the microchip in a code generator that is coupled to the memory circuit to generate an RF signal that is modulated with the identification data. A switch element disconnects a resonant circuit in the microchip when the identification data is transmitted back to the read / write device. The resonant circuit serves to program the microchip memory circuit and the tag in the field by receiving pulse / pause modulation (PPM) signals from the RF carrier signal to allow the identification code of the tag to be altered. Strobbe describes a mix of commands and data using AM modulation.

Kriofsky et al., "Transmitter Arrangement - Inductively Coupled Receiver" US Patent 3,859,624 (1975), discloses a conventional low frequency label that feeds energy through an inductive coupling so that the label generates unique coded information from sending back to the reader. The encoded information is not, however, transmitted as part of or modulation of the inductive energy signal.

Therefore what is needed is a method to remotely deliver an RFD3 tag while at the same time transmitting information to the tag.

Some means have been found by which the carrier signal that transmits to the label can at the same time deliver data that sensitive and energy.

Rectifiers for RFD3 Labels In current RFID label designs, carrier signals are rectified through the use of transistors on the chip that are normally slow, since there is no need for fast response times. A conventional full wave bridge rectifier that uses 4 diodes as shown in Figure 9 is not normally used in an RFTD tag because the parasitic links formed in a conventional monolithic integrated circuit, by which a diode bridge would be made, the structure would be inoperable in the application of an RFD tag > .

Figure 10 is a cross section of a typical integrated circuit design for a rectifier bridge as illustrated in Figure 9. The links 86 in the circuit of Figure 10 become inclined forward when the AM signal is applied to the contacts 88 and 90 corresponding to the same links referred to in the scheme of Figure 9.

Trying to implement a transmitter structure in a higher frequency range such as 915 megahertz or 2.5 GHz in an RFID tag leads to even greater difficulties. First, MOS transistors must be scaled to operate at such speeds or a high-speed bipolar device as when using a biCMOS process. Both types of transmitting technology require a much higher production cost and the parasitic capacitance in such devices has a substantially greater effect as the frequency in the operation increases.

Therefore, what is needed is a method for rectifying a carrier signal transmitted to an RFID tag for the purpose of energizing said tag that is not subject to the defects of the prior art.

BRIEF SUMMARY OF THE INVENTION The invention is a method for programming a radio frequency identification apparatus comprising providing an antifusible in a memory cell coupled to a line of bits in the radiofrequency identification apparatus. A loose capacitance in the bit line is loaded. The loose capacitance is selectively discharged by the antifusible to draw a maximum high current from the loose capacitance charged to program the antifusible. As a result, the antifusible is programmed at high speed and with little energy.

Charging the loose capacitance involves charging the capacitance to a voltage in excess of the antifouling programming voltage. Normally charging the loose capacitance in the bit line charges the capacitance with approximately 60 to 100 microwatts of energy or less.

The selective discharge of the antifusible is carried out in an example by coupling the antifusible through a transistor input to ground. The input transistor has a maximum saturation current capacity. The antifüsible has a programming time defined by a predetermined duration of time. The loose capacitance on the bit line is charged to an energy level so that the saturation current is achieved by the antifluid and the transistor during the programming time of the antifusible.

In other words, the invention is a method for programming an antifusible having a minimum programming time at high speed with low energy comprising charging a bit line coupled to the antifusible at a predetermined voltage and thus at a stored and predetermined energy level. . The bit line has a chargeable capacitance. The bit line is discharged through the antifusible at high speed substantially equal to the minimum programming time required by the antifusible to generate a voltage and current through the antifusible enough to program the antifusible when using a low average of energy.

The invention is also a method for remote auto-calibration of the circuits of the RFID tag which comprises receiving an external signal having a characteristic parameter and receiving an internal signal having a characteristic parameter. The characteristic parameters of the external and internal signals are compared. An error signal indicative of the difference in the characteristic parameters in the external and internal signals is generated. A correction signal is generated which when applied to the remote circuit compensates the internal signal to allow the calibration of the external signal. As a result, the remote RFID tag circuit is calibrated with respect to the external signal for reliable and inexpensive communication with it.

Generating the correction signal comprises generating a correction signal from the scilator to adjust the internal signal within a predetermined tolerance of the external signal.

In an alternative example, generating the compensation signal comprises generating a correction factor to be used in the operation of the remote RFID tag circuit where the error in the characteristic parameter between the external and internal signals remains substantially constant during times of operational interest of the Remote RFID tag circuit.

The invention includes a method wherein the operational characteristics of the circuit of the remote RFID tag changes in periods of time greater than those periods of time of operational interest of the circuit of the remote RFID tag. The method further comprises repeating the steps of receiving the external / internal signals, comparing the characteristic parameters, generating an error signal and generating a correction signal to update the compensation signal as the error signal slowly changes over time.

In a particular instance, generating the correction signal comprises generating a signal for choosing a compensation RC time constant for coupling to the oscillator.

The invention is also defined as an apparatus for auto calibrating a remote RFID tag circuit comprising a comparator coupled to an external signal and an internal signal that will be calibrated with respect to the external signal. The comparator generates an error signal indicative of the difference in a characteristic parameter of the external signals , **. internal A processor circuit is coupled to the comparator and is responsive to the error signal to generate a compensation signal that when applied to the label circuit Remote RFID allows calibration of the internal signal of the remote RFID tag circuit by calibrating with the external signal received by the remote circuit. As a result, the remote RFID tag circuit is provided with economical and reliable calibration for communication.

Thus it is understood that in one instance the apparatus further comprises a memory coupled to the processor circuit for storing the compensation signal to maintain the calibration of the remote RFID tag circuit.

The apparatus further comprises an oscillator in the remote circuit for generating the internal signal and an RC network having a plurality of RC values. The compensation signal of the processor circuit selects one of the RC values to couple the oscillator to maintain a characteristic parameter of the calibrated internal signal within a predetermined tolerance of the external signal.

In another example, the compensation signal generated by the processor circuit is a correction factor indicative of the error between the internal and external signals. The correction factor is applied by the processor circuit to operations within the remote RFED tag circuit to maintain a reliable calibration with the external signal. In particular, the correction signal is provided at the ratio between the characteristic parameter for the external signal and the internal signal.

The invention is further defined as a method for providing synchronization in data communication comprising verifying a communication data stream having a predetermined error correction protocol for a unique data bit pattern and determining whether the unique data pattern violates the error verification protocol. The synchronization of the single data pattern is used as a synchronization signal if the error verification protocol is violated. As a result, bit and frame synchronization is achieved anywhere within the data bit pattern. The unique pattern is a unique pattern that is normal for normally received data. In the illustrated example, determining if a violation in the error correction has occurred is determining if a violation of the parity error has occurred.

More specifically, the data stream is organized into words and the single data pattern comprises at least one word subject to the error correction protocol. The word has a bit length at least equal to the predetermined minimum so that the probability of creation in a normal data stream the single pattern with violation to the error correction is less than a predetermined acceptable minimum.

The invention is an apparatus for providing a synchronization marker comprising an error correction circuit for receiving a data stream in signal. A decoder verifies the data stream in signal by a unique pattern and a violation to the error protocol in simultaneous parity. The decoder is coupled to the error correction circuit and disconnects the error correction output in the case of simultaneous detection of single data pattern and violation to error correction to generate a synchronization signal. The error correction circuit is a parity checker.

The invention is a method of providing power and communicating data to a wireless remote RFTD tag circuit comprising transmitting a carrier signal to the circuit to provide power to the circuit. The carrier signal is modulated at low levels using pulse amplitudes equal to or less than a predetermined maximum. The predetermined maximum is determined by the longest duration at which the carrier signal can be turned off before the circuit of the remote R? TD label loses the stored energy to a sufficient degree to make the operation of the remote RFID tag circuit unreliable The carrier signal is modulated by pulses that have at least two distinguishable pulse amplitudes. The pulse amplitudes are correlated with the information transmitted to the circuit of the remote RFID tag. In another example, the carrier signal is modulated by at least three pulses of different pulse amplitudes to communicate binary data and control signals. The modulation is at a frequency substantially lower than the carrier signal so that the remote circuit is modulated at the reduced frequency at lower energy. For example, the carrier signal is modulated with a cycle of performance of or less than a maximum predetermined by the minimum performance cycle in which the circuit of the remote RFID tag will continue to operate reliably.

The invention is further an improvement in a diode rectifier having a plurality of diodes in an RFDD tag comprising an insulating material disposed below and between each of the diodes in the rectifier to electrically isolate each diode "Of each of the other diodes within the rectifier to prevent the forward impulse of any of the diode links at high frequencies.

In one example, the insulating layer comprises an insulating substrate on which the diodes are formed. For example, the substrate is sapphire and the diode is formed by a process of silicone on sapphire. In another example, the insulating layer is a silicone substrate surface of an integrated circuit having an upper oxide layer and the diode is a stacked diode disposed in the oxide layer. The stacked diode is preferably a Schottky diode operable with carrier signals of high frequencies in which the RFDD tag is operated.

The invention can be better visualized in view of the following Figures in which like elements are mentioned with similar numbers.

Brief Description of the Drawings Figure 1 is an idealized scheme of a memory cell in which an antifluid is used and programmed is an RFID tag.

Figure 2 is a timing diagram of the programming method of the invention used in the memory cell of Figure 1.

Figure 3 is a schematic of the energy of a self-calibrated circuit for an RFID tag.

Figure 4 is a flow diagram illustrating the operation of another exemplary embodiment of the invention wherein the auto circuit calibrates with a carrier signal.

Figure 5 is a block diagram of a circuit where the method of Figure 4 is used.

Figure 6 is a block diagram wherein a bit and frame synchronization of the invention is used.

Figure 7 is a wave diagram showing the transmission of data in an energy carrier signal.

Figure 8 is a wave diagram of an alternative exemplary showing the transmission of data signal and control in an energy carrier signal.

Figure 9 is a schematic of a full wave bridge rectifier.

Figure 10 is a cross-sectional view of a conventional integrated circuit in which the bridge circuit of Figure 9 is implemented.

Figure 11 is a cross-sectional view of an SOS diode in an integrated circuit for use in the bridge circuit of Figure 9 on an RFD tag.

Figure 12 is a cross-sectional view of a stacked diode in an integrated circuit or use in the bridge circuit of Figure 9 in an RFID tag.

The invention can be better understood by considering the following detailed description.

Detailed Description of the Preferred Specimens RFD3 Memory Low Power Antifusible Let us first consider a method to program or write in an RFID tag with a transient pulse in both high and low frequencies, that is, in the GHz and KHz ranges. As will be clear below, programming an RFID tag using transient pulses instead of a long-term regulated signal allows for less control circuits, less programming time, less power, lower cost and power requirements for the RFID tag.

In the prior art, programming the RFID tags was usually implemented by optically or electrically erasable programmable technologies that require a current voltage or pulse of a certain value for a specific period of time to apply to the RFDD tag. For example, an optically erasable apparatus must have a minimum of 10 volts applied to the apparatus while a current of the order of 0.5 milliamperes is supplied for at least 1 millisecond. In electrically erasable memories, the voltage requirement is usually a minimum of 15 volts for at least 1 millisecond, although the current requirements can be as low as 100 microamperes.

- The advantages of a invention are discovered using an electrically programmable element that requires very little energy to be programmed. Such an element is an antifusible like that described in U.S. Patent No. 4,442,507; 4,796,074; and 5,095,362 which are incorporated herein by reference. The voltage in the loose nodal discharge capacitance in the antifouling device is exploited to provide enough energy to program the structure of the antifouling.

Consider the idealized schematic diagram of Figure 1, which shows an antifusible memory element, generally annotated with the reference number 10. The element 10 is comprised of a current source 12 of some type operating with a voltage of Vcc. The current source 12 is then coupled through a line of bits 14 to an antifuse 16. A semiconductor transistor 18 is coupled to the antifuse 16 and can be selectively activated to read if the antifuse 16 is in high or low impedance state, thus representing a 1 or 0 bit. The nodal capacitance of the circuit 10 with the bit line 14 is represented in the diagram of FIG. 1 by an effective loose capacitance 20. In normal operation, the memory cell 10 is acceded to the turning on the control transistor 18 by increasing its input voltage and detecting whether current flows through the bit line 14. If the antifluid 16 has not been programmed and therefore has open circuits or is in high impedance, it will almost not flow current. If the antifuse 16 has been programmed or the circuit has been closed or is at low impedance, a predetermined amount of current will flow through the bit line 14.

To program the bit in the cell 10, the bit line 14 is raised to a high voltage ... on the critical voltage required to program the antifuse element 16. A finite amount of time is required to completely raise the bit line 14 due to the requirement to charge the loose capacitance 20. This charging time is a function of the amount of current that is supplied to the bit line 14 and the amount of loose capacitance 20 associated with the bit line 14. By allowing the bit line 14 to reach its level Stable DC of operation before turning on the control transistor 18, the control transistor 18 can set the upper limit of current through the antifuse 16, as opposed to being restricted or set by the capacity of the power source 12.

For example, let's assume in regard to illustration, that the antifluid 16 has a programming level of 4 volts. Assume further that the Vcc, the power source, is set to 6 volts. Assume that the maximum energy level through the control transmitter 18 is 1 milliamper, the loose capacitance 20 is 3 picofarads and the energy source 12 is capable of providing up to 10 microamperes. By the law of Ohm in form • differential when power source 12 is turned on, bit line 14 will require 1.8 microseconds to reach the 6 volt level under these pretensions. At any time after this time period of 1.8 microseconds, the control transmitter 18 can be turned on and antifuse 16 will try to withstand the 6 volts applied to it by the voltage supply. However, the voltage through antifusible 16, in fact, will only reach 4 volts before collapsing. The time required to program the antifusible 16 is, therefore, practically instantaneous or at least much less than 10 microseconds.

Under the pretensions of this example, a potential current level of 1.2 jimiamperes could be reached within the antifusible 16. However, it is assumed that the The 18 control transistor in the proposed example will limit the current to 1.0 milliamperes. Even more important are the average power requirements per time as best illustrated in the timing diagram of Figure 2. Lines 24 and 26 represent the current and voltage on the line of bits 14 characteristic of a classical load node. The voltage in the control transistor 18 is shown with the curve 28 and is activated in time 30. The voltage and current in the antifuse 16 is noted by lines 32 and 22. Note that the maximum current through the antifluid 16, as illustrated in line 22, it is quite high, but of very short duration. The average power or current supplied through the bit line 14 is, therefore, very small.

Normally, the electrical behavior as illustrated in Figure 2 would not be considered a benefit. However, in the situation of RFID tags, the amount of energy available for the integrated circuit within the RFID tag is very limited. Normally, the energy supplied to an RFDD tag is provided remotely by transmitting radio frequencies. The amount of energy required to read an RFID tag is usually 20 microwatts, usually operating at the 2 volt level and 10 microamperes. Based on the information described above in relation to the energy needed to program a bit, the power supply for an RFD3 tag should be increased to 60 microwatts, namely 6 volts to 10 microamperes. If the memory device were based on UV or electrically erasable memories, the energy levels would need to be increased from 5,000 to 1,500 microwatts respectively. Even these major numbers for other technologies are misleading since neither UV or electrically erasable devices can be programmed with transient pulses, but they require well-defined sustained voltage pulses.

Auto Synchronization Calibration for an RFID Tag According to the invention, a reference signal is initially generated in the receiver of the remote RFID tag by capturing a received standard signal and placing it in temporary or permanent storage in the circuit of the RFJD tag. The signals received later are then compared to the captured standard. Variations of the captured standard are then detected to allow the decoding of the data either by AM or FM techniques.

Figure 3 is a simplified block diagram illustrating a means of implementing the invention. An oscillator 34 on the chip of the RFD3 tag operates approximately on the carrier frequency of the input signal or some multiple thereof. As illustrated in Figure 3, an input signal is provided on line 36 and an appropriate characteristic thereof, such as frequency, phase change, time delay or the like is compared in a comparison circuit 38, which has its other input, the output of the oscillator 34. The difference in the characteristic parameter between the two is provided an output 40 of the comparator 38 and is appropriately converted to a digital format by an analog-digital converter. A correction command signal is finally supplied by a microprocessor 42 to a memory 44. Normally, due to the design of the oscillator 34 it can not be carried out accurately due to the large variation of components or processes of the integrated circuits or other environmental factors.

The correction signal corresponding to the difference signal is stored inside [& memory 44 and is then coupled through a decoder 46 to a plurality of switching devices 48 or a resistance ladder is coupled to a single capacitance (not shown), each of said switches 48 is coupled to an RC 50 circuit. or network capable of selectively providing circuit options to the oscillator 34 through which the frequency of the oscillator can vary can be equivalently replaced. Each circuit RC 50 corresponds to a different RC delay, which when coupled by means of one of the devices 48 to the oscillator 34, serves to adjust the output of the oscillator 34. The appropriate RC 50 delay circuit (s) is thus chosen by the microprocessor 42. until the output of the comparator 38 indicates that the appropriate difference signal between the on-line input signal 36 and the output of the oscillator 34 falls within an acceptable range. When this is achieved, the correction signal is stored within the memory 48 for use during all subsequent operations of the RFD3 tag or at least until it is updated. The memory 44 may be provided as a non-volatile memory to allow the calibration information to be stored permanently so that reconfiguration of the internal oscillator is not required each time the label is turned on.

The operation can be clarified considering an example. A resistor chosen initially of 100 kiloohms and a 50 picofarads capacitor results in a time constant of 5 microseconds for the oscillator 34. Due to variations in the process, the final resistance may instead be 130 kiloohms which results in a real-time constant of 6.5 microseconds, thus placing the oscillator out of frequency.

If an input signal has a periodicity of 4 microseconds, the time constant of the internal signal must be reduced to match the input signal one by one. Therefore, the resistor coupled to the internal oscillator 34 must be reduced to 80 kiloohms so that the RC time constant for the oscillator is equal to 4 microseconds. Conventional resistance ladder networks allow such a transition within the required accuracy.

An alternative methodology is summarized with the flow chart of Figure 4. The pulses of the internal watch clock of the RFD3 tag are counted in step 52 for a predetermined number of pulses of the external clock or at least for some arbitrary period of time . The pulse number of the internal clock is determined in step 56. This ratio becomes a calibration standard. From then on, deviations from this ratio can be recognized as meaningful data without making any effort to actually calibrate the RFID tag clock with the external communication standard, but simply to measure and store what is in effect a ratio of calibration.

For example, let's assume that data is transmitted through changing frequency keys between 915 Megahertz and 920 Megahertz. Let's assume that the clock on the chip of the RFED tag is not operating at the 915 Megahertz standard. The calibration ratio established by the methodology in the diagram of Figure 4 of the internal clock frequency against the clock frequency of the input signal is 0.9989 in this way. When an input signal of 920 Megahertz is received then, the ratio changes to 0.0035. Therefore, changes in high frequency in the proportion can be reliably identified as a state change data. Slower variations for the heading of the apparatus, time of the apparatus and environmental wear can be detected and used to readjust the calibration ratio appropriately.

Figure 5 illustrates a block diagram of a circuit that can be used to implement the methodology of Figure 4. The internal clock of the RFDD tag is provided to a first counter 58, while the external input signal or the signal of the The external clock is provided to a second counter 60. Both counters 58 and 60 count the signals of the clocks for a predetermined time after which the accumulated count is provided to a data and address transport 62 to which a microprocessor 64 and a microprocessor 64 are coupled. memory 66. The calculated and stored ratio is then used as a calibration device for the circuits of the RFED tag symbolically noted in Figure 5 with the reference number 68.

Synchronization of Bits and Frames The present invention overcomes the disadvantages of bit and frame synchronization described in the prior art section above and lends itself to being implemented in an integrated circuit in a manner that does not contain closed phase or even phase cycle. necessary way a microprocessor. In the invention, a unique bit pattern is provided which is a typical data pattern, instead of being a forbidden or even atypical data pattern. Bit and frame synchronization is achieved by the violation of an error management scheme such as a correction scheme and error c (ECC) that uses parity or polynominal bits to achieve frame synchrony. At the same time, the use of a typical data pattern provides certainty that the actual data will be / recognized correctly.

An example will make the above clearer. In an even parity scheme, the unique pattern is an irregular pattern of 1 's and 0's with an even parity bit that identifies it as the frame creator followed by the even-parity data. Bit synchronization can thus be achieved anywhere in the bit stream. The unique pattern-making pattern is efficiently matched to a stored pattern and validated by parity with the keyword and even with the following data words.

In other words, the transmitted digital information has within it a combination of bits comprising a single bit pattern. The unique bit pattern can be a data pattern in which a particular error management scheme for the parity bits is chosen contrary to the assumed error convention. Whenever this unique pattern with an error in parity is received, it is recognized as a synchronization box for all subsequent data and is not treated as an error. The chance that the unique pattern in which a parity error will occur is so small that incorrect identification in the single synchronization box is extremely unlikely.

An example will make this approach clearer. Assume that 32 word bits are being generated in which the last bit is a parity bit. Assume further that the detection of the error and the correction scheme assumes even parity, which is the number of 1 bits in the 32 word bits are always transmitted so that an even number of bits are included in the word, the parity bit is 1 or 0 as appropriate to achieve the above. ,. we now add that 31 of the bits are data bits and that a unique pattern of these 31 bits is chosen as the pattern of frame synchronization. Let's assume that this pattern has an even number of l's in. { he. The parity bit would be 0, if the error correction scheme was not violated. In this case, the parity error is intentionally violated and the parity bit is set to 1. The communication system on the RFD3 tag will then recognize the word because it has a parity error, but also because it has the unique data pattern of synchronization of pictures. Therefore, the parity error would be ignored. The time re reception of this word is then taken as a synchronization or checker creator.

For an 8-bit word the probability that a data pattern assumes the data bit pattern and has a parity error is 1 to 28, or 256 to 1 if it is assumed that a worse case of 50 odds exists. % of a data error In fact the rate of data error in most systems is much lower, typically 1 every 232 after multiple repeated transmissions in most applications of RFID tags. For an 8-bit word, this probability may not be high enough for reliable synchrony. However, in a 32-bit word, the probability of this parity error and the bit pattern occurring becomes 232 in the worst case or becomes more than 4 billion to 1 against it. The communication error rates at this level are more than acceptable and are exceeded by other factors that normally arise in an RFD3 tag application.

The scheme can be easily implemented in an RFD3 tag apparatus simply by using a special decoder in combination with a conventional parity checker to detect the unique data frame synchronization to disconnect the output of the parity verifier for that word and to provide a internal synchronization control signal for use within the RFID tag circuit in response. Figure 6 is a simplified block diagram of a circuit in which the synchronization protocol can be implemented. The input data stream is coupled on line 70 to a conventional parity checker 72 and to a decoder 74 which checks the data stream for the unique bit pattern together with the parity violation. When this occurs, the decoder 74 disconnects the output of the parity checker 72 via a gate 78 so that no parity error signal is transmitted to the RFTD tag circuits (not shown) and generates a synchronization pulse on its output. 76 Simultaneous Energy and Data Transmission When operating at high frequencies the carrier frequency can be reduced in amplitude or turned off completely for short periods of time as illustrated in the diagram in Figure 7 without causing the RFID tag to lose power. Since the reduction in the strength of the carrier signal is for such a short period of time, the DC energy in the integrated circuit inside the label after rectification does not suffer a significant reduction.

An example will make the above clearer. Consider a sample calculation in which the longest pulse duration that the carrier would shut off is 0.5 microseconds. Assume that the DC current requirement is 20 microamperes and the capacitance of the voltage supply line, Vdd, on the RFD3 label is 200 picofarads. During this period of time, it can be shown that the increase in voltage on the Vdd line is approximately 0.05 volts. A drop of 50 millivolts in the power supply is usually not as drastic as to make the chip inoperable.

The periodicity of the modulation allows the simple use of clocks. In addition, the variation of the duration of the signal can be used to transmit data like l's and 0's. The Figure 7 is a wave diagram of a carrier envelope, showing typical data that can be transmitted at a baud kilohertz rate. The circuits within the RFID tag need only be able to distinguish between a pulse of 0.1 to 0.5 microseconds in order to reliably identify whether a 1 or a 0 is being transmitted. For example, the pulse of 0.1 microseconds 80 can be used to represent 0's, while the 0.5 microsecond pulse is used to represent binary l's. The reduction of errors can be achieved through repetition of pulses or redundancy.

The RFD3 tag remains fully energized because despite the fact that the carrier envelope is essentially turned off by data transmissions, the pulse amplitude is not so great as to cause the chip to reduce the energy in the baud rhythms in which the RFD3 tag operates normally. For example, as illustrated in Figure 7, at a baud rate of 33 kilohertz, one pulse is transmitted every 7.5 microseconds. This leaves approximately a charge cycle of 98 percent that allows the energy circuits within the RFID tag to recover the small voltage loss during the longest pulse duration it sees.

An alternative scheme is illustrated in Figure 8. Here, three durations of different uses are used to represent a creator, a binary 0 and a binary 1. Again, the pulse Je o. The microsecond 80 represents a binary 0, the pulse of 0.5 microseconds 82 a binary 1 and the pulse of 0.3 microseconds 82 a synchronization, control signal or other identifier creator. All that is required is that the circuits of the RFID tag be able to detect pulse amplitudes with a difference of 0.2 microseconds.

A consequence of this technique is that the chip time in the RFID tag can be determined from the modulation of the carrier at a much lower rate than the carrier itself. This, in turn, saves significant energy consumption on the label RFID because circuits that operate at high speeds consume substantially more energy than those that operate at low speeds.

An RFDD Tag Diode for Use in Energy Rectification A diode rectifier is formed according to the invention by isolating the diodes from the integrated circuit substrate to ensure that a charge to the diode or other circuits is not applied without warning. A means to implement this is to manufacture diodes in an integrated circuit process with an insulation between elements such as silicone or sapphire (SOS) as illustrated in the cross-sectional view of Figure li or more generally by making silicone on the insulator . In any case, the active apparatus like the diode 104 is completely covered with an insulator, namely the substrate insulator 106 and the passive isolator 108. The metal contacts 110 and 112 are provided to the region N 114 and the region P 116, respectively.

Another means to achieve the same result is to make the diode inside the bridge , rectifier on the surface of the integrated circuit as illustrated in Figure 12. The fabrication of integrated circuit surfaces is illustrated in Roesner, "Memory for Read Only Stacked on a Substrate Semiconductor ", US Patent 4,424,579 (1984), in which the stacked diode is used as a memory cell In Figure 2 the silicon substrate of the integrated circuit is provided under a region N + encapsulated in oxide 120. An oxide layer 122 rests between the region 120 and the region of the substrate 118. A silicone layer of the type N 124 is then fixed within the N + 120 region and is properly exposed to a metal contact 26 for forming a Schottky diode layer at the interface 128 between them.The strongly altered contact region 120 opens similarly and is provided with an electrical contact 130. The Schottky diode of Figure 12 could be equivalently replaced with a link diode P- N if desired The Schottky diode is preferred because it is a major carrier device and does not require a single crystal silicone of such high quality as that required by a J-N link In addition, the Schottky diode is much faster and can easily respond to the high frequency carrier signal which is atypical for the diode bridge in the conventional integrated circuit presented above in relation to Figures 9 and 10.

Many alterations and modifications can be made by those of ordinary skill in the art without departing from the spirit and scope of the invention. Therefore, it should be understood that the exemplary illustrated has been established for the purpose of exemplifying and should not be taken as limiting the invention which is defined by the following claims.

The words used in this description to describe the invention and its various examples should be understood not only in the sense of their commonly defined meanings, but should include special definitions in this descriptive structure, materials or facts beyond the scope of commonly defined meanings. . Thus, if an element can be understood in the context of this description including more than one meaning, then its use in a claim should be understood as generic for all possible meanings supported by the description and the word itself. The definitions of the words or elements of the following claims are, therefore, defined in this description to include not only the combination of elements that are literally established, but any equivalent structure, material or facts to carry out substantially the same function in substantially the same way to obtain substantially the same result. In addition to the equivalents of the claimed elements, obvious substitutions now or later known to those skilled in the art are defined within the scope of the defined elements. It should be understood then that the claims include what is specifically illustrated and described above, what is conceptually equivalent, what can obviously be substituted, and also what is essentially incorporated into the main idea of the invention.

Claims (38)

1. The claims are: 1. A method for programming a radiofrequency identification apparatus comprising: providing an antifluid in a memory cell coupled to a line of bits in said radio frequency identification apparatus; load a loose capacitance on said bit line; and selectively discharging said antifluid to attract a high maximum current through said antifluid from said loose loaded capacitance to program said antifluid, so that said antifluid is programmed at high speed and low energy.
2. 2. The method of claim 1 wherein charging said loose capacitance comprises charging said capacitance to a voltage that exceeds the programming voltage of the antifluid.
3. 3. The method of claim 1 wherein charging said loose capacitance in said bit line loads said capacitance with approximately 60 microwatts of energy or less.
4. 4. The method of claim 1 wherein charging said loose capacitance on said bit line loads said capacitance with approximately less than 100 microwatts of energy.
5. 5. The method of claim 1 wherein selectively discharging said? Ntifiable coupling said antif? Via through a transistor to ground, said step transistor has a maximum saturation current capacity, said antif? Has a programming time defined by a duration of predetermined time, said loose capacitance in said bit line is charged at an energy level such that said saturation current is obtained by said antifluid and transistor during said programming time of said antifluid.
6. 6. A method for programming an antifluid having a minimum programming time at high speed and low energy comprising: charging a bit line coupled to said antifluid at a predetermined voltage and thus at predetermined stored energy level, said bit line has a Chargeable capacitance; and downloading said bit line through said antiflugable at high speed substantially equal to said minimum programming time required by said antifluid to generate a voltage and current level through said antiflugable sufficient to program said antifluid while using an average low. of energy.
7. 7. A method for auto calibrating remote RFID tag circuits comprising: receiving an external signal having a characteristic parameter; receive an internal signal having said characteristic parameter; compare said characteristic parameters of said external and internal signals; generating an error signal indicative of the difference in said characteristic parameters in said compared external and internal signals; and generating a correction signal that when applied to said remote circuit compensates said internal signal to allow calibration with said external signal.
8. 8. The method of claim 7 wherein generating said correction signal comprises generating an oscillator correction signal to adjust said internal signal within a predetermined tolerance with the external signal.
9. 9. The method of claim 7 wherein generating said compensation signal comprises generating a correction factor for use in operation of said remote RFTD tag circuit wherein said error in said characteristic parameters between said external and internal signals remains substantially constant during times of interest. operation of said remote RFID tag circuit.
10. The method of claim 7 wherein said operational characteristics said RFDD tag circuit changes in periods of time greater than those time periods of operational interest of said remote RFID tag circuit and further comprises repeating the method comprising of receiving said external and internal signals, comparing said characteristic parameters, generating an error signal and generating a correction signal to update said compensation signal as said error signal changes with the passage of time.
11. 11. The method of claim 8 wherein the operational characteristics of said remote circuit changes for periods of time greater than those periods of time of operational interest of said circuit of the remote RFID tag and further comprises repeating the method comprising receiving said external signals. and internal, comparing said characteristic parameters, generating an enormous signal and generating a connection signal to update said compensation signal as said enormous signal slowly changes with the passage of time.
12. 12. The method of claim 9 wherein the operational characteristics of said remote circuit change with the passage of periods of time greater than those periods of time of operational interest of said remote circuit and further comprises repeating the method comprising receiving said external and internal signals. , comparing said characteristic parameters, generating an enormous signal and generating a connection signal to update said compensation signal as said enormous signal slowly changes over time.
13. 13. The method of claim 8 wherein generating said connection signal comprises generating a signal for choosing a compensation time constant RC to couple to said oscillator.
14. 14. An apparatus for auto calibrating a remote RFD3 tag circuit comprising: A comparator coupled to an external signal and an internal signal that will be calibrated with respect to said external signal, said comparator generates a signal of huge indicative of the difference in a characteristic parameter of said external and internal signals; a processor circuit coupled to said comparator responsive to said huge signal to generate a compensation signal that when applied to said remote circuit allows the calibration of said internal signal of said remote circuit to be calibrated with said external signal received by said remote circuit, for which said remote RFID tag circuit is provided with reliable and economical calibration for communication.
15. 15. The apparatus of claim 14 further comprising a memory coupled to said processor circuit for storing said compensation signal to maintain calibration of said remote RFID tag circuit.
16. 16. The apparatus of claim 15 further comprising an oscillator in - said remote circuit for generating said internal signal and an RC network having a plurality of eligible RC values, said compensation signal of said processor circuit chooses one of said RC values for coupling said oscillator to maintain a characteristic parameter of said internal signal calibrated within a predetermined tolerance with said external signal.
17. 17. The apparatus of claim 15 wherein said compensation signal generated by said processor circuit is a connection factor indicative of said jumble between said external and internal signals, said connection factor being applied to said processor circuit for operations within said circuit of Remote RFID tag for niantener a reliable calibration with said external signal.
18. 18. The apparatus of claim 17 wherein said connection signal is proportional to the relationship between said characteristic parameter for said external signal and said internal signal.
19. 19. A method for providing synchronization in data communication comprising: verifying a communication data stream having an encore connection protocol for a single data bit pattern; determine if said unique data pattern also violates said enores verification protocol; and using the synchronization of said unique data pattern as a synchronization signal if said enores verification protocol is violated; by means of which a bit and frame synchronization is achieved anywhere within said data bit stream.
20. 20. The method of claim 19 wherein verifying said data bitstream for said unique pattern comprises verifying a typical single pattern of normally received data.
21. 21. The method of claim 19 wherein determining whether a / violation of the connection of enores determines if a violation of the parity penalty has occurred.
22. 22. The method of claim 20 wherein determining whether a violation to the connection of enores has occurred determines whether a violation of the parity error has occurred.
23. 23. The method of claim 19 wherein said data stream is organized into words and said unique data pattern comprises at least one word subject to said encore connection protocol, wherein said word has a bit length at least equal to said predetermined minimum so that the probability of creating in a normal data stream said unique pattern with violation to the connection of enores is less than a predetermined acceptable minimum.
24. 24. An apparatus for providing a synchronization creator comprising, an ion connection circuit for receiving a stream of data signals; and a decoder for verifying said stream of data signals by a unique pattern and violation of huge in the simultaneous parity, said decoder is coupled to said connection circuit of enores and disconnects said connection output of enores in the case of simultaneous detection of said unique data pattern and the enores connection violation to generate a synchronization signal.
25. 25. The apparatus of claim 24 wherein said encore connection circuit is a parity checker.
26. 26. The apparatus of claim 25 wherein said decoder verifies data stream of data bits by said unique pattern comprising a typical single pattern of normally received data.
27. 27. The apparatus of claim 25 wherein said data stream is organized into words and said unique data pattern comprises at least one word subject to said encore connection protocol wherein said word verified by another decoder has a bit length at least equal to a predetermined minimum so that the probability that said unique pattern will arise in a normal data stream with violation of the connection of enores is less than a predetermined acceptable minimum.
28. 28. A method for simultaneously providing power and communication data to a remote and wireless RFDD tag circuit comprising: transmitting a carrier signal to said circuit to provide power to said circuit; modulating said carrier signal to reduced levels using pulse amplitudes equal to or less than a predetermined maximum, said predetermined maximum is determined by the longest duration at which said carrier signal can be turned off before said remote RFID tag circuit loses stored energy to a sufficient degree that makes the operation of said unreliable remote RFID tag circuit.
29. 29. The method of claim 28 wherein said carrier signal is modulated by pulses having at least two distinguishable pulse amplitudes, said pulse amplitudes being connected to the information transmitted to said remote RFID tag circuit.
30. 30. The method of claim 29 wherein said carrier signal is modulated by at least three pulse amplitudes to communicate binary data and control signals.
31. 31. The method of claim 28 wherein said modulation is at a frequency substantially less than said carrier signal such that said remote circuit is operated at said reduced frequency with less energy.
32. 32. The method of claim 31 wherein said carrier signal is modulated by pulses having at least two distinguishable pulse amplitudes, said pulse amplitudes being connected to the information transmitted to said remote RFTD tag circuit.
33. 33. The method of claim 28 wherein said carrier signal is modulated with a cycle of performance at or less than a predetermined maximum as determined by the minimum performance cycle in which said RFID tag circuit will still operate reliably.
34. 34. An improvement in a diode rectifier having a plurality of diodes in an RFTD tag comprising: insulating material disposed below and between each of said diodes in said rectifier to prevent a forward inclination of any of said urods links in high frequencies.
35. 35. The improvement of claim 34 wherein said insulating layer comprises an insulating substrate on which the diode is formed.
36. 36. The improvement of claim 35 wherein said substrate is sapphire and said diode is formed by a sapphire silicone process.
37. 37. The improvement of claim 34 wherein said insulating layer is a silicone substrate surface of an integrated circuit having an overlying oxide layer and said diode is a stacked diode disposed on said oxide layer.
38. 38. The improvement of claim 37 wherein said stacked diodes are diodes Schottky operable with carrier signals at high frequencies in which the label / * RFID is operable. IMPROVEMENTS IN AN APPARATUS AND METHOD OF USING LABELS FOR IDENTIFYING RADIO FREQUENCIES Abstract of the Invention Antifluous Low Energy RFID Memory A method for programming or writing on an RFD3 tag with a transient pulse on both cans and low frequencies, that is, on the GHz and KHz ranges as described. Programming an RFID tag using transient pulses instead of long-term regulated signals allows fewer control circuits, less programming time, less power, less cost and energy requirements for the RFID tag. Auto Synchronization Calibration for an RFD3 Tag. A reference signal is initially generated in the receiver of the RFID tag by capturing a standard input signal and placing it in temporary or permanent storage in the circuit of the RFID tag. The signals received later in time are then compared with the captured standard. Then variations of the captured standard are detected to allow the decoding of the data either by AM or FM techniques. Synchronization of Bits and Tables A unique bit pattern that is a normal data pattern, rather than a forbidden or even atypical data pattern. The synchronization of bits and frames is achieved by the violation of a scheme of administration of enores as it is a scheme c and connection of enores (ECC) that uses bits of parity or polynomials to achieve the synchronization of tables. At the same time, the use of a typical data pattern provides the certainty that the real data will be recognized correctly. Simultaneous Energy and Data Transmission When operating at high frequencies, the carrier frequency can be reduced in amplitude or turned off completely for short periods of time without causing the RFID tag to lose power. Since the reduction in the strength of the carrier signal is for such a short period of time, the DC energy in the integrated circuit inside the label after rectification does not suffer a significant reduction. An RFD3 Label Diode for Use in Energy Rectification A diode rectifier is formed by isolating the diodes from the integrated circuit substrate to ensure that a load is not applied without warning to the diode or other circuits. One way to implement this is to manufacture the diodes in a process of integrated circuit with an insulator between the elements such as sapphire or silicone (SOS) or more generally by making silicone on insulation or making diodes on the passive surface of the integrated circuit. High-speed rectification on the carrier frequencies of the RFID tag is achieved using Schottky diodes.