MXPA96001661A

MXPA96001661A - Intelligent circuit switch of fault detie

Info

Publication number: MXPA96001661A
Application number: MXPA/A/1996/001661A
Authority: MX
Inventors: Gershen Bernard; Neiger Benjamin; Rosenbaum Saul
Original assignee: Leviton Manufacturing Co Inc
Priority date: 1995-05-04
Filing date: 1996-05-03
Publication date: 1999-10-14

Abstract

The present invention relates to an intelligent circuit breaker system electrically connected to load at the time of detection of an interruption condition, comprising: circuit breaker means including phase and neutral ports of line side and load, in where the phase and neutral ports are electrically connected, respectively, to the phase and neutral terminals of the alternating current source and the circuit breaker means generate an interruption signal to interrupt the flow of alternating current to the detection of the condition of interruption, a relay switch includes a relay coil and phase and neutral contacts, wherein the line and load ends of the phase contact are electrically connected, respectively, between the load side phase port of the means of switch and a phase terminal of the load, the line and load ends of the neutral contact are electrically connected respectively, between the neutral load-side port of the switch means and a neutral terminal of the load and the relay coil is electrically coupled between the load ends of the phase and neutral contacts to control the contacts in response to the switch signal - an incorrect open contact electrical detector (DEICA) electrically connected to the line and load ends of one of the phase and neutral contacts to detect an incorrect power line condition when the contacts are in the open state an incorrect closed contact electrical detector (DEICC) electrically connected to the load end of the phase contact and to the line and load ends of one of the neutral and phase contacts to detect an incorrect power line condition when the contacts are in a closed state, a timing signal generator electrically connected to the improper open and closed electrical line sensors for generating system timing signals, a test circuit electrically coupled to the switching means and responding to the timing signal generator to regularly test the operability of the switching means, an alarm circuit that electrically responds to each of: the test circuit, the timing signal generator, the incorrect open contact power detector and the incorrect closed contact electrical detector to communicate at least one of: a laying condition incorrect open contact electrical, a closed contact malfunctioning electrical condition, an operational failure condition, and a need for external test condition, and an electrically connected power supply between the load ends of the phase and neutral contacts and the timing signal generator

Description

INTELLIGENT SWITCH OF GROUND FAULT CIRCUIT BACKGROUND OF THE INVENTION The present invention relates to ground fault circuit interrupters (GFCIs) and, more particularly, to a built-in test circuit system (BIT), which increases the operational reliability of ground fault circuit interrupter devices . Ground fault circuit interrupters were developed to meet a great need for a device that was capable of detecting the presence of abnormal current flow, for example, a current flow from a phase line to ground, and interrupt immediately the energy to a failed line, in which the abnormal current was detected, to protect people from an electric shock, fire and explosion. To fully protect human life, electrical circuit breakers must detect such fault currents in the order of 3 to 50 mA, corresponding to load currents that vary in the order of 10 to 100 A. Before the development of the circuit breakers of land failure, in certain European countries differential breakers were known and used, to provide ground fault protection. Differential circuit breakers include a differential transformer with a core through which two conductors of the electrical circuit being inspected pass. The two wires act essentially as primary windings. The differential transformer also includes current-interrupting contacts, which, in the case of a short circuit in the line to ground, or an abnormal current leak to ground, are forced to a high impedance state, ie, an open state . The state of the contacts is controlled by a semiconductor device, which is energized by a secondary of the differential transformer. It was found that such devices were, however, unacceptable, due to their insensitivity to detect current and, therefore, their ineffectiveness to ensure complete protection of human life. The ground fault circuit interrupters evolved from the differential circuit breaker technology. Ground fault circuit interrupters were developed as ground detectors, including a circuit breaker connected between a power source and a load; The power source is connected to the load through the ground fault circuit interrupter, by means of a neutral conductor and a phase conductor. The ground fault circuit interrupter also includes a differential transformer connected through the neutral and phase conductors. The circuit breaker is activated when the differential transformer detects that more current is flowing into the load, from the source, through the phase conductor, than the one that is flowing back to the source, through the neutral conductor. Primary and secondary windings are included inside the differential transformer, which provides a means to detect the current. A tertiary winding is placed close to the neutral conductor, in the vicinity of the load, by means of which a current is induced in it, in the case of a ground connection. If the induced current is large enough, the breaker contacts are forced open. Similarly, a ground fault protection system is known, which includes a differential transformer formed by a toroidal core, through which each of two line conductors and a neutral conductor pass, to form primary windings of at least one round. A secondary winding of the differential transformer serves as an output winding, and is connected to a ground fault circuit interrupter circuit. A discharge coil of a circuit breaker, having a plurality of contacts in line with the conductors of a distribution circuit, it is energized with a minimum current. A pulse generator is housed in the neutral conductor to produce a high frequency current in it, over the ground connection of the neutral conductor, between the differential transformer and the load. The high frequency current is produced by the periodic discharge of a diac, when a voltage is applied to the output winding in a capacitor connected to it. The pulses induce voltage pulses in the neutral conductor, passing through the transformer core. Induced voltage pulses do not affect the current balance in the distribution system, as long as the neutral conductor is not grounded in the load side of the transformer. If a ground connection occurs, however, the voltage pulses produce a current in the neutral conductor, which does not appear in any of the line conductors. The ground fault detection elements detect a consequent imbalance, and cause the contacts to open, interrupting the current flow in the distribution system. Another known arrangement describes an electrical circuit breaker that includes highly sensitive elements that respond to ground fault. The elements include a differential transformer with a toroidal core made of a magnetic material. The phase and neutral conductors pass through an opening in the toroidal core, forming primary windings of a single turn. The differential transformer also includes a secondary winding that includes a plurality of turns wound in the toroidal core. This secondary winding is connected to a solenoid assembly that includes an armature, an operating coil and a frame, mounted in a box. The armature is adapted to move between an extended position and a retracted position, in response to the energization of the operating coil. Attached to the armature is a trigger hook, which is arranged to engage with the armature member of the activating assembly. In this way, the energization of the operating coil causes the trigger hook to pull the armature away from a trigger member to initiate the discharging of the circuit breaker. Consequently, the solenoid assembly opens the contacts of the circuit breaker, in response to the failed ground current in the order of 3 to 5 Ma, and therefore, is desirable from the point of view of protecting human life against a electric shock. Another known ground fault circuit interrupter includes a differential transformer connected to an alternating current source, which produces a voltage output when an imbalance occurs in the current flow between the power lines. The voltage output is coupled to a differential amplifier by a coupling, rectified, limited current capacitor, and applied to a gate of an SCR. When the SCR is driven, the winding of a transformer connected through the power line is energized, causing two breaker switches to open. A circuit is also provided to close the switch when the line becomes unbalanced. Another protection arrangement uses a ground leakage protector, which includes a ground fault release coil, controlled by a ground fault detector. The ground fault release coil is energized normally, and de-energized when a ground fault appears. Upon detection of a ground fault, a restriction trigger is disabled, resulting in the opening of the circuit breaker. Still another protection arrangement uses a unitary automatic switch of the molded box type, which includes inside its box elements sensitive to ground faults, elements sensitive to overcurrents, and elements sensitive to short circuit currents, all the elements mentioned above act in a common trigger trigger of the circuit breaker, to cause an automatic opening when an overcurrent is detected. Also included is a current unbalance detection sheet, which energizes a discharge solenoid, to release a normally secured magnet plug, to cause a discharge. Similarly, a ground fault protection system is known, which employs a dormant oscillator, which is triggered in oscillation to initiate the disconnection of the protected distribution circuit, on the occurrence and detection of a type of neutral fault. to Earth. Although numerous techniques are available to protect against ground faults, a key concern in the application of ground fault circuit interrupters in residential and commercial environments is the reliability of the ground fault circuit interrupter. As long as the ground fault circuit interrupter is operating properly, ground fault protection is provided, avoiding electrical shock. When dealing with reliability problems, it should be considered that most ground fault circuit interrupters are connected to the existing electrical wiring in the installation and then forgotten, assuming the owner of the house or the contractor, that it will operate correctly for one, five or ten years after it was installed. Unfortunately, this is not necessarily so. Ground fault circuit interrupter devices are subject to many failure modes. For example, ground fault circuit interrupters are susceptible to a bad power supply, to an open coil of current sensing coils, to integrated circuit failures, to a short or open SCR device, to an open coil of the switch automatic, failed contacts, etc. Therefore, there is a need for a ground fault circuit interrupter capable of communicating to a user whether the device is functioning properly or not, at any time after its installation. One solution is to incorporate a test button on the front of the ground fault circuit interrupter device, which when simulated presses a ground fault. The internal circuitry treats this simulated ground fault as if a real fault had occurred. Through this, all the internal components and the circuit system are exercised and tested. If the internal mechanism of the ground fault circuit interrupter is working properly, the contacts are opened and power is removed from the protected electrical circuit. After a test, the ground fault circuit interrupter must be reset to its normal operating condition. This can be done by pressing a reset button on the front of the ground fault circuit interrupter device. Users would be instructed to periodically test their ground fault circuit interrupters and replace faulty devices. The problem with this scheme is that in reality most users do not test their ground fault circuit interrupters on a regular basis, if they do, even though the front of the ground fault circuit interrupter is labeled with the words 'TRY MONTHLY' on its surface. In this way, there is a real need for a ground fault circuit interrupter device that incorporates the ability to automatically test itself periodically, without any user intervention, in addition to reminding the user to periodically test the circuit breaker of ground fault manually. A factor that decreases the reliability of the ground fault circuit interrupter, in addition to the user not testing the ground fault circuit interrupter, is a power interruption and the corresponding over voltage when the power is restored. Thus, it would be beneficial if the ground fault circuit interrupter detected the energy that is being restored after a sufficiently long power interruption, and forcing the user to subsequently test the device. The restoration of the energy can cause large voltage and current peaks to appear in the power line, thus creating a component fault. Another potential problem arises because ground fault circuit interrupters were typically installed before electricity was applied, especially in a new construction. Consequently, there is a real possibility that an installer could inadvertently connect the line side of the AC power line to the load side of the ground fault circuit interrupter. While downstream electrical devices are protected, any receptacles built within the ground fault circuit interrupter device itself would not be protected, creating a potential hazard. Then the ground fault circuit interrupter would remain incorrectly connected, unless the device was able to detect an incorrect power line condition. The ability to detect if the line and load sides are connected in reverse increases the security level of the device. At the time the power is initially applied, the electrical fault circuit interrupter would warn the user, by means of a visual and / or audible alarm, in the event that an incorrect power line condition is detected. The visual and / or audible alarm could not be eliminated until the incorrect electrical wiring condition was removed, decreasing the probability of incorrect electrical wiring.

OBJECTIVES AND SUMMARY OF THE INVENTION It is therefore an objective of the present invention to provide a ground fault circuit intelligent switch device (IGFCI), which can automatically test its internal circuit system in a periodic manner, increasing, by same, its own probability of proper operation in the case of a real earth fault. Such a ground fault circuit interrupter can test itself monthly, weekly, daily or even hourly. In particular, all the key components can be tested, except relay contacts. This is because the interruption of the contacts for their test, could have the undesirable result of removing the power to the user circuit. However, once a month, for example, the ground fault circuit interrupter device may generate a visual and / or audible signal or alarm, reminding the user to manually test the ground fault circuit interrupter. The user could, in response to the signal, initiate a test by pressing a test button, thereby testing the operation of the contacts, in addition to the rest of the circuit system of the ground fault circuit interrupter. After a successful test, the user would readjust the ground fault circuit interrupter device, by pressing a reset button. Another object of the present invention is to provide an intelligent ground fault circuit interrupter system (IGFCI), which has an increased operating reliability over conventional ground fault circuit interrupters. The intelligent ground fault circuit interrupter incorporates a built-in test circuitry and partial redundancy, in an effort to provide this increased reliability. The built-in test circuit system automatically tests the internal components of the ground fault circuit interrupter, except relay contacts, periodically, such as once every hour. If a fault is detected, a visual and / or audible alarm is generated. As a result, the relays open immediately using built-in redundant relay discharge elements. Another object of the present invention is to provide an intelligent ground fault circuit interrupter with the ability to detect when the ground fault circuit interrupter is incorrectly connected in a power line system, for example, when the connections have been reversed of load and line. Upon detection of an incorrect power line condition, an alarm and / or audible is generated to warn the user that the device is in an incorrect power line state, and the relay contacts are opened by removing the AC power of the devices Electrical downstream. The ground fault circuit interrupter can not be readjusted unless the incorrect power line condition is eliminated. Another object of the present invention is to provide an intelligent earth fault circuit breaker with the ability to inspect the earth leakage current that rises constantly or slowly in the AC power line, and adjust the threshold accordingly. Discharge of the internal circuit of the ground fault circuit interrupter, up or down, avoiding the annoying interruption of the ground fault circuit interrupter. The discharge threshold of the ground fault circuit interrupter would track the slowly rising and falling earth leakage currents, caused by certain artifacts. However, 5 mA of leakage current that rises rapidly, would immediately cause the ground fault circuit interrupter circuit to discharge the relay and open the contacts. Still another object of the present invention is to provide a warning signal for the periodic test to warn a user to manually test the ground fault circuit intelligent switch device. A visual and / or audible warning signal would be generated 30 days after the energy was initially applied, and 30 days after the last manual test was performed. Preferably a daylight detector would be included to silence the warning signal during the evening and night hours, while most people are asleep. The present invention provides an intelligent circuit breaker system for the electrical connection between an alternating current source and a load to interrupt an alternating current flow between the source and the load, upon detection of an interruption condition. The system includes a circuit breaker electrically connected to neutral phase terminals of the alternating current source, to cut the alternating current at the source when an interruption condition is detected. The circuit breaker acts in conjunction with a relay switch, which includes a relay coil and phase and neutral contacts. The phase and load ends of the phase contact are electrically connected, respectively, to a load side phase port of the breaker element, and a load phase terminal. The phase and load ends of the neutral contact are electrically connected, respectively, to a load-side neutral port of the switch element, and a neutral load terminal. The relay coil controls the state of the contacts (ie, the high or low impedance state) in response to a breaker signal generated in the switch.

The system includes an incorrect open contact electrical conductor detector (OCMD), electrically connected to one of the phase and neutral contacts, to detect an incorrect power line condition, when the contacts are in an open state, and a detector Closed-contact incorrect electrical power line (CCMD), electrically connected to the incorrect open-contact power detector, and to one of the neutral and phase contacts, to detect an incorrect power line condition when the contacts are in a closed state. The system also includes a timed signal generator to generate timed system signals, a test circuit electrically coupled to the switch element and the timed signal generator to test the operability of the switch element and generate a signal therefrom, an alarm circuit which responds electrically to the test circuit, the timed signal generator, the incorrect open contact electrical detector and the incorrect closed contact electrical detector to communicate an incorrect electrical contact condition for open contact, a power line condition incorrect contact closure, an operational fault condition, and a need for an external test condition, and an electrically connected power supply between the load ends of the phase and neutral contacts, and the timed signal generator. Preferably, the various objects and features of the present invention will be apparent from the following description, in which the preferred embodiments are declared in detail, in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a functional block diagram of a preferred embodiment of the present invention. Figure 2 is a detailed schematic diagram of a power supply circuit, which can be used within the embodiment of Figure 1. Figure 3 is a detailed schematic diagram of an audible alarm circuit, which can be used within of the embodiment of Figure 1. Figure 4 is a detailed schematic diagram of a timed signal generator, which can be used within the embodiment of Figure 1. Figure 5 is a detailed schematic diagram of a laying detector incorrect electric contact, which can be used within the modality of Figure 1.

Figure 6 is a detailed schematic diagram of an incorrect closed contact electrical switch detector, which can be used within the embodiment of Figure 1. Figure 7 is a detailed schematic diagram of the ground fault circuit interrupter, which can be used within the embodiment of Figure 1. Figure 8 is a detailed schematic diagram of an automatic gain control circuit, which can be used within the embodiment of Figure 1. Figure 9A is a detailed schematic diagram of a portion of a self-test circuitry, which may be used within the embodiment of Figure 1. Figure 9B is a detailed schematic diagram of a portion of the self-test circuitry, which may be use within the modality of Figure 1.

DETAILED DESCRIPTION OF THE INVENTION In accordance with Figure 1, a preferred embodiment of an Intelligent Earth Fault Circuit Interrupter System (IGFCI) 10 will now be described (hereafter we will not refer to it interchangeably as "intelligent ground fault circuit interrupter"). "," system "and" device ") of the present invention. The intelligent ground fault circuit interrupter 10 shown in Figure 1 preferably includes a standard Ground Fault Circuit Interrupter (GFCI) 12 as its "core" structure, easily known to those skilled in the art., a self-test circuit 14, incorrect open contact and closed contact electrical contact detectors 20, 24, an alarm circuit 18 and an automatic gain control circuit 16. Properly installed, the system 10 protects all current electrical devices down connected to it, as well as the receptacles present in the device itself. It should be noted, however, that the description of the preferred embodiment is presented merely for purposes of illustration and is not intended to limit the scope or spirit of the present invention. Figure 1 shows the intelligent ground fault circuit interrupter 10 as a four-terminal device, which includes power input terminals AC-1 and AC-2, hereinafter referred to as phase and neutral line terminals , and output terminals of the LOAD-1 and L0AD-2 systems, hereinafter referred to as phase and neutral load terminals. An AC power source (not shown in the figure) can be connected to the device 10 to provide AC power to it via the phase line and neutral terminals AC-1 and AC-2. A metal oxide varistor (MOV) 270 is electrically connected between the phase and neutral line terminals to suppress voltage peaks. The ground fault circuit interrupter 12 is placed in a current path to alternate the current flow from the alternating current source to the load. The ground fault circuit interrupter includes line-side phase and neutral ports (AC-1__IN, AC-2__IN) and load-side ports (AC-1_0UT, AC-2_OUT), where AC-1_IN and AC- 2_IN electrically connect the ground fault circuit interrupter to the phase and neutral line terminals of the alternating current source. The ground fault circuit interrupter is also electrically connected to a self-test circuit 14, a first contact 28 of a relay switch 31 in the AC-1_0UT terminal and a second relay contact 30 of the switch 31 in the neutral line terminal AC -2 0UT. Also connected to the line side of the relay contact 28, there is a phase port of the incorrect contact electrode detector 20 open, a charging port from which is electrically connected to the load side of the relay contact 28, the load terminal phase LOAD-1 of the ground fault circuit intelligent switch and a phase port of the incorrect closed contact electrical detector. The incorrect closed contact electrode detector 24 is electrically connected at a line side phase port to the load side neutral terminal of the AC-2_IN ground fault circuit interrupter and to a line side of the relay contact 30 , and in a load-side neutral port to a load side of the relay contact 30 and a LOAD-2 load side neutral terminal of the ground fault circuit intelligent switch. The intelligent ground fault circuit interrupter 10 also includes a power supply 26, which provides direct current for the intelligent ground fault circuit interrupter from the alternating current source. A phase port of the power supply 26 is electrically connected to the LOAD-1 phase load terminal and to the load side of the relay contact 28. A neutral port of the power supply is electrically connected to the LOAD-neutral load terminal. 2, and the load side of the relay contact 30. The power supply generates and supplies direct current to the system (ie, Vcc and Vcc / 2, which are not shown in the system diagram of Figure 1). A frequency calibration signal port is electrically connected to an input port of a timed signal generator 22. The timed signal generator 22 is electrically connected to timing ports of the incorrect open and closed contact power line detectors., 24, to the self-test circuit 14 and to the alarm circuit 18, respectively. The alarm circuit 18 is also electrically connected to the self-test circuit 14, the incorrect open-contact power line detector 20 and the incorrect closed-contact power line detector 24. One of the key features of the intelligent power circuit breaker Earth 10 is the ability of the device to detect an improper installation, i.e., an incorrect electrical wiring, to an electrical wiring system in which it is installed. The most common cause of improper electrical wiring occurs when the AC power source is connected to terminals LOAD-1, LOAD-2, and the load is connected to terminals AC-2, AC-2. The present invention anticipates such incorrect electrical wiring, whether the contacts are open or closed. More particularly, the incorrect open contact electrical detector 20 detects an incorrect electrical wiring condition when the relay contacts 28, 30 are in an open state, and the incorrect closed contact electrical detector 24 detects an incorrect electrical wiring when the relay contacts are in a closed state. The relay contacts 28, 30 pass alternating current to the load if the ground fault circuit interrupter 12 keeps the contacts in a closed state. The Automatic Gain Control (AGC) circuit 16 continuously adjusts the sensitivity of the ground fault circuit interrupter to track or compensate for ground leakage current, typically generated by loads attached to the system, i.e., appliances such as refrigerators, washing machines, washing machines, etc. The ground leakage current in many such devices can cause an annoying interruption of the ground fault circuit interrupters, if the appliances are located in a shared branch circuit, such as the ground fault circuit interrupter, due to the design of the electrical circuit system contained in it. Accordingly, the intelligent ground fault circuit interrupter, through the automatic gain control current, recognizes and adjusts this type of leakage current. The self-test circuit 14 is interfaced with portions of the center circuit system of the ground fault circuit interrupter, to provide a self-test without assistance, without attention, of the entire ground fault circuit interrupter circuit, including its SCR and the discharge coil. The power supply 26 generates the direct current electrical voltages required by the internal circuitry of device 10, through direct current connections identified in Figures 2-8, 9A and 9B, and includes neutral and frequency calibration ports ( that is, 60 HZ, which will be discussed in greater detail later). The device 10 uses voltages of 12 and 6 volts, that is, Vcc and l / 2Vcc, respectively. The timed signal generator 22 generates the signals that finally warn the user of a need to test the device 10, as well as to activate periodic internal self-tests. The alarm circuit 18 serves to indicate an alarm state to the user, for example, an audible signal to communicate various alerts to the user, such as when there is an incorrect power line situation. In the preferred embodiment, the alarm circuit includes a ceramic piezoelectric element as the sound producing component that in fact generates the alarm sound. As an alternative, the sound can be produced by a horn, a buzzer or other sound generating element, known to those skilled in the art. Alternatively, it is contemplated that the alarm circuit generates a flag signal, which can be transmitted to a detector linked to a digital computer, which acts in accordance. The circuits defining the embodiment of the present invention, which is shown in Figure 1, and which were briefly described above, will now be described in greater detail, with reference to Figures 2-8, 9A and 9B. In the figures, the same numbers define the same terms. Figure 2 is a detailed schematic diagram of a mode of power supply 26, previously identified in Figure 1. The power supply 26 is shown electrically connected at its phase port to the load side of the relay contact 28 and the LOAD terminal -1; the frequency calibration port outputs a signal that crosses the zero, or clock "" 60 HZ ", which is generated in it, to synchronize the operation of the system or device 10. The power supply rectifies the current alternating supplied through the ground fault circuit interrupter 12, through the contact 28 while it is operational, providing by means of the same, a signal of l / 2Vdc and a signal of Vcc to the rest of the system. preferably, a CMOS device, in order to minimize the total energy dissipation for the device 10 to average between 10 and 20 milliwatts A preferred form of the power supply circuit is as follows: A resistor 32, having a value nominally between 10 and 20 ohms, is electrically connected to a load end side of the relay contact 28, and to a second end of a first end of a capacitor 36 and to a first end of a resistor 34. The second ends of the resistor 34 and the capacitor 36 are electrically connected to the timed signal generator 22, as mentioned above, to a cathode end of a zener diode 38 and an anode end of a diode 40. The capacitor 36 serves as an impedance in series to reduce the line voltage of the alternating current on the load end side of the contact 28, with the energy requirement in the supply being relatively low; the capacitor 36 also helps in the correction of the energy factor. By defining the capacitor 36 with a value of 1 μF, an equivalent impedance of approximately 2.6 KO at 60 Hz is generated. The resistor 34, in parallel with the capacitor 36, is designed with a high value (around 100 K ohms). ) to limit the current through the zener diode 38. The zener diode 38 displays a flashover value of about 15 V, in order to previously regulate the input voltage of the alternating current. The zener diode 38 also defines the origin of the signal crossing the zero, 60 Hz, and the clock input to the timed signal generator 22. The cathode end of the diode 40 is electrically connected to an anode end of a storage capacitor 42 , a first end of a current limiting resistor 44, and the collectors of the NPN transistors 50, 48, 58. The diode 40 provides half-wave rectification for the storage capacitor 42, which provides current to the zener diode 46 and avoids the discharge of the storage capacitor 42, during the negative half cycle of the alternating current source. A second end of the resistor 44 is electrically connected to both a base of the transistor 48, and to a cathode end of a second zener diode 46. The resistor 44 supplies current from the storage capacitor 42 to the zener diode 46, which displays a Disruptive voltage of 13 V, to maintain a constant voltage in the NPN transistors 48, 50. The anode ends of the zener diodes 38, 46, and the cathode end of the storage capacitor 42 are electrically connected to ground. An emitter of transistor 48 is connected to a base of transistor 50, and an emitter of transistor 50 is connected to a connector of an NPN 60 transistor (defining Vcc). An emitter of transistor 58 is electrically connected to a base of transistor 60, an emitter of which provides l / 2Vcc. A collector of the transistor 60 is electrically connected to a first end of a resistor 54, a first end of a storage capacitor 56 and a base of the transistor 58. The cathode end of the storage capacitor 56 and the second end of the resistor 54 are connected electrically to ground. The storage capacitor 56 helps maintain the base of the transistor 59 at a constant voltage in the event of momentary oscillations in the Vcc. Resistors 52, 54 are defined to be approximately 100 KO, to form a voltage divider whose output is about one half of the voltage Vcc pair regulate the pair of NPN transistors 58, 60. Accordingly, a constant voltage of about l / 2Vdc is supplied from the emitter of the transistor 60. The reduced voltage of l / 2Vcc serves as a reference voltage for some of the voltage comparators that are used in the circuitry of device 10. Because the power supply 26 is connected to the AC source on the load side of the relay 28, no power is supplied for any reason to the unloading of the relays 28, 30 of the system. Figure 3 is a detailed schematic diagram of an embodiment of an alarm circuit 18, previously identified in Figure 1. The alarm circuit 18 receives many inputs from the circuits still to be described in detail, for example, it is supplied a bar MISWIRE_OPEN signal from the incorrect open contact power line detector 20 (Figure 5), a bar MISWIRE_CLOSED signal from the closed contact incorrect power line detector 24 (Figure 6), and a pair of bar SCR_FAIL signals and bar GFCI_FAIL from the self-test circuit 14 (Figures 9A, 9B), all of which are supplied to a Nand 62 circuit. The designation 'bar' after any signal name means that the signal is active low. The logic output of the Nand circuit 62 provides an ALARM_TRIP signal to the cathode ends of the diodes 64 and 66. An anode end of the diode 64 is electrically connected to a first end of a resistor 65 to generate an input signal to a Nand circuit. 70. The Vcc is also connected to a second end of the resistor 65 and to the logical Nand 70 circuit. The logic output of the Nand circuit 70 is provided to a cathode end of a diode 80, an anode end of the diode 66, and to the first ends of the resistors 72 and 76. The second end of the resistor 76 is electrically connected to a cathode end of the resistor. diode 74, whose anode end is electrically connected to a first end of a discharge capacitor 78, a second end of resistor 72 and a second input to circuit Nand 70. An anode end of diode 80 is electrically connected to Vcc through a resistor 82, and to an input of a logic alternative circuit 84. A second input to the alternative circuit 84 receives a TEST_REMINDER signal from the timed signal generator 22 (which will be described later with reference to Figure 4); The logic output of the alternative circuit is electrically connected to a logic Nand 86 circuit. A second input to the Nand circuit 86 is electrically connected to the logic output of the circuit through a resistor 88. The magnitude of the output signal (feedback) is maintained at a first end of a capacitor 90, whose second end is connected to Earth. The logic output of the Nand circuit 86 is also electrically connected to an input to the PIEZO 92 element, an output of which is connected to ground, to generate an alarm. The PIEZO element is only an example of an alarm or sound generation circuit 18, which can be used in the system to produce various alarm or beep sounds of different duration to communicate when the system 10 is in certain states, or in the occurrence of various events. For example, the alarm or "beeping" will signal the user in the event that an incorrect power line condition is detected. The actual frequency of the sound emitted by the circuit 18 is determined by the values of the resistor 88 and the capacitor 90, which are coupled to the gate 86 in a classical oscillator configuration. The charging and discharging of the capacitor 90 causes the logic output of the Nand circuit 86 to swing back and forth or oscillate with a duty cycle of approximately 50 percent, because the capacitor 90 is charged and discharged through the same resistor 88. If, however, the output of the alternative circuit 84 is low, the oscillations cease, because the output of the Nand circuit 86 remains high no matter what appears through the capacitor 90. Preferably, the resistor 88 and the capacitor 90 define a time constant RC which rings the component 92 that produces the sound in between 2.5 to 3.0 KHz. As long as the output of the gate (circuit) Or 84 is high, the oscillator causes the resonator 92 to generate a tone. The Nand 70 circuit, resistors 72, 76, the diode 74 and the capacitor 78 determine the duty cycle (i.e., the on and off times) of the oscillator built around the Nand circuit 86 to activate the PIEZO 92 element. The tone duty cycle, however, is not symmetric because the resistors 72, 76 have different values, whose parallel combination determines the duration of the tone off. Due to the blocking effect of the diode 74, the resistor 72 only determines the duration of ignition of the tone. Resistors 72, 76 are preferably chosen to produce on-pitch periods of approximately 150 milliseconds and one-off off-tone. The tone occurs when the ALARM_TRIP signal is high (ie, the diodes 64, 66 are negatively polarized in reverse). This allows the output of the logic Nand circuit 70 to oscillate due to the charge and discharge of the capacitor 78, similar to the action of the capacitor 90, as described above. The input of the alarm signals in the logic Nand circuit 62 is generated by system 10, when either an incorrect power line condition or a fault related to the ground fault circuit interrupter is detected. A low, therefore, in any of these inputs causes the alarm circuit 18 to output an audible or visual alarm, to warn the user that an incorrect power line condition or fault has occurred. Conversely, by keeping the tone or alarm indications off, the non-feedback inputs to the logical Nand 70, 86 circuits are kept in the low state by the ALARM_TRIP signal, causing the logic signals that came out from there stay in the high state, which prevents oscillation. A low output is provided from the Nand circuit 62 through the diodes 64, 66 forcing the outputs of the Nand circuits 70, 86 to remain in the high state. The logic Ñor circuit 84 enables the oscillator that activates the element PIEZO 92 with the signal TEST_REMINDER generated inside the timed signal generator 22. This TEST_REMINDER signal works to remind the user to periodically manually test the device 10. When the signal of TEST_REMINDER is high, the resonator 92 will produce a short alarm tone (or a short infrared visible light output) once per minute. Figure 4 is a detailed circuit diagram of a mode of a timed signal generator 22, described above in relation to Figure 1. The combination of the timed signal generator and the alarm circuit 18, contained within the present invention, it was developed in part because it was found that instructions for the user (accompanying conventional ground fault circuit interrupters) to periodically test the system or device, at least once a month, are typically ignored by the user. In addition, it was found that most users ignore the clear notes placed not only inside the installation instructions of the unit, but even those on the front of the device itself. The timed signal generator aims to compensate for this reality by causing a short chirping sound to be generated once every minute to remind the user to test the device once a test reminder signal is enabled (preferably every 30 days). The timed signal generator 22 also generates test pulses using the built-in test circuit system (self-test circuit 14, identified in Figures 9A, 9B, which will be described in detail below) to precipitate an automatic self-test once every hour , and the energy in the reset signal (P R_0N_RESET) that is used in the system 10 to put various components in a known state when the system energy is initialized. In the core of the signal generator 22 is a chronometer circuit 114, which may include any monolithic integrated circuit, a group of logical functions MSI or LSI, a sequencer based on read-only memory or another circuit activated by clock, known to those skilled in the art, which is capable of counting. Upon application of the energy to the system, the timer 114 generates the PWR_ON_RESET and P R_ON_RESET bar signals, which are active immediately after the energy is applied, and remain active for at least 100 msec. The 60 HZ signal provided by the power supply 26 (signal crossing the zero generated by the zener diode 38) activates the chronometer. All the signals generated by the timer 114 are finally derived from this clock input. As mentioned above, 30 days after the AC power is initially applied, the ground fault circuit intelligent switch device 10 issues a high active test reminder signal, TESTJREMINDER, to warn the user of the need for • manually test the device 10. To do this, the user momentarily presses a switch button 94 (not shown in Figure 1) located on the front of the device 10, the end of which is connected to the LOAD-1 terminal. An opposite end of the switch 94 is electrically connected to a first end of a resistor 96, a second end of which is connected to the terminal AC-2. The first end of the resistor 96 is also electrically connected to a first end of a resistor 98, a second end of which is connected to an anode end of a diode 100. A cathode end of the diode 100 is electrically connected to a first end of the diode 100. a resistor 102, at an anode end of a diode 106, a reset input to the timer 114 and a first end of a resistor 112. A second end of the resistor 112 is electrically connected to a first end of a capacitor 113, a second end of which is connected to ground, and also as a GND input to the timer 114. The cathode end of the diode 106 is electrically connected to Vcc and to an anode end of a diode 108. A cathode end of the diode 108 is electrically connected to a first end of a capacitor 110, a second end of which is connected to ground, and as an input Vdd to stopwatch 114. In addition to the signals of POWER_ON_RESET, P0W ER_0N_RESET bar mentioned above, the stopwatch also generates the signals 150MS, 300MS, 1MIN, ÍHR, 2HR, 60_DAY, 120_DAY and 240_DAY. The signals 60_DAY, 120_DAY and 240_DAY are provided as inputs to a logic alternative circuit 146, an output of which is provided to a logic circuit Nand 126, together with the signals 1MIN and DAY generated by a signal generating circuit DAY 117. Inside of the signal generating circuit DAY 117, a first end of a resistor 120 is electrically connected to an anode end of a diode 124. The second end of the resistor 120 is electrically connected to the first ends of a resistor 116, and of a photoresistor 118. , which are electrically connected in parallel to the Vcc. The second ends of the resistors 116 and 118 are electrically connected to a base and an emitter of an NPN transistor 119, respectively. A transmitter transmitter 119 is electrically connected to a first end of a resistor 122, a second end of which is connected to ground, and to a cathode end of a diode 124. The PWR_ON_RESET bar is provided to each of the three Or 128 circuits, 130 and 132 logical. 150MS is provided to the logical circuits Or 130 and 132, and 300MS is provided to the alternative logical 128 service. The output of the alternative logic circuit 128 is provided as a low active reset to a D-type trigger circuit 134. An output is provided from the logic circuit Nand 126 as a clock input to the trigger circuit; the Vcc maintains the "D" input of the high circuit, through a resistor 140. Trigger circuits type "D" 136 and 137 are also included, which are electrically connected by the forward resistors 142 and 144 to the Vcc. The signals ÍHR and 2HR are electrically connected as clock inputs to the f / f circuits 136 and 138, respectively, from the timer 114. The output of the signals from the logic circuits Or 130 and 132 is electrically connected to the circuits f / f 136, 138 as active low reset inputs. Finally, the signals TEST_REMINDER, bar 1HR_PULSE and bar 2HR_PULSE are the logic outputs that come from the outputs "Q", "Q bar" and "Q bar" of the trigger circuits 134, 136 and 138, respectively. Activation of the momentary switch 94 simulates a ground fault by momentarily causing the current flowing within the device to diffuse via terminals AC-1 and AC-2. If it is working properly, the ground fault circuit interrupter circuit 12 (Figure 7) detects the difference in current flow, by means of the magnetic cores 312, 314, and generates an SCR control signal therein. As a result, the SCR 244 is triggered within the ground fault circuit interrupter, the relay discharge coil 260 is energized and the relay contacts 28, 30 of the ground fault circuit intelligent switch are energized. The pressure of the test button 94 also causes the timer 114 to reset, by readjusting its internal counters and beginning a count of a 30-day period again. The timer reset input, which is high active, is coupled to the TEST_BUTTON signal through the resistor 98 and the diode 100. The resistor 102 and the capacitor 104 provide filtering for the reset input signal.

Trigger circuit "D" 134, therefore, operates as a trigger and generates a high pulse of 150 ms long once every minute, that is, the signal TEST_REMINDER. Since its input goes up through the resistor 140 to Vcc at each rising edge of its clock input, high logic is clocked to the trigger circuit, and appears at the "Q" output of the circuit. The output of the logical Nand 126 circuit goes up when all its inputs are high. Approximately 30 days after the energy was initially applied to the device 10, the signal 60_DAY becomes high, causing the output of the alternative logic circuit 146 to be high. If the DAY signal and the 1MIN signal are also high, the trigger circuit ("D" f / f) 134 is clocked and high logic appears at the "Q" output of the circuit. Approximately 150 ms later, the 300MS signal from the timer 114 becomes low and readjust the output "Q" of the trigger circuit 134 to a logic low. The 300MS signal is coupled with the bar signal PWR_0N_RESET to allow any signal to reset to the trigger circuit 134. This reset signal can also readjust the trigger circuits 136, 138, through the logic circuits Or 130, 132, respectively . The output of the signal DAY from the circuit 117 is activated high when the intensity of the light surrounding the intelligent ground fault circuit interrupter device 10 sufficiently decreases the resistance of the photoresistor 118. Consequently, an increased current flows through the transmitter of transistor 119 and resistor 122, negatively polarizing in reverse to diode 124 and the voltage level of signal DAY that will be pulled to Vcc. When there is insufficient light intensity (ie, at night), the resistance of the photoresistor 118 is very high, which limits the current flow through the resistor 122 to negatively polarize the inverse to the diode 124. Then, the Resistor 122 dissipates the current to ground, maintaining the output of the Nand circuit 126 at a low logic. This prevents the TESTJREMINDER signal from sounding during the evening and night hours, the time when most people are asleep. If the user does not pay attention to the TEST_REMINDER signal that occurs once every minute, which started after 30 days, the signal will remain active for approximately another 210 days after which the timer 114 resets itself. If at any time during the 210 days the user manually tests the device 10, the timer 114 is readjusted and starts counting again the 30 day period. The clock signals 120_DAY, 240_DAY alternate with signal 60_DAY in the alternative logic circuit 146, to form one of the 'three inputs to the alternative logic circuit 126, each of which can cause a state change in the output of the trigger circuit 134, ie the signal TEST_REMINDER. Another key feature of the ground fault circuit intelligent circuit breaker system 10 is its ability to detect an insorresting power line condition, when the system is connected to the contacts of the contact relays 28, 30 in either an open or closed state. . This is very important because it is impossible to predict in what state the relay contacts will be when the AC power is applied for the first time. The open-contact contactless detector 20 detects and memorizes, using the trigger circuit 174, whether the alternating current energy is correctly connected to the terminals AC-1, AC-2, or incorrectly to the terminals L 0 AD-1, LOAD-2 This detection occurs at a point in time a little after the energy is initially applied. If the device 10 is installed with the relay switches 28, 30 already in the closed position, which is a real possibility, the detection circuit system is omitted., in which case the incorrect closed contact electrical detector 24 must make a determination of whether the electrical wiring is appropriate or inappropriate. With reference to Figure 5, a detailed flow chart of a preferred form of an incorrect open contact electrical line detector 20 will now be described. The terminal AC-1_IN is shown in the figure electrically connected to an anode end of the diode 148 and the line side end of the contact 28; the load side end of the contact 28 is electrically connected to both the LOAD_l terminal, and to an anode end of a diode 160. The cathode ends of the diodes 148, 160 are electrically connected to the first ends of the resistors 150 and 162 , respectively. The second ends of the resistors 150 and 162 are connected to the first ends of the resistors 152, 164, respectively, and also to the base of the NPN transistors 156 and 168, respectively. The emitters of the transistors 156, 162 are grounded, and the collectors are connected through the resistors 154, 156, respectively, to Vcc. A second end of the resistor 152 is conested to the terminal AC-2_OUT, to the line-side end of the probe 30, to the first end of a resistor 151 and to the first end of a capacitor 153. Accordingly, the combination of the resistors 150 152 acts as a voltage divider to negatively bias the base of the transistor 156. The collector of the transistor 156 is also latched both to the alternative logic bus 175 and to the logic conjunction circuit 172. A second end of the resistor 164 is elastically cones to the load side end of the relay 30, to a second end of the resistor 151 of a second end of the capacitor 153. The combination of the resistors 162, 164 together form a voltage divider. , which defines the base input to the transistor 168. The cholestor of the transistor 168 is also set to the alternative sirsuite 175, and as double inputs to a Nand 170 logic loop. An output of the Nand circuit 170 is provided as a logical input to the cirsuite by sonjunion 172. An output of the link circuit 172 is provided as a "D" input to a trigger cir- cum 52. The operation of the detector cir- cum 20 is dependent on the NPN transistors 156, 168, which are arranged to detect the alternating current energy between the AC line side and the LOAD terminals. If an AC power source is correctly confected to the terminals AC-1, AC-2, and, if the contacts of the relays 28, 30 are in the open position, the alternating current energy is only pumped through the diode 148. The LOAD side of relays 28, 30, is left without AC power. The collector current flows through the resistor 154 from Vcc to ground, and a low logic is applied to the input of the cirsuite by sonjunsión 172 logiso. For sonicity, the input to trigger trigger 174 is a low logic, regardless of the state of transistor 168, as long as AC power is applied across terminals AC-1, AC-2. The timed signal generator 22 (Figure 4) supplies the bar signal PWR_ON_RESET as a clock input to the trigger circuit 164, whose guiding edge times the "low" input outside as a "Q bar" signal, defining a signal MISWIRE_OPEN of bar in a high state (that is, without incorrect power line condition). Therefore, if energy is applied to the open contacts 28, 30, the output signal from the detection circuit system 20 remains high. Alternatively, if the AC power is incorrectly connected to the terminals LOAD-1, LOAD-2, and the relay contactors 28, 30 are in the open position, the transistor 156 remains off and the resistor 154 pulls an input to the circuit by conjunction 72 logically high, on the application of AC power. Therefore, the current flows through the diode 160 and is separated inside a voltage separator formed by the resistors 162, 164, by turning on the transistor 168. Consequently, the current flows through the resistor 166, grounding the inputs to the logical alternative circuit 170. The logical output of the alternative circuit goes up, which causes the output of the signal from trigger cir- cuit 174, MISWIRE_OPEN, to go down over the rising edge of the bar signal PWR_ON_RESET. A low signal from the MISWIRE OPEN bar activates the alarm circuit 18, the sual warns the user that there is an incorrect power line condition. Since the timer 114 of the timed signal generator 22 is synchronized with the 60 Hz signal, the rising edge of the bar signal PWR_ON_RESET does not occur at zero crossing, but at a point within the alternating current cycle, in which the data that operate as logical inputs to the Nand and And 170, 172 circuits are reliable. If the AC power is incorrectly connected to the terminals LOAD-1, LOAD-2, and the relay contacts 28, 30 are When closed, the application of alternating current power will prevent the open sontasto 20 electrical signal from detecting the alarm. Therefore, the bar output signal MISWIRE_OPEN remains high. Accordingly, a deference is made for the incorrect closed contact electrode detector 24 to determine whether the device 10 is correctly connected, and the alternative logic circuit 175 generates a bar CONTACT_CLOSED signal from the collector outputs of the transistors 156, 168, which are low only when the relay contacts 28, 30 are in the closed state. The closed contact malfunction detector 24 uses the bar signal C0NTACT_CL0SED to determine if the earth fault circuit interrupter circuit system 12 is properly connected.

If the relay contactors 28, 30 are open, the control passes from the insensitive sontasto serrated electrode 24 to the open contact insterest resistor 20 to determine if the device 10 is properly connected. Referring now to Figure 6, a preferred form of the closed contact incorrect electrical wiring detector 24, described above with reference to Figure 1 will be described. Because the mechanical relay contacts 28, 30 exhibit a finite ohmic resistance, it is generated a detectable voltage drop through each, in the energy rise when the contacts are in their closed state. More particularly, on energizing the system, the system 10 simulates a serge carrying 2 to 3 amps on the extreme load sides of the contactors 28, 30 for a period of time of approximately 250 μsec. This burst of current generates a finite voltage drop across the equivalent impedance of the relay contacts 28, 30, which is in the order of 3 mO. This voltage drop can be detected and amplified using standard components, and will only be generated if the device 10 is properly connected. If it is connected inappropriately, no voltage drop will appear through the relay counters. In the preferred embodiment, only the voltage drop is detected through one of the relay contacts, the relay contact 28. However, any of the relay contacts 28, 30 can be used to detect the presence of the voltage developed through its impedance "on" equivalent. The line side end of the contact 28 is electrically connected to the terminal AC-1_0UT of the ground fault circuit interrupter 12 and to the first ends of the resistors 182, 184, and to a capacitor 186. A second end of the resistors 182 , 184, and a first end of the capacitor 188 are electrically connected to the load end side of the relay sontaste 28 and to the LOAD-1 terminal. The second end of the capacitors 186, 188 are electrically connected, respectively, to invert and not reverse the op-amp inputs 190. The reversing input to op-amp 190, is also elastically matched to a cathode end of a diode 189 , to an anode end of a diode 187 and to a first end of a resistor 181. The non-inverting input to op-amp 190, is also electrically connected to an anode end of the diode 189, to a cathode end of the diode 187 and to a first end of a resistor 183. The second ends of the resistors 181, 183 are respectively connected to a first end of the resistor 178 and to a second end of the resistor 176, and to a second end of the resistor 178 and to a first end of the resistor 180. The first end of the resistor 176 is connected to Vcc and the second end of the resistor 180 is connected to ground. An op-amp output 190, a CONTACT_CURREN signal, is electrically connected to a logical alternative bus 207. Also electrically connected to the terminal LOAD-1 is an anode end of a diode 202; a cathode end of the diode 202 is electrically connected to the first ends of the resistors 204 and 192. Each of the second ends of the resistors 204 and 192 are electrically consti- tuted to a FET consumption 206 and to an anode end of the diode 196. A The cathode end of the diode 194 is sonicated elastically both to a first end of a resistor 196, a second end of which is connected to the LOAD-2 terminal, and to a base of an NPN 200 transistor. An emitter of the transistor 200 is also const to the terminal LOAD-2, while its collector (signal CURRENT_FLOW) is electrically connected to a gate of FET 206, to a first end of a resistor 198, and to an input to a circuit Nand 208. The signal PWR_ON_RESET, generated by the stopwatch 114 inside the timed signal generator 22, to a second end of the resistor 198 to control the state of the FET gate 206. The bar CONTACT_CLOSED signal is input, generated within the incorrect open contact power detector 20 to the alternative circuit 207 with the signal CONTACT_CURRENT . An output of the alternative circuit 207 is provided as a "D" input to a trigger circuit 202. The CURRENT_FLOW signal is provided within the Nand 208 circuit, an output of which (CURRENT_FLOW bar), with the signal PWR_ON_RESET, is provided as a clock input to the trigger circuit 212, by the alternative logic circuit 210. An output of the trigger circuit "Q" defines a bar MISWIRE_CLOSED signal. Upon energization of the device, a positive PWR_ON_RESET pulse is provided by the timer 114 as an input of the alternative circuit 210, to the chooser of the transient 200 and to the gate of the n-channel MOSFET 206, through the resistor 198 (100 Kohms). The PWR_ON_RESET signal has a minimum duration of at least one complete alternating current cycle. The pulse time length is defined to overlap at least one zero crossing that goes from negative to positive of an energy signal generated by the alternating current source. The MOSFET 206 is used as a voltage controlled switch, to control the current flow from the alternating current power source, through the resistor 204. Having a value of about 1 to 2 ohms, the resistor 204 allows them to flow approximately 2 to 3 amps through the relay contacts 28, 30, when the line voltage of the alternating current reaches approximately 4 to 5 volts. The current flow through the resistor 204 is restricted to the positive half cycle due to the blocking effect of the diode 202. Furthermore, the MOSFET 206 can only be turned on at a zero cross from negative to positive, due to the action of the transistor 200 Resistors 192, 196 and diodes 202, 194 provide base current during the positive half cycle to block the MOSFET gate 206 to ground, preventing it from igniting. However, sufficient base current is not generated until the AC line voltage reaches approximately 4 to 5 volts. In this way, current is allowed to flow through the resistor 204 until the line voltage of the alternating current reaches 4 to 5 volts, after which the transistor 200 is turned on, grounding the MOSFET gate 206, turning it off effectively. The current flow through the resistor 204 produces a voltage drop of about 10 mV across the relay contacts 28, 30 for approximately 250 μsec. The MOSFET gate 206 is the source for the CURRENT_FL? W signal, which is reversed before it alternates with the bar signal PWR_ON_RESET through alternative cirusuite 210. If the device is properly connected to the power source of current alternating while the contacts are closed, the voltage comparator 190 senses and amplifies the voltage drop produced through the ohmic resistor 182 of the relay contact 28. Both sides of the relay contact 28 are coupled to the inputs of the voltage comparator 190, through capacitors 186, 188 of 0.01 μF. These layers provide insulation between the reference voltage and the earth of the comparator circuit 190. The voltage separator, which is formed by the resistors 176 (10 MO), 178 (1 KO), 180 (2 MO), supplies the voltage of reference that the purchaser 190 needs to determine if the ground fault circuit smart switch device 10 is properly connected. The resistors 181, 183 protect the inputs of the comparator 190 when the relay contacts 28, 30 are in the "open" position by limiting the current between the AC power source side and the load side of the relay contacts 28, 30. Diodes 187, 189, back to back, limit the voltage potential between the inputs of the amplifier to a drop of the diode to protect it against damage due to excessive voltage. If the device is connected correctly, a positive pulse signal (ie a 12 volt signal) appears at the output of the comparator 190. This high logic active signal, CONTACT_CURRENT, is clocked in the trigger circuit 212 after having been first connected with the bar signal C0NTACT_CL0SED in the alternative circuit 207. The output "Q" is a low active signal, MISWIRE_CL0SED bar, and is only in a low logic when both relay contacts 28, 30 are in the closed state • , otherwise MlSWIRE_CL? SED bar is high. If the bar MISWIRE_CLOSED is in high logic, then the relay contacts 28, 30 are open and the trigger circuit input is in high logic, regardless of the logic level of the CONTACT_CURRENT signal. This is to ensure that the output signal of the bar circuit MISWIRE_CLOSED 212 remains high in the case that the relay contacts 28, 30 are in the open state, in accordance with the open contact insorrested power line detector 20, to determine if there is an incorrect power line condition. The signal provided by the alternative circuit 210 remains at a high logic level from zero crossing until the alternating current reaches 4 to 5 volts. At that point, transistor 200 is turned on and dissipates the signal in the gate of MOSFET 206 to ground, causing the CURRENT_FLOW signal to go low. This signal is inverted by the Nand circuit 208, whose edge in elevation is used to time the level of the signal CONTACT_CURRENT to the output of the trigger circuit 212. The output, MISWIRE CLOSED of the bar, is high if no condition of the signal is detected. the wrong power, and low if an incorrect power line condition is detected. If the device 10 were incorrectly connected (ie, that the AC power source was connected to the LOAD-1 terminals, LOAD-2), and the relay contacts 28, 30 were closed, the current produced by the resistor 204 would not flow through the contacts 28, 30. This is because the current path extends from the LOAD-1 terminal, through the diode 202, the resistor 204, the MOSFET 206 to the LOAD-2 terminal . Consequently, no current flows through the relay contactors 28, 30, which causes the output of the comparator 190 to go low. The signal C0NTACT_CL0SED is therefore driven low, since the alternating current appears on both sides of the relay contacts 28, 30. Correspondingly, when the trigger circuit 212 is clocked, the bar signal MISWIRE_CLOSED goes low, activating the alarm, warning the user that the device 10 is incorrectly connected and causing the relay contacts 28, 30 to be interrupted by the optocoupler 248 (Figure 7). With reference to Figure 7, a preferred embodiment of a ground fault circuit interrupter circuit 12, described above extensively in connection with Figure 1, will now be described. Terminals AC-1 and AC-2 of the intelligent circuit breaker of Ground fault can be electrically connected to the neutral phase lines of the alternating current source and to the phase and neutral line terminals of the ground fault circuit interrupter AC-1_IN and AC-2_IN. A first phase conduction element 211 connects the terminal AC-1_IN to the terminal AC-l_OUT, and a second neutral condussion element 213 electrically the terminal AC-2_IN to the terminal AC-2_OUT. The terminals AC-1_0UT and AC-2_OUT are also electrically connected to the line sides of the contactors 28, 30, respectively. The driving elements 211 and 213 are positioned in such a way that they extend through a pair of magnetic cores 312, 314, which detest alternating current flowing in and out of the ground fault short-circuit intelligent switch device 10. Terminal AC-1_0UT is also electricallystated to a first end of relay coil 260; a second end of the relay coil 260 is elastically cones to an anode end of a diode 252 and a cathode end of the diode 256, which together with the diodes 254, 258, form a portion of a diode bridge. The cathode ends of the diodes 252, 254 are electrically connected to an anode end of a SCR 244. The cathode end of the SCR 244 is connected to a first end of a resistor 246, a second end of which is connected to a continuous ground and and a transmitter gate of a transistor 249 of an optoelectronic switch 248. The anode end of the SCR 244 is also electrically connected to a first end of a resistor 242 and to a collector of the transistor 249 of the switch 248. The magnetic core 312 generates an AGC_IN signal which is proportional to an amount of current flowing inside the ground fault cirsuite switch, and provides the signal as an input to pins 2 and 3 of LM1851 228; the AGC_IN signal is also provided to the automatic gain control circuit (AGC) 16 (Figure 8). The magnetic core 314 generates a signal that is proportional to an amount of current flowing back from the ground fault circuit interrupter (in the neutral) and provides the signal through a capacitor 226. A first end of the capacitor 226 it is also connected to a second end of a capacitor 222 as an input to pin 4 of LM1851, and to the anode ends of diodes 256, 258. A second end of capacitor 226 is electrically connected to pin 5 of LM1851 228. The LM1851 228 is an integrated circuit which, through its input pins, detects small differences in the current flowing through terminals AC-1 and AC-2, identifying, by the same, ground faults. Upon detection of a ground fault, LM1851 228 carries the fault information by the status of a signal, GFCI_0UT, provided on pin 1. Pin 1 is electrically connected to a first end of a resistor 230, a second end which is connected to a first end of a capacitor 240 and to a gate of an SCR 244. The state of the output of pin 1 (ie, the signal GFCI_0UT) controls the status of SCR 244, by integrating the output of the ground fault circuit interrupter. In other words, a particular level in the capacitor 240, referred to as the SCR_GATE signal, controls the impedance state of the SCR. SCR_GATE defines the driving state inside the SCR path to ground, which in turn defines the current flow from the AC-1 terminal, through the conductive element 211, through the relay coil 260, the diode 252, the conduction path of SCR 244, and the resistor 246; Neutral line current flows through diode 258, element 213 through AC-2. The flow of current through the coil 260 forces the relay contacts 28, 30 to an open state, cutting the power to the load and preventing a user from being injured. The automatic gain control circuit 16 (Figure 8) is electrically connected to the ground fault circuit interrupter 12, through the first and second ends of a resistor 232, which preferably has a value of about 2 MO. The signal that comes out from the automatic gain control circuit through resistor 232, varies the sensitivity of LM1851 228 to the leakage current detected in the system. A first end of the resistor 232 is also electrically connected to the pins 8 and 6 of the LM1851, and the second end of the resistor is connected to the pin 8, to a cathode end of a diode 234 and to an anode end of a storage capacitor 236. The pin 7 of the LM1851 is electrically connected, through a capacitor 238, to a continuous and slow ground. As mentioned above, the SCR_GATE signal controls the flow of current through the SCR 224, and the choke and emitter of the transistor 249 of the opto-opener 248, is connected through the anode and cathode ends of the SCR 244. The optocoupler responds to an ALARM_TRIP signal, generated inside the alarm circuit system 18, and that is provided at photodiode 251. When the ALARM_TRIP signal goes high, that is, an alarm condition occurs, current flows through the photodiode to ground, through resistor 250. This causes the optocoupler to turn on, creating an alternate path for the current that deflects the SCR and energizes the coil 260 opening, by means of the relay contacts 28, 30. In this way, the optocoupler serves as a backup or alternative element for the interruption of the relay contacts 28, 30, and either when the SCR has failed or when a fault has been detected in the ground fault circuit interrupter circuit system 12. Another slave interface of the system 10 of the The invention is its ability to dynamically adjust sensitivity. to the leakage current of the ground fault circuit interrupter circuit 12, using the automatic gain control. Currently, certain devices are not required to be protected by a ground fault circuit interrupter, because they generate an undesirable parasitic ground leakage current, which would interfere with the normal operation of a ground fault switch. Appliances such as refrigerators, dishwashers, washing machines, etc., or devices with switchable power supplies in it, for example, typically use capacitors in their filter circuits. These capacitors are usually connected directly to the ground wire of the AC power line, thereby generating a ground leak and causing an "annoying interruption" of the ground fault circuit interrupter. Because the intelligent ground fault circuit interrupter of the present invention overcomes the problems associated with such devices, it is envisioned that intelligent ground fault circuit interrupters will become a UL requirement within the mieme.

With reference to Figure 8, a preferred embodiment of an automatic gain control circuit 16, described above extensively with reference to Figure 1, will now be described. The automatic gain control circuit 16 detects and compensates for a leakage current of Slow, steady and fast lifting. In other words, the automatic gain control circuit distinguishes between a fast-rising leakage current caused by a human, and a constant or slow-rising leakage current caused by certain artifacts or other devices. In a case where the leakage current is constantly increased, the ground fault circuit interrupter tracks this increase and raises its internal reference threshold level for interruption, over which an additional 5m will interrupt the circuit breaker of ground fault. In the case of a steady state or slow-rise leakage current, up to 25 ma can be compensated by the automatic gain control circuit 16. However, any leakage current over 30 ma will interrupt the ground fault circuit interrupter . Although the sensitivity can be increased in immobile or constant state, the dynamic sensitivity of the ground fault cirsuite switch does not change. At all times, 5m of leakage at rapid elevation (ie, that produced by human contact) will interrupt the ground fault circuit interrupter circuit. In order to receive the AGC_IN signal from the ground fault circuit interrupter 12, the first ends of the layers 340, 342 are coupled to the core 312 of the ground fault circuit breaker. The sapacitores prevent the self-generating ganglia sontrol circuit from interfering with the current detection by the ground fault circuit interrupter 12. The second ends of the capacitors 344 and 346 are electrically connected to the first end of the resistors 344. , 346, the second ends of which are con- sistently used to invert and not reverse the inputs to op-amp 349, respectively. The second end of the sapacitor 342 is also electrically consisted through a resistor 348 to l / 2Vcc. An op-amp output 349 is electrically connected to the cathode end of the diode 350, an anode end of which is connected to ground, and to an anode end of the diode 352. The cathode end of the diode 352 is electrically connected to a first end of a diode. capacitor 362, to a first end of a resistor 358, a second end of which is grounded, to a first end of a resistor 356 and to a proximal end of the diode 354. The anode end of the diode 354 is electrically connected to a first end of a capacitor 360, a second end of which is connected to ground, and to a first end of a resistor 368. A second end of the capacitor 362 is electrically connected to a base of the NPN tracer 366 and to a first end of the reefer 364, a second end of which is connected to earth. An emitter of transistor 366 is connected to ground, while its collector is connected to a second end of resistor 368, to a first end of resistor 280, a second end of which is connected to ground, and to a base of transistor 286. The transmitter of the transistor 286 is connected, through a resistor 286, to ground, and a collector is connected, through a resistor 284, to a gate of FET 290. The second end of the resistor 284 is also electrically connected to a first end of a transistor 282. A second end of the resistor 282 is elastically latched to a first end of a resistor 292 of 500 K ohms, a second end of the sual is connected to a source of the N-channel of FET 292. The output of the signal of amplifier 349 is rectified by diodes 350, 352, and charged to capacitor 360, through resistor 356. The voltage appearing through capacitor 360 negatively biases the base of transistor 286, through resistors 368, 280. The collector current flowing through transistor 286, causes the equivalent impedance of FET 290 to decrease. The FET / resistor series combination of 500 K ohms 292 is shown in parallel in parallel with resistor 232 (Figure 7) with a threshold of 2 MO. Decrease the equivalent impedance (2 MO) by a factor of 5, corresponds to decrease • the sensitivity of the ground fault circuit interrupter '5 to 25 ma. As the impedance decreases, so does the sensitivity. In conssuensia, more current is taken to interrupt the ground fault circuit interrupter 12, i.e., the constant-state reference threshold at which the ground fault circuit interrupter will be interrupted.

For example, a constant leakage current of 1 ma causes the impedance of FET 290 to decrease, in order to raise to 6 ma (ie, the constant state threshold of 1 ma, plus 5 ma of fixed dynamic threshold) Leak level at which the ground fault circuit interrupter is interrupted. A leak in constant state of 5 ma will adjust the FET 290 to an equivalent impedance of 1.5 MO. The resulting impedance adjusts the sensitivity of the ground fault circuit interrupter to 10 ma (ie, the constant state threshold of 5 ma, plus the fixed dynamic threshold to 5 ma). The maximum equivalent impedance of the FET 290 will raise the threshold in steady state to 25 ma. In this way, any leakage above 30 mA will interrupt the ground fault circuit interrupter. In a similar way, a slowly decreasing leakage current changes the threshold in a constant state, on which 5 m will interrupt the ground fault circuit interrupter. A decreasing leakage current causes the output of the amplifier 349 to decrease, negatively polarizing the diode 352 in reverse. The accumulated load on the capacitor 360 is discharged to ground through the resistors 356, 358, haeta which reaches the new level set by the output of the amplifier 349. The output on the voltage across the sapacitor 360 causes a corresponding increase in the impedance of the FET 290, the result of the decreased current of the collector flowing through the transistor 286. This causes it to appear a higher voltage on the FET gate 290. This higher gate voltage raises the equivalent impedance of the FET 290. The higher resistance combined with the adjusted resistor 232, in parallel with the series combination of FET 290 and the resistor 292 , low threshold of cirsuite ground fault switch switch 12. As described above, the dynamic threshold of the cirsuite switch of f land 12 nunsa sambia from its previously adjusted level of 5 ma. In this way, if, for example, the constant state threshold has been raised from 0 ma to 10 ma, due to 10 ma of leakage current present in the alternating current power line, the device 10 will interrupt by 5 ma leakage current that rises rapidly, the type caused by humans. To achieve this, the ground fault circuit interrupter circuit 12 uses a transistor 366 to quickly discharge the capacitor 360 and the base of the transistor 286. This causes the equivalent impedance of the FET 290 to return back to its original sensitivity setting. 5 ma. A rapidly rising leakage current, of the type that humans may cause, causes the output of the amplifier 349 to rise rapidly, causing the current to charge the capacitor 362. The voltage across the resistor 364 rises is the voltage of the amplifier. capacitor in elevation, until it is sufficient to turn on the transceiver 366. Tractor 366 that turns on quickly, decreases the load on the base of transistor 286, turning it off, and also quickly unseats the 360 sapasitor. Another important feature of the smart switch device is ground fault circuit 10, is the capacity of the dietary device to constantly inspect the ground fault circuit interrupter system 12, to ensure proper operation in its task of protecting users against ground faults. To accomplish this task, a test circuit 14 is included, to perform a built-in test, to perform two independent self-test operations on the ground fault circuit interrupter, assuring the user's safety. A first self-test is performed once every hour, and verifies that the discharge coil 260 and the SCR 244 are working properly. A second test is performed once every two hours, and it verifies that the integrated circuit 228 of the ground fault cirsuite switch is working properly. With reference to Figures 9A, 9B, respectively, the first and second self-test circuits will now be described. Referring now to Figure 9A, a preferred embodiment of a first portion of the self-test circuit 14 will be described for implementation within the present invention. The first self-test portion is electrically connected to the ground fault circuit interrupter 12 inside which the coil 260 and the SCR 244 are tested, in conjunction with the bus signal 1HR_PULSE, produced by the timed signal generator 22. Consequently, SCR 244 is turned on by the SCR_GATE cersa at the end of the positive portion of the alternating current cycle, i.e. at approximately 170 degrees. The presence of any current flowing through SCR 244 is detected and identified by means of the SCR_CURRENT signal. If no current is detected, the alarm is activated and the relay switches 28, 30 are interrupted by the alternative activating element of the optocoupler 248 (described above). The LOAD-1 terminal is electrically connected to a first end of a resistor 372 and to a cathode end of a diode 370. The anode end of the diode 370 is electrically connected to the second end of the resistor 372, at an anode end of the capacitor 374, a a cathode end of a zener diode 376 and two inputs of a logic Nand circuit 378 as an echo signal of 170 degrees, 170_DEG. The signal 170_DEG is generated through the resistor 372 and the capacitor 374 during the half of the positive cycle, when the capacitor 374 charges through the resistor 372. The values are chosen in such a way that the gate entrance to the circuit 378 rises high enough to cause its output to go down to approximately 170 degrees within half of the positive cycle, generating the bar signal 170_DEG. The zener diode 376 simply prevents the input voltage from rising high enough to damage the gate inputs of the Nand circuit 378. The gate output of the 378 (170_DEG bar) gate is a normally high signal that goes low 170 degrees within the positive cycle half of the alternating current, and remains low until crossing zero. The signal 1HR_PULSE generated inside the timed signal generator 22 ee combines with the signal 170_DEG, inside a circuit Ñor 380 logiso, a sual output is provided to a base of a transistor 384. A collector of the transistor 384 is connected, through of the resistor 382, to Vcc and the emitter of the transistor is grounded through a retractor 386. In this way, the transistor 384 only turns on when both inputs to the gate 380 are low. As mentioned above, the 1HR_PULSE signal is approximately 75 meters long, loosening more than one cistern from the alternating sorptive energy. The sorptive flowing through transistor 384 produces a voltage across re-emitter 386, igniting the SCR for about 10 degrees and ending in the half-cycle of the alternating current. During the half negative phase, the diode 370 quickly discharges the capacitor 374 for the next positive half-circle. If the discharge coil 260 and SCR 244 are functioning properly, current will flow through these two components when the transistor 384 is turned on. It is at this point that the SCR__CURRENT signal, shown in Figure 7, will be in its maximum point. This signal is provided to a pair of inputs to a logical Nand 390 circuit, where it is inverted to generate the SCR_CURRENT bar signal, and to a cathode end of a zener diode 388. The bar signal SCR_CURRENT pre-sets a trigger circuit 392, causing the "Q" output of the trigger cir- cleum to rise immediately. The bar signals 170_DEG and 1HR_PULSE are inputs to the alternative logic circuit 394, an output of which is provided to the trigger circuits 392, 396. An output "Q" of the trigger circuit 392 is electrically connected, as an input D, to the trigger circus 396; the bar signal PWR_ON_RESET is provided as its "pre-set" input as well as an "adjust" input of the trigger circuit 392. Accordingly, the rising edge of the bar signal 170_DEG times the logic output of the cirsuite of trigger 392 within trigger circuit 396. Previously, upon firing, trigger circuit 392 is reset low and trigger circuit 396 is reset high. If the current flows through the SCR 244, then a high is entered into the trigger bus 396, and the output, bus SCR_FAIL, remains high. The alarm, therefore, is not activated. However, if no sorrier is detested, then a drop is made within trigger trigger 396, and the bar signal SCR_FAIL goes low, the alarm is triggered and optocoupler 248 interrupts relays 28, 30. Since the input When the trigger circuit 392 is blocked low, always a low is clocked from the Q output of the trigger circuit 392. In this way, in the absence of the adjusted beat previously derived from the current of the SCR 244, the Q output of the trigger circuit goes to a low, indicating a fault with SCR 244 and / or coil 260. Referring now to Figure 9B, a preferred embodiment of a second portion of self-test circuit 14 will be described. The signal 2HR_PULSE generated inside the timed signal generator 22 is provided at the input of the clock to a trigger circuit 410. The clock input is also electrically connected to a first end of the resistors 398, 498. A second or end of the resistor 398 is electrically connected to a battery of the NPN 400 traneer, one of which is connected to ground, and a collector of which provides an output path for the SCR_GATE signal. A second end of the resistor 408 is electrically connected to a gate of the N-channel of FET 406. A source of FET 406 is electrically consti- tuted to the terminal AC-2_OUT, a consumption of which is electrically connected to a cathode end of a diode 404 An anode end of the diode 404 is connected to the LOAD-1 terminal through a retractor 402. The signals GFCI_OUT and PWR_ON_RESET are provided as the "D" and "pre-fit" inputs to the trigger circuit 410, respectively. The second self test is preferably performed every two hours, and verifies the proper operation of the stopwatch 114 of the LM1851 and the ground fault circuit interrupter 12, using the signal 2HR_PULSE, produced by the timed signal generator 22. The active 2HR_PULSE signal to FET 406 to simultaneously simulate a ground fault, prevent the SCR 244 from catching fire, and detect the output of the ground fault cirsuite switch 12. The raised state of the 2HR_PULSE signal turns on the transistor 400, through the resistor 398 , blocking the gate of SCR 244 to ground, and activating FET channel N 406, through reefer 408, allowing current to flow during the positive half cycle from terminal LOAD-l to terminal AC-2_OUT, through of the resistor 402 and the diode 404, creating an imbalance in the current flowing through the magnetic core 312, 314. If the ground fault circuit interrupter 12 is working properly This will detect the imbalance created by the simulated ground fault and output a pulse on pin 1 (GFCI__0UT) of timer 228. The signal GFCI_OUT is input to trigger cir- cum 410, where an edge in elevation of the signal 2HR_PULSE of bar the time inside the trigger circuit, as its input "D". As a result, the "Q" output of the circuit, the bar signal GFCI_FAIL, remains high (the operation was appropriate). However, if the GFCI_OUT signal is low, the bar signal GFCI_FAIL goes low, astivating the alarm and interrupting the relay contacts 28, 30, through the optocoupler 248. The output "Q" of the trigger 410 is normally high, being adjusted previously high by means of the bar PWR_ON_RESET signal, on the initial application of the alternating current energy. The SCR is prevented from catching fire during the test by the blocking action of transistor 400. The base of SCR 244 is kept serrated to the ground potential, by transistor 244, preventing the SCR 244 from turning on while the test is in progress. . In other words, no response to the ground fault simulated by the test is used. It should be noted that, as defined in the preeent, a slowly rising leakage current is defined as that leakage current that is typically associated with certain talee artifacts such as washing machines, dishwashers, and so on. Leakage current rapidly changing is identified as such sambios in the sorriente that are indissociable from a ground fault, for example, more than 5 ma for an adjusted period of time. The embodiments of the present invention, described in the present specification, drawing and claim, are presented merely as examples of the present invention. Other modalidadee, formae, or modifications thereof easily eect to themselves, and are contemplated within the scope of the present invention.

Claims

CLAIMS 1. - A smart seventh circuit breaker, electrically connected between an alternating current source and a load, to interrupt an alternating current flow from the source to the load, upon detection of an interruption condition, comprising: This includes the phase and neutral side-line and load ports, where the line-side phase and neutral ports are electrically connected, respectively, to the phase and neutral terminals of the alternating current source, and the cirsuite switch element generates an interruption signal to interrupt the flow of alternating current to the detest of the interruption condition; a relay switch that includes a relay coil and phase and neutral contacts, wherein the line and load ends of the phase contact are electrically connected, respectively, between the load side phase port of the switching element and a switching terminal. phase of the load, the line and load ends of the neutral contact are electrically connected, respectively, between the load side neutral port of the switching element and a neutral terminal of the load, and the relay coil is electrically coupled between the ends Charge the fae and neutral contacts, to control the contact in response to the interruption signal; an open contact insorrested power line detector (OCMD) electrically connected to the line and load ends of one of the phase and neutral contacts, to detect an incorrect electrical laying condition, when the contacts are in an open condition; an incorrect power sampled conductor (CCMD) detector is located at the load end of the phase contact and the line and load ends of one of the neutral and fae contact, to detect an incorrect power line condition, when the contacts are in a closed state; a timed signal generator connected electrically to the open and closed contact insorresto electronic detectors, to generate timed signals to the system; a test circuit electrically coupled to the switch element and responsive to the timed signal generator, to regularly test the operability of the switch element; a sirsuito of alarm eléstrisamente responsive to each one of: the test circuit, the generator of timed signal, the detector of wrong electrical wiring of open contasto and the detector of incorrect electric wiring of closed contact, to communicate at least a D: a incorrect electrical contact condition of open contact, a condition of incorrect contact closure, an operational failure condition, and a need for an external test sonde; and a supply of energy connected elastically between the twill ends of the phase and neutral sontats, and to the clocked signal generator.
2. The intelligent circuit breaker system, defined in claim 1, is sarastered because the switch buster inspects a line current flowing from the source to the load, and a neutral current flowing from the load to the source, and generates the signal of interruption based on a difference detected between the line and neutral currents.
3. The intelligent cirsuite switch system, defined in claim 1, characterized in that it also includes an automatic gain control element, electrically coupled to the switch element, to provide an adjustment signal to the circuit breaker element, to vary a definition. of the interruption condition.
4. The seventh intelligent circuit breaker, defined in claim 3, sarasterized because the automatic gain control element detects and defines leakage current losses within the seventh, and automatically adjust the adjustment signal to compensate for them.
5. The intelligent cirsuite switch system, defined in claim 4, is sarasterized because the automatic ganglion sontrol element adjusts for slow-varying leakage current, up to 25 ma.
6. The intelligent circuit breaker system, defined in claim 4, characterized in that the interrupting signal interrupts the flow of alternating sorptive to the detest of a suction leakage current of minus 5 ma, which has been determined to have changed abruptly . 1 . - The intelligent cirsuite switch system, defined in claim 1, is sarasterized because it also includes an overvoltage suppressor electrically connected through the phase and neutral side-line ports of the switch element. 8. The seventh intelligent circuit breaker, defined in claim 7, characterized in that the surge suppressor includes a metal oxide varder. 9.- The intelligent switch system of cirsuito, defined in claim 1, is sarasterized because the switch element of sirsuito comprises a ground fault interrupter circuit. 10. - The intelligent circuit breaker, defined in claim 1, characterized in that the interruption signal causes the relay coil to interrupt the relay contacts to an open state. 11.- The intelligent cirsuite switch system, defined in claim 1, is sarasterized because the incorrect power line conditions arise from a detection of one of the phase and neutral terminals of the electrically connected alternating current source, respectively. to one of the load ends of the phase and neutral contactors. 12. The intelligent seven-bit sirswitch switch, defined in claim 1, characterized in that the alarm circuit includes a piezo-transducer transducer to generate, at least, an alarm signal depending on the freshness. 13.- The intelligent circuit breaker system, defined in claim 1, sanitized because the test circuit implements a self-test at least every 2 hours. 14. The intelligent circuit breaker, defined in claim 1, sarasterized because the alarm service indicates a need for a user to test the system, less than 30 days. 15. The intelligent switchwitch system of claim 14, characterized in that the alarm clock communicates regularly the need to test the system according to the need of the test indication, until the user tests the seventh, except during another hours apart. of the day. 16. A method for detecting ground faults on a load side of a switching circuit is electrically between an alternating current source and a load, so that alternating current flowing through the circuit is reliably interrupted on the detection of an interruption condition by means of the cirsuito, comprising the steps of: detecting a first quantity of alternating current flowing from the alternating current source to the load, using the switch sirsuito; detect a second amount of alternating current flowing from the load to the alternating current source, using the switch cirsuito; generating a difference signal indicative of a difference between the first and second quantities; compare the difference signal with a reference signal, which is proportional to a maximum alternating current flow difference, to define an interruption sonsion in response to it; interrupting the flow of alternating current on the occurrence of said condition; inspect the cirsuito and identify the alarm conditions that require the intervention of the user, to ensure reliable detection of ground fault; and generating an appropriate alarm signal to communicate to a user a need for that intervention. 17.- The method defined in claim 16, characterized in that the alarm conditions are determined in the occurrence of: a detection of the incorruptible electrical wiring of the switch sirsuito, a detest of a non-operative condition inside the switch circuit, and a detest of a time that requires user assistance when testing the operability of the circuit breaker. 18. The method defined in claim 16, characterized in that it also includes a step of communicating to the user an identification of the alarm condition. 19. The method defined in claim 16, characterized in that the somparation step is carried out in a comparator. 20. The method defined in claim 19, characterized in that it also includes a step of adjusting a sensitivity of the comparator, in accordance with a non-alarm condition of leakage current detection. 21. The method defined in claim 20, sarasterized because the step of adjusting a sensitivity of the somparador, includes a somparasión of a detested several sambio leakage leakage, determined during the somparasión step. 22. An intelligent circuit breaker electrically connected between an alternating current source and a load, to interrupt an alternating current flow from the source to the load, on the detection of an interruption condition, comprising: a circuit breaker circuit ground fault circuit, which is electrically placed between the load and the source, to interrupt the alternating current flowing to the load, upon the detection of the interruption condition, including the circuit breaker ground fault contacts switches, which they prevent the flow of alternating current when they are set to a high impedance state, and allow alternating current flow when adjusted to a low impedance state; an incorrect electrically powered power line detector to the switch sirsuito, to detest an incorrect power line condition in the intelligent circuit breaker; a test circuit electrically coupled to the switch sirsuite and to the test lead of the insorrested resistor, to test the operability of the circuit breaker; and an electrically responsive alarm circuit to the test circuit. 23. The intelligent circuit breaker as defined in claim 22, characterized in that the incorrect power line detector includes elements to detect the incorrect power line condition, when the contacts are set to one of the high and low impedance states. . 24. The cirsuite intelligent switch as defined in claim 22, characterized in that it also includes a timed signal generator, electrically connected to the insurmountable insterest resistor. 25. The intelligent circuit breaker as defined in claim 22, characterized in that it also includes a power supply connected electrically to a twill end side of the sontats to sonvert the alternating current to direct current, when the contacts are in a low impedance state. SUMMARY A smart sirsuite switch system is electrically connected between a source of alternating current and a twig to interrupt an alternating current flow from the source to the serge, on the loss of an interruption condition. A circuit breaker electrically connected to the phase and neutral terminals of the alternating current source defines the interruption condition. A relay snubber with a relay coil and fae and neutral contacts is included, so that the line and load ends of the faee contact are electrically connected, respectively, between the load side phase port of the switch element and a phase terminal of the load. The line and load ends of the neutral contact are electrically connected, respectively, between the neutral port of the circuit breaker and a neutral terminal of the load. The relay coil is electrically coupled between the load side of the phase and neutral contacts, to control the contacts in response to the interruption signal. An open sontasto insorrested power line (OCMD) detector is supplied to one of the phase and neutral contacts, to detect an insorresting resistor when the contacts are in an open state, and an incorrect power line detector. Closed contact (CCMD) is electrically connected to the power line detector ! incorrect contact open and one of the neutral and phase contacts, to detect an incorrect power line condition when the contacts are in a closed state. A timed signal generator generates timing signals to the system. A test siren, which is blasted through the switch element and the timed signal generator, tests the operability of the switch element. An alarm circuit is electrically responsive to the test circuit, to the timed signal generator, to the test lead of the insetresto open sontasto and to the detesting of the electric connection of the sontasto serrado, to communicate a condition of incorrect electrical contact with open contact, an incorrect electrical contact condition for closed contact, an operasional failure condition, and a need for an external test. A power supply is electrically connected between the load ends of the fae and neutral contacts, and the timed signal generator.