MXPA95004822A - Device for demodulating and decoding digital detelevision data transmitted by cable, satellite and terrestrial - Google Patents

Abstract

The present invention relates to a system for receiving a modulated signal from multiple types of transmission channels, the signal which is representative of compressed digital data encoded in one of a plurality of coding formats, and which presents one of a plurality of modulation formats, a method comprising the following steps of: selecting a modulation format for demodulation between encoding formats including QAM and PSK; demodulating said modulated signal according to the selected modulation format to produce a demodulated signal; an encoding format for decoding between the plurality of encoding formats, and decoding the demodulated signal according to the selected encoding format to produce a decoded and demodulated signal

Description

Apparatus for Oesmodular and Decode Digital Television Data Transmitted by Cable, Satellite and Terrestrial The invention relates to the field of digital signal processing apparatuses suitable for use in a multi-channel receiver, of digital television data transmitted by cable, satellite and terrestrial. The use of advance error correction is known in the art because it includes convolutional encoding in the transmission of coded data over a noisy channel from a transmitter to a receiver that includes a bifurcation metric computer for a convolutional decoding r based on an alqorithm of Viterbi. The Viterbi Algorithm is commonly used to decode a convolutionally coded sequence of bits transmitted through a noisy channel. At the center of the Viterbi algorithm, there is a series of repetitive r-compare-select operations which accept as input certain metrics (called ammeter metrics) calculated on each symbol received from the demodulator. For terrestrial, cable and satellite transmission of high-speed data signals, such calculations need to be performed at very high speeds. Additionally, in a modem / decoder operating through different channels with different (but related) coding schemes, the cost of calculating branch metrics becomes excessive in terms of query table memory or actual physical equipment to perform these calculations. In the case of a satellite transmission channel, it is customary to transmit some particular punctured code for quaternary phase shunt manipulation (QPSK) known to the convolutional receiver decoder. In the case of a terrestrial or cable transmission channel, a particular pragmatic code "trellis" (such as quadrature amplitude modulation code (QAM), phase amplitude modulation code (PAM) or derivation manipulation code) of phase (PSK) known by the convolutional decoder of the receiver For example, the prior art discloses the use of a pragmatic code of "trellis", as a practical code for high definition television (HDTV) QAM transmission. in the past, the receiver including an amidation metric computer for a convolutional decoder based on the Viterbi algorithm was typically designed to operate with only a predetermined type of convolutional code, however, it is very likely that multi-channel digital television receivers will enter in the mass production market in the near future and, over time, replace the television receivers to Current broadcasting satellite transmissions are already available, in addition to cable and terrestrial transmission. Accordingly, it is desirable that the convolutional decoders of such multi-channel digital television receivers respond selectively to the type of code (either perforated or pragmatic "trellis," as the case may be) and the type of modulation (PSK including both QPSK and 8-PSK, PAM or QAM, as the case may be) of the channel that is currently being received by the multi-channel digital television receiver. Additionally, mass-produced television receivers should be designed considering a reduction in cost and complexity. The inventor has recognized that a single signal processing device can advantageously accommodate multiple demodulation and decoding functions within the context of a digital television signal processing system, for example. In accordance with the principles of the invention, the disclosed digital signal processing apparatus provides decoding and demodulation elements incorporating different types of demodulation and decoding functions. As a result, a single signal processing network can demodulate and decode signals of different signal format, such as, for example, terrestrial, cable and satellite signals. In a system for receiving a modulated video signal, from multiple types of transmission channels, an apparatus in accordance with the principles of the present invention provides a demodulated and decoded output signal. The received video signal is representative of compressed digital video information, such as television picture information, and is encoded in a format of a plurality of encoding formats. The received video signal is also modulated in a format of a plurality of modulation formats. The apparatus includes a demodulator to selectively demodulate the received modulated video signal in a format of a plurality of modulation formats, to provide a demodulated signal. The apparatus also includes a decoding to selectively decode the demodulated signal, encoded in a format of a plurality of encoding formats. In accordance with a feature of the invention, the demodulator selectively demodulates the video signal modulated by Pulse Amplitude Modulation (PAM), Quadrature Amplitude Modulation (QAM) or Phase Derivation Manipulation (PSK). In accordance with another characteristic of the invention, the selective decryption r decodes the demodulated signal, encoded in perforated code format or "trellis". In a further feature of the invention, the selective decoding decodes the demodulated signal with a selected code rate of a plurality of code rates. Illustratively, the decoder of the present invention is a convolutional decoder including a ram metric computer and a Viterbi decoder. In a first embodiment, this amometrics metric computer can be selectively programmed to operate with any of the encoded-QPSK-pe and a plurality of Q and I signal entries encoded in pragmatic trellis of PAM or QAM major alphabet. In a second mode, this ammeter metering computer can additionally be selectively programmed to also operate with Q and I signal inputs encoded in 8-PSK "trellis". Illusively, the branch metric computer has 2x-bit I and 2-bit Q signal inputs, and comprises (1) a RAM that has an effective depth of 2X storage locations and a sufficient amplitude to store data inputs. amplitude of 4-m bits of, at least one pre-filled look-up table defining I and one defining Q, at each storage location, (2) a group of at least four adders, and (3) means to anticipate the respective sum outputs of four group adders to the Viterbi decoder of the convolutional decoder.

In the second embodiment, the amplitude of the RAM is sufficient to store the amplitude inputs of 4-m bits of two pre-loaded query tables defining I and defining Q, at each storage location; the group of at least four adders comprises eight adders organized into first and second group of four adders; and the means for anticipating the respective sum outputs of four adders of the Viterbi decoder of the convolutional decoder, includes four comparators, with each of them anticipating the Viterbi decoder with the smallest sum output of the corresponding adders of the first and second groups. Figure 1 illustrates the different types of transmission channels, which can be received by a multichannel compressed digital television receiver, transmitted from a compressed anticipated error correction digital television transmitter; Figure 2 is a block diagram showing the relationship between the convolutional decoder, the demodulator applying an input to the decoder, and a microcontroller interface to the decoder of the digital television receiver 1 -comprised from multiple channels of Figure 1; Figure 3 is a block diagram of the structural elements of the convolutional decoder shown in Figure 2, which shows the coupling of the interface of the microcontroller of Figure 2, to the structural elements of the convolutional decoder; Figure 3a is a functional diagram of the operative elements of the convolutional decoder shown in Fiqura 3, when programmed by the microcontroller interface of Figure 3, to operate in a "trellis" p-code decoding mode; Figure A is a diaqra of blocks of the structural elements of the ram metric computer shown in Figure 3; and Figure A a, illustrates the functional organization of the structural elements of the branch metric computer shown in Figure 4. As shown in Figure 1, the multichannel digital-compressed television receiver 100 is capable of selectively receiving digitally encoded television data, transmitted on each channel of a plurality of different channels. This plurality of channels includes the satellite transmission channel 102, which transmits digitally encoded television data from the pre-corrected error television transmitter 104; the terrestrial transmission channel 106, which transmits digitally encoded television data from the error-corrected television transmitter 108; and the cable transmission channel 110, which transmits digitally encoded television data from the previously corrected error television transmitter 112. As is known in the art, early correction of errors in the transmitter commonly comprises convolutional packet coding of successively transmitted symbols of digital-compressed television data already encoded. As is further known in the art, while perforated codes based on QPSK are commonly used for the transmission of convolutional encoded data in a satellite channel, the pragmatic trellis codes of higher alphabet n / nt-1 (i.e. , 8, 16, 32, 64, 128 and 256), are generally used for transmission based on PAM, PSK or QAM of convolutional encoded data, in terrestrial or cable channels. Accordingly, the multi-channel receiver 100 is required to incorporate a convolutional decoder that is capable of decoding any particular code, for example based on QSPK or PAM, PSK or QAM of pragmatic "trellis" codes n / n + 1 of greater alphabet, depending on the channel selected from the multiple channels that are being received. More specifically, the multi-channel receiver 100, comprises a digital processing apparatus which, as shown in Fiqura 2, includes the receiver convolutional decoding 200, and the receiver demodulator 202 which, as is known in the art, applies each of a series of symbol packages convolutionally encoded, successively received as the signal input data to the receiver copolymer decoder 200. Each packet of symbols successively received from these data, defines a point in the plane of the input phase (I), the quadrature phase (Q ). The digital processing apparatus of the multichannel receiver 100 further comprises a microcontroller that includes a microcontroller interface 204 for applying a control input to the receiver convolutional decoder 200. The relationship between the structural elements of the receiver convolutional decoder 200 employed by the present invention, and the control of these elements by the interface of the external microcontroller 204, is shown in the Fiqura 3. As shown in Figure 3, the structural elements of the receiver convolutional decoder 200, include synchronization circuits 300, dummy data inserter 302, branch metric computer 304, Viterbi decoder 306, convolutional encoder 308, "trellis" 310 scrambler, delay logic 312, synchronization monitor 314 and selection means 316. The microcontroller interface 204, provides a list of specifications to the structural elements urals mentioned above, which configures the operation of the convolutional encoder, either as a decoder for perforated codes or, alternatively, as a decoder for "trellis" codes. Figures 3a and 3b, respectively, show the manner in which the elements of the convolutional encoder shown in the Fiqura 3 are, (1) configured for operation as a decoder for perforated codes or (2) configured for operation as a decoder for codes "trellis" The output data of the demodulator 202 is applied as input data Q, 1 to the synchronization circuits 300. For illustrative purposes, it is assumed that each of the data Q and I is defined by 6 bits (ie the data). of input are applied on a total of 12 parallel input conductors). This allows gue. each of the different points 64x64 = 4096, in the Q plane, I is defined chickens components of 6 ~ bits I and 6-bits Q, of the input data of 12-bits. The synchronization circuits 300 also receive clock inputs and clock enable (Clk Enb) thereto. In addition, the synchronization circuits 300, receive control data from the interface of the microcontroller 204, and supply data thereto, and is directly coupled to the synchronization monitor 314. Each of the elements 302, 304, 306, 308 and 310 , has control data applied to them from the interface of the microcontroller 204. Additionally, although not shown in Figure 3, the clock is applied to these elements. The suitably synchronized data Q and I are anticipated from the sync circuits 300, through the dummy data inserter 302 to the branch metric computer 304, in response to data entry clock enable (DICE) and enabling of data output clock (DOCE). Additionally, the properly tuned Q and I data is anticipated through the delay logic 312 to the "trellis" dealloader 310 and the synchronization monitor 314. The dummy data inserter 302, is used primarily for perforated codes and is responsible for the insertion of fictitious data corresponding to a deletion map specified for said perforated codes. For "trellis" codes, the dummy data inserter 302 simply passes through its input data to its output. The code selection and the corresponding deletion map is passed to the fictitious data inserter 302, via the interface of the microcontroller 204. The fictitious data inserter 302, times the data output with an internal clock at a speed that depends on the coding scheme used. Since the output and input data rates are different (for perforated codes), the data input clock enable (DICE) signals and the data output clock enable (DOCE) signals are unique. The DICE signal is the clock enable signal "of the receiver demodulator 202, while the DOCE signal is generated internally in the dummy data inserter 302 (and is derived from the clock signal.) Specifically, the fictitious data inserter 302, consists of a FIFO storage mechanism, a write clock to write the soft decision samples at suitable locations, and a read clock (which operates at a faster rate than the write clock, and depends on the punched coding). used for its clock speed) to read the data for metric branch calculations The dummy samples are also inserted into the appropriate locations before being read The rammed metric computer 306, (the details of which are discussed later in Figs. and 4a) derives 4 separate 5-bit outputs in response to each of the successively received symbol pads These 4 separate 5-bit outputs and the signal TWELVE of the rammed metric computer 306, are applied as inputs to the Viterbi decoder 306. The Viterbi decoder 306, which has a speed R = l / 2, compression length k = 7 decoded, performs the Viterbi alqorithm for perforated codes and "trellis", wherein the 5-bit metric inputs of the branch metric computer 306, are used to update the states and make bit decisions. The Viterbi 306 decoder uses means of adding-comparing r-selection (ACS), path metric storage means, and the emory for the trajectories sob evivientes in each level in the "trellis". In addition, the Viterbi 306 decoder is also responsible for metric renormalizations, to avoid accumulation and overflow of accumulated metrics. A 1-bit output of the decoded Viterbi 306 is applied as an input to the convolutional encoder 308. For the perforated codes and "trellis", the convolutional encoder 308 serves to regenerate the best estimates of the two transmitted of the velocity of 1/2 built-in code The output of the encoder 308 is also applied to a synchronization monitor 314, for use in the verification of the state of punctuated code sync. Additionally, the 1-bit output of the Viterbi decoded 306 is applied as an input to the selection means 316. The 2-bit output of the convolutional encoder 308 is applied to the "trellis" 310 dealloader, which is responsible to make symbol decisions, for the mode of operation coded in "trellis", shown in Figure 3b. In the operation mode coded in "trellis", the "trellis" scrambler 310, uses the 2-bit output of the convolutional coder 308, for selection of subgroups together with the symbol data received Q and I delayed, anticipated to the same through the logic of delay 312, to make these decisions of symbols. A 6-bit output of the "trellis" scrambler 310 is output as an input to both the on-line monitor 314 and the selection means 316. The delay logic 312 considers the delay introduced by the Viterbi decoder 306 / decoder 308 and the associated circuits, and synchronizes the data stream to the encoder output with the received symbol current. The control input through the interface of the microcontroller 204, selects one of the 4 possible path memory lengths of the Viterbi 306 decoder, which is also used to appropriately select the delay time in the delay logic 312. The sync monitor 314, which is coupled to the synchronization circuit 300, the output of the "trellis" unlayer 310, the encoder 308 , the output of the delay logic 312, and the interface of the microcontroller 204, uses the metric information of branches in conjunction with a specification of the interphase's observation interval. mic or controller 204, to decide the synchronization state. It also provides information to the synchronization circuits 300 for optional automatic synchronization. In an automatic synchronization operation mode, the internal synchronization circuits are used to perform the synchronization function. Alternatively, synchronization could be done from external circuits. The synchronization monitor 314 is also used to provide a signal to the demodulator to resolve phase ambiguities. This signal is used solely for the purpose of considering the phase ambiguities in the receiver demodulator 202. Additionally, the synchronization monitor 314 provides a demodulated synchronization signal for use by components downstream of the receiver 100. The selection means 316, which receive the 1-bit output of the decoded 306, and the 6-bit output of the "trellis" 310 dealloader, applied as inputs to them, anticipate all these 7 bits to their output when the convolutional decoder is operating in its code mode "trellis" and anticipates only 1 bit of the output of the Viterbi decoder 306 at its output when the convolutional deecodi fi ed r is operating in its perforated code mode. These output data, together with a DOCE signal and a clock, are supplied from the selection means 316 for use with co-downstream of the receiver 100. The structure of the ram metric computer 304 comprises the random access memory (RAM) 400, adders 402 I and Q of memory banks 0 and 1, and comparators 404 I and Q of memory banks 0 and 1. The RAM 400 can also be a read-only memory. The RAM 400 is pre-loaded during an initialization phase with pre-calculated, programmable query tables Q and I of the microcontroller interface 204, applied as a control input to it. In response to the Q and I signals, anticipated from the fictitious data inserter 302 (which punches punched coded symbols based on QPSK) to the RAM 400 as signal inputs thereto, the selected inputs of the Q and I inputs of these Query tables are read as outputs of RAM 400 and applied as inputs to adders 402 I and Q of memory banks 0 and 1 ,. The output of adders 402 I and Q of memory banks 0 and 1 ,, is applied as an input to comparators 404 I and Q of memory banks 0 and 1, and the output of comparators 404 I and Q of memory banks 0 and 1, is anticipated as an input to the Viterbi decoder 306. More specifically, as shown functionally in Figure 4a, the RAM 400 is organized in a metric memory bank 0, and a metric memory bank 1 The memory bank 0 is made up of a first pair of subgroups by purchasing first subgroup I 00, and first subgroup Q 00; a second pair of subgroups comprising second subgroup I 01, and second subgroup Q 01; a third pair of subgroups complying third subgroup I 11, and third subgroup Q 11; and a fourth pair of subgroups comprising fourth subgroup I 10, and fourth subgroup Q 10. Memory bank 1, is also formed of 4 similar pairs of subgroups Q and I, thus providing a total of 8 pairs of subgroups Q and I for RAM 400. Each of the 8 sub-groups I receives the signal input I to RAM 400, and each of the 8 sub-groups Q receives the signal input Q to RAM 400. In general, each of the signal inputs Q and I, is an x-bite signal (specifically aeumidated in the illustrative example of Figure 3, as a 6-bit signal). Each of the 8 subgroups I derives an m-bit signal output (illustratively assumed as a 4-bit signal output) and each of the 8 subgroups Q derives a signal output of m-b its. All 8 signal outputs separated from Q and I m-bits of RAM 400, are anticipated as inputs to the respective adders of adders 402 I and Q of memory banks 0 and 1. Specifically, the first output outputs pair of sub-groups of bank 0 are applied as first and second inputs to adder 402-1; the two outputs of the second pair of subgroups of bank 0, are applied as first and second inputs to adder 402-2; the two outputs of the third pair of subgroups of bank 0, are applied as first and second inputs to adder 402-3, the two outputs of the fourth pair of subgroups of bank 0, are applied as first and second inputs to adder 402-4; the two outputs of the first pair of subgroups of bank 1 are applied as first and second inputs to adder 402-5; the two outputs of the second pair of subgroups of bank 1 are applied as first and second inputs to adder 402-6; the two outputs of the third pair of subgroups of bank 1 are applied as first and second inputs to adder 402-7; and the two outputs of the fourth pair of sub-groups of the bank 1, are applied as co or first and second inputs to the adder 402-8. An output signal separated from (m-t-l) -bits (ie, 5-bit signal in the assumed case) is derived from each of these 8 adders. All 8 output signals separated from (m + l) ~ bits of the adders are anticipated as inputs to the respective comparator comparators 404 I and Q of memory banks 0 and 1. Specifically, the outputs of the adders 40-1 and 402-5 are applied as first and second inputs to the comparator 404-1, the outputs of the adders 402-2 and 402-6 are applied as first and second inputs to the comparator 404-2, the outputs of the adders 402-3 and 402-7 are applied as first and second inputs to the comparator 404-3, and the outputs of the eminators 402-4 and 402-8 are applied as the first and second inputs to the comparator 404-4. Each of these comparators paes to its output the lower-valued value of its two inputs (m + l) -bits. The respective outputs of the 4 comparators constitute the metric computer output of branches 304 (ie, four 5-bit outputs in the assumed case), which are applied as inputs to the Viterbi decoder 306. Structurally, the RAM 400 is of a fixed bit storage size, which has an effective depth of 2X storage locations (i.e., corresponding to locations 1 through 64 in the assumed example, where x = 6). Each of the I and Q signal inputs to bank 0, and each of the I and Q signal inputs to bank 1 of RAM 400, has a separate look-up table associated therewith. The width of the RAM 400 is sufficient to store four pre-computed query tables with a width of 4m-bits (m = 4 in the assumed example), each of which is made of 2X inputs, which have been supplied to them through the control input of query table I and Q proqramable. Thus, the bit storage size of the RAM 400 is (2X) (4) (4m) or, in the supposed case, a bit storage size of 4096 bits. In the case of implementing a perforated code based on QPSK, a simple technique is to pass the maximum values I and Q and store the perforated metrics in appropriate locations in the query tables. This requires a possible trimming of the actual I and Q data, but can be handled at the front end of the decoder 200. In addition, the look-up tables can be programmed to allow a desired maximum branching metric value, disregarding certain input data I and Q less important. As discussed above, the branch metric computer 304 is a component of the convolutional decoder based on the Viterbi 200 alqorithm, which is used to decode the drilled codes based on QPSK for satellite modem operation, over a noisy channel and pragmatic trellis codes n / n + 1 speed based on a larger alphabet (16, 32, 64, 128 and 256 PAM, QAM or 8-PSK), for cable or terrestrial operation over a noisy channel. As it is known, due to the noise of the channel, the location point of a demodulated symbol received in the plane I, Q, will be displaced from its location point transmitted in the plane I, Q. The location point of each demodulated symbol received successively in the I, Q plane, is defined with a resolution of 2 (that is, 64 x 64 = 4096 in the assumed example), by the I and Q signal inputs for RAM 400 The important fact to note about RAM 400 is that its memory requirement is independent of the size of the alphabet. The 4 m-bit entries (4-bits in the presumed case) of the repecting reference tables I and Q of the bank 0, corresponding to a demodulated symbol currently received, define the respective I and Q components of the respective distance in the plane I, Q, of the location points of each of the A constellation subgroups of specified valid symbols surrounding the location points of the demodulated symbol currently received, from the location point of this currently received modulated symbol. In the QPSK case, (in which each subgroup location point defines only a simple symbol location point) and in the cases of QAM 0 PMA of the major alphabet (in which each subgroup location point corresponds to the locations) of a subgroup of 1/4 of the symbols in that alphabet necessary for the Viterbi decoder 206, with the "trellis" 310 scrambler selecting the correct point within the subgroup based on received, delayed, applied data), a simple component I and a simple Q component are sufficient to define the four subgroups unambiguously. Therefore, in these cases only bank 0 of RAM 400 is required. However, in the case of 8-PSK, a simple component I and a single component Q used independently are insufficient to define four symbol subgroups unambiguously . Therefore, in the case of 8-PSK, bank 0 is used to define location points of 0 °, 90 °, 180 °, 270 °, and bank 1 (which operates in a manner similar to that from bank 0 described above), is used to define locations of 45 °, 135", 225", 315 °. The comparators 404-1 to 404-4, which employ data derived from both banks 0 and 1 of the RAM 400, are used to resolve this ambiguity in a manner described below. The emersors 402-1 to 402-8 use the distance components I and Q to read the valid constellation location points of the RAM 400, to calculate the so-called Manhattan distance (I + Q), defined by each of the 8 subgroups. The Manhattan distance assignment is not the true Euclidean distance (I 'Q2) 1 2 but a distance measurement that considers points near the I, Q plane more importantly than the points in the I, Q plane furthest from the plane. received symbol location point. The Manhattan distance metric uses the sum of the differences between the I and Q coordinates of two points in the two-dimensional space I, Q Eeta distance measurement is monotonous with distance, but weights points in different ways depending on its position with respect to the point to which the distance is being calculated. However, because the use of the Manhattan distance metric makes the operations at the I and Q coordinates decoupled and independent, the memory requirements are drastically reduced to store the possible distances from any received location point. for a valid constellation location point. Each of the comparators 404-1 to 404-4 are designed to pass the smallest of the two metrics applied from bank 0 and bank 1, as inputs to them. Thus, in the case of a code based on 8-PSK, each of the comparators 404-1 to 404-4 will derive as an output either from the metric input of bank 0 or bank 1, depending on which is more little. However, in the case of codes based on QPSK, PAM or QAM, the query tables I and Q stored in bank 1 of RAM 400 are programmed to be filled with metrics of maximum values, so that they are effectively inactive, and therefore, each of the comparators 404-1 to 404-4 passes the selected metric out of bank 0 of RAM 400. In a multi-channel receiver not designed to receive a code based on 8-PSK, it can be eliminate both comparator objects and memory bank 1 from RAM 400 (thereby reducing the memory storage capacity required of RAM 400 by half). Although the convolutional decoder described herein is primarily for use in a multi-channel television receiver, to receive digital television data compressed in pragmatic "trellis" or encoded -profiles, there is no it is intended that the type of encoded data capable of being decoded by the convolutional decoding described, be limited only to television data, but that it may be employed for any other type of encoded data capable of being decoded by the convolutional decoder described. In addition to being suitable for use in a cable, satellite and terrestrial television data receiver as mentioned above, the described decoder apparatus is also suitable for use in other applications including fiber optic transmission, direct and telephone microwave.

Claims (1)

CLAIMS 1. In a system suitable for receiving a modulated video signal, such as a television signal, from multiple type transmission channels, the video signal being representative of compressed digital video information encoded in one of a plurality of formats of coding, and displaying one of a plurality of modulation formats; the apparatus comprises: a demodulator for selectively demodulating the modulated video signal in an appropriate manner, for a selected format of said plurality of modulation formats, to produce a demodulated output signal; and a decoder for selectively encoding said demodulated signal in a manner appropriate to a selected format, of said plurality of encoding formats, to produce a decoded and demodulated signal. The apparatus according to claim 1, wherein each format of said plurality of encoding formats uses a code rate selected from a plurality of different code rates. 3. The apparatus according to claim 1, wherein the deecodi fi ed r and the demodulator operate with variable clock speeds. 4. The apparatus according to claim 1, wherein said plurality of modulation formats includes PAM modulation. 5. The apparatus according to claim 1, wherein said plurality of modulation formats includes QPSK modulation. The apparatus according to claim 1, wherein said plurality of modulation formats includes QAM modulation. The apparatus according to claim 1, wherein the decoder is a convolutional decoder for a plurality of convolutionally coded symbol packets, applied as diqital input signals of quadrature phase (Q) and input phase (I). ) to them from said demodulator, wherein said convolutional decoder includes a ram metric computer and a Viterbi decoder; and wherein said branch metric computer comprises: a memory having an effective depth of storage locations 2X, where x is a given first integer greater than one, each location of the container having a sufficient effective width to store an entry of, at least, a look-up table that defines I and an entry of, at least, a look-up table that defines Q, where cad one of the entries of a look-up table that defines I and a look-up table which defines Q, consist of a group of first, second, third and fourth m-bite metric values, where m is a given second integer greater than one, the memory including a control input to precark such 2X storage locations with, at least, a look-up table defining I and, at least, a look-up table defining Q, and 2x-bit Q and 2x-bit I signal inputs, to read the cited query table that define I, stored in the u storage location defined by the value of a 2x-bit signal currently applied to the 2x-bite I signal input, and the said query table entry that defines Q, stored in the storage location defined by the value of a 2x-bit signal currently applied to said signal input Q of 2x-its; a group of adders that include a first adder to add the first m-bit metric value of the reading of the query table entry defining I, to the first m-bit metric value of the query table reading which defines Q, to derive a summation output (m + l) - bits; a second adder to add the second metric value of m-bits from the reading of a query table entry defining I, to the second m-bit metric value of the reading of a look-up table defining Q, to derive a exit from euma (mt-1) -bi te; a third eumator for adding the third metric value of m-bits from the reading of a query table entry defining I to the third m-bit metric value of the reading of a look-up table defining Q, for drift-one sum output (m + l) ~ bits; and a fourth adder to add the fourth metric value of -bit from the reading of a query table entry that defines I, to the fourth m-bit metric value of the reading of a lookup table that defines Q, to derive a sum output (m + 1) -bi ts; and means to anticipate the respective output of euma of the four adders of said group to the aforementioned Viterbi decoder. 8. The convolutional decoder defined in claim 7, wherein x = 6 and m = 4. 9. The convolutional decoder defined in claim 7, wherein said convolutional decoder includes digital processing means capable of selectively decoding coded-punched QPSK symbol packets and a plurality of pragmatic "trellis" encoded symbol packets. / n + 1 QAM and PAM; and an external microcontroller having an interface with the convolutional decoder, for applying programmable I and Q look-up tables, for said control output of the ram metric computer, which are precalculated according to the selected code to be decoded.

1 . The convolutional decoder defined in claim 9, wherein, under the control of said microcomputer interface, said convolutional decoder is configured to be selective in order to be in either a decoded code decoding mode or in a decoding mode of pragmatic "trellis" code; and wherein said digital processing means include: fictitious data insertion means, which operate only when the convolutional decoder is in its punched code decoding mode, to suppress the perforations of the I and Q input signals applied to said convolutional decoder , before they are applied to the 2x-bit Q and 2x-bit Q signal inputs, of the memory of the ram metric computer; and scrambling means is "trellis" in response to a recoded output from the Viterbi decoder and the I and Q input signals applied to said convolutional decoder that have been delayed, the "trellis" disabling means being operated only when the decoder convolutional. it is in its pragmatic "trellis" code decoding mode. 11. In a system for receiving a modulated signal from multiple types of transmission channels, said signal being compressed digital data encoded in one of a plurality of encoding pages and exhibiting one of a plurality of modulation formats, said multiple types of transmission channels including at least two channels of between terrestrial, cable and satellite transmission channels; said processing apparatus comprises: a demodulator for selectively demodulating the modulated signal in a manner appropriate for a selected format of the modulation formats, including PAM, QAM and PSK, to produce a demodulated signal; and a decoder for electively decoding said demodulated signal in a form appropriate to a selected format of the encoding formats, including encoded "trellis" and punched-out code formats, to produce a decoded and demodulated signal.