MXPA00000171A - 2.048 mhz clock converter to line signal at 2.048 mbit/s - Google Patents

Abstract

The clock converter from 2.048 MHz to a line signal at 2.048 Mbit/s is a unit meant to generate a PCM signal frame at 2.048 Mbit/s from a 2.048 MHz input clock. The PCM frame signal with Cyclic Redundancy Code (CRC) created by this unit, although it does not carry data traffic, does carry information on the phase of the input clock. It is provided with eight data outputs synchronised in phase with the 2.048 MHz input clock. The input interface as well as the eight PCM output frames comply with recommendations G.703, G.704 and G.706 of the ITU-T. In addition, it is provided with an alarm signal which is activated in the event that the 2.048 MHz clock signal disappears from the input of the converter.

Description

CLOCK CONVERTER FROM 2.048 MHz TO LINE SIGNAL AT 2.048 Mbit / s DESCRIPTION OF THE INVENTION The present invention relates to a clock converter of 2048 MHz to line signal at 2048 Mbit / s, which provides essential features of novelty and notable advantages with respect to known means and used for similar purposes in the current state of the art. More specifically, the present invention consists of a converter with eight data outputs with a PCM frame at a speed of 2,048 Mbit / s, which are hooked in phase to an input clock of 2,048 MHz, all of which comply with the recommendations of the International Telecommunication Union ITU-T G.703, G.704 and G.706. The present invention has its application in the field of telecommunications and more specifically in the synchronization of switching centers and mobile telephony.

BACKGROUND OF THE INVENTION When the transmission networks belonged to the plesiochronous digital hierarchy, the synchronism reference signals for the switching and mobile telephony exchanges were obtained from the frames of the tributary signals transported at a speed of 2,048 Mbit / s.

With the implementation of the synchronous digital hierarchy in the transmission network, it is necessary to synchronize the equipment of the transmission networks. The synchronization of these equipment is done starting from a master clock of 2.048 MHz, which is the reference for the entire network, and a transport network responsible for carrying the reference signal to all nodes in the network. While the transport network was plesióc / ona the switching and mobile telephony centrals obtained the reference of the sicronismo of the data frames, PCM signals of 2.048 Mbit / s, that reached them through the signals of the tributaries of entrance to the central. With the new situation produced in the architecture of the network due to the deployment of the synchronous transport network, in which the synchronism reference signal can not travel in the tributaries, as it did in the plesiochronous network, but it does so in the line signals and, therefore, the synchronism references are clocks and not data frames, it is necessary to use an Mbit / s for the synchronization of the switching and mobile telephone exchanges. In the current state of the art, some similar equipment is known that performs the aforementioned functionality, but is only valid for synchronizing certain very specific equipment, and also only synchronizes one device per card. The present invention provides the remarkable advantages of being able to synchronize any electronic equipment, and up to a maximum number of eight simultaneously.

The clock converter from 2.048 MHz to 2.048 Mbit / s line signal, is a device that generates eight output signals with a PCM frame structure at a speed of 2.048 Mbit / s, starting from an external input clock. 2048 MHz. Both the input and the output interfaces comply at all times with ITU-T Recommendations G.703, G.704 and G.706 of the International Telecommunication Union (ITU). In addition, the converter provides information on the status of the input clock by means of an alarm that indicates whether this clock is present in the input of the same or not. The present invention is constituted by three large blocks: an input receiver, a frame generator and an output stage. The input receiver module is responsible for adapting the impedance of the input coaxial cable to the input impedance of the converter equipment, and adapting the level of the line signal received at the input of the converter to the input levels acceptable by the generator. plot. For this it consists of an impedance matching network and a signal level converter. The frame generator is responsible for creating a PCM frame with a Cyclic Redundancy Code (CRC) in which the existing traffic in the data channels is zero logical level, and to use the external clock received at the input as a clock source to generate the output frame. For this it consists of a hierarchy frame generator of 2,048 Mbit / s.

The output stage has as functions to generate eight output frame signals according to the recommendations G.704 and G.706 of the UITT-T, adapt the output impedance of the equipment to that of the output coaxial cable and generate a signal alarm in case the entry clock disappears. Therefore, it is constituted by a converter of the internal data signals, a line signal, a transformer for the impedance adaptation of the equipment output to the impedance of the line to which it is connected and an alarm circuit that acts in case the external input clock in the module disappears.

BRIEF DESCRIPTION OF THE DRAWINGS Other features and advantages of the invention will become apparent from the following detailed description of a preferred embodiment of the invention, taken as an illustrative and non-limiting example with reference to the accompanying drawings, in which: Figure 1 represents a block diagram of the clock converter from 2.048 MHz to the line signal of 2.048 Mbit / s according to the invention.

DETAILED DESCRIPTION OF THE INVENTION To carry out the detailed description of the preferred embodiment of the invention, permanent reference will be made to the figures of the drawings, in which figure 1, or single figure, the detailed block diagram of the parts of which the clock converter from 2.048 MHz to line signal of 2.048 MHz input, following the recommendations G.703 (Physical and electrical characteristics of the interfaces of the digital hierarchies), G.704 (Synchronous frame structures used in the hierarchical levels of 1,544, 6,312, 2,048, 8,448 and 44,736 Mbit / s) and G.706 (Frame alignment procedures and Cyclic Redundancy Code (CRC) relating to the basic frame structures defined in recommendation G.704) of the International Union of Telecommunications (ITU). It also provides information about the status of the watch has disappeared. The operation of the converter is described below: The input receiver (2) receives the clock signal (1) from the external input source, adapts the impedance of the line signal to the input and at the same time transforms the clock levels input to adapt them to acceptable values by the next circuit, which is the frame generator (4). The frame generator (4) creates an empty frame (5) with structure PCM plus CRC using phase (3) of the input clock and according to ITU-T G.704 and G.706 recommendations. The frame signal (5) is brought to the input of eight output stages (6-13) that provide the logical and electrical output levels (14-21) respectively, according to ITU-T Recommendation G.703 and which are necessary to connect to the computers to be synchronized. The output stages also provide an alarm signal (22) if the clock (1) disappears from the input of the equipment, this alarm signal is transformed into a light signal (24) indicating failure through the adapter (23) .

Claims (5)

NOVELTY OF THE INVENTION CLAIMS

1. - Clock converter from 2.048 MHz to line signal to 2.048 Mbit / s, destined to the synchronization of switching and mobile telephone exchanges, which is characterized by the fact that it generates several data output frames with a PCM signal structure at 2,048 Mbit / s from a clock (1) of 2,048 MHz of input to a receiver (2), whose output is connected to a frame generator (4), which is brought to the input of the output stages (6-13) intended to be connected to the equipment that requires synchronization. 2.- Clock converter from 2.048 MHz to line signal at 2.048 Mbit / s, according to claim 1, characterized in that the receiver (2) of input of the clock signal (1) of 2.048 MHz is entrusted of adapting the impedance of the input coaxial cable to the input impedance of the equipment, and of converting the level of the received line signal (1) to the acceptable input levels by the built-in frame generator (4). 3.- Clock converter from 2.048 MHz to line signal at 2.048 Mbit / s, according to claim 1, characterized in that the frame generator (4) is responsible for creating a frame (5) with PCM structure with CRC (Cyclic Redundancy Code) for correction of errors, at its output using as reference the phase (3) of the input clock and according to the recommendations ITU-T G.704 and G.704 of the International Telecommunication Union. 4.- Clock converter from 2.048 MHz to line signal at 2.048 Mbit / s, according to claim 1, characterized in that in the output stages (6-13), by means of a converter of the internal data signals At the line signal, the logical and electrical output levels are obtained in accordance with Recommendation ITU-T G.703, to connect to equipment that requires synchronization, and also through a transformer adapts the output impedances of the equipment to that of the coaxial output cable. 5.- Clock converter from 2.048 MHz to line signal to 2.048 Mbit / s, according to claim 4, characterized in that said output stages generate an alarm signal (22) in the event that the input clock (1) disappears from the input of the converter, which is transformed to signal (24) light indicating fault by means of an adapter (23).