KR970056902A - Synchronizer in a multiprocessor environment - Google Patents
Synchronizer in a multiprocessor environment Download PDFInfo
- Publication number
- KR970056902A KR970056902A KR1019950067113A KR19950067113A KR970056902A KR 970056902 A KR970056902 A KR 970056902A KR 1019950067113 A KR1019950067113 A KR 1019950067113A KR 19950067113 A KR19950067113 A KR 19950067113A KR 970056902 A KR970056902 A KR 970056902A
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- KR
- South Korea
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- interrupt signal
- processor
- time value
- start time
- multiprocessor environment
- Prior art date
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Abstract
본 발명은 멀티 프로세서 환경에 관한 것으로서, 제1인터럽트 신호에 의하여 인터럽트되어 입력 명령을 수행하는 다수개의 프로세서(P1-P4)들과; 동기화 회로 (1)로서, 상기 수행할 명령을 제2인터럽트 신호에 따라 해당 제1인터럽트 신호와 함께 해당 프로세서(P1-P4중에 하나)에 인가하며, 다음 시작 시간값을 출력하는 동기플세서(P5)와, 상기 동기 프로세서(P5)의 다음 시작 시간값을 인가받아 저정하는 에지스터(11)와; 타이버(12)와; 상기 타이머(12)의 시간값이 상기 레지스터(11)에 저장된 시작 시간값과 동일한 때에 상기 동기 프로세서(P5) 상기 제2인터럽트 신호를 출력하는 비교부(13)를 포함하는 동기화 회로(1)를 구비한다. 즉, 본 발명은 동기 프로세서내에 각 프로세서들이 수행하여야 할 동작 시작 시간값을 저장하고 동작 시간 시간에 도달하였는지를 타이멀서 체크하여 동작시간 시간이면 해당 프로세서에 해당동작을 명하는 명령 신호 및 인터럽트 신호를 출력케하므로서 멀티 프로세서 환경에서 프로세서간의 동기를 맞출수 있다는 효과가 있다.The present invention relates to a multiprocessor environment, comprising: a plurality of processors (P1-P4) interrupted by a first interrupt signal to perform input commands; As a synchronization circuit (1), a synchronization processor (P5) for applying a command to be performed to a corresponding processor (one of P1-P4) along with a corresponding first interrupt signal according to a second interrupt signal, and outputting a next start time value. And an edgester 11 for receiving and storing a next start time value of the synchronous processor P5; A tie 12; A synchronization circuit 1 including a comparator 13 for outputting the second interrupt signal to the synchronous processor P5 when the time value of the timer 12 is equal to the start time value stored in the register 11; Equipped. That is, the present invention stores the operation start time value to be performed by each processor in the synchronous processor, and checks whether it has reached the operation time time, and outputs a command signal and an interrupt signal instructing the corresponding operation to the processor at the operation time time. This allows the synchronization between processors in a multiprocessor environment.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 본 발명에 따른 멀티 프로세서 환경에서 동기 장치의 블럭도,1 is a block diagram of a synchronization device in a multiprocessor environment according to the present invention;
제2도는 본 발명에 따른 멀티 프로세서 환경에서 동기 장치에 이루어지는 동기화 회로의 블럭도.2 is a block diagram of a synchronization circuit formed in a synchronization device in a multiprocessor environment according to the present invention.
제3도는 제2도의 동기화 회로내 동기 프로세서에 저장되는 테이블의 일예를 도시한 도면.FIG. 3 shows an example of a table stored in the synchronization processor in the synchronization circuit of FIG. 2. FIG.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950067113A KR970056902A (en) | 1995-12-29 | 1995-12-29 | Synchronizer in a multiprocessor environment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950067113A KR970056902A (en) | 1995-12-29 | 1995-12-29 | Synchronizer in a multiprocessor environment |
Publications (1)
Publication Number | Publication Date |
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KR970056902A true KR970056902A (en) | 1997-07-31 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019950067113A KR970056902A (en) | 1995-12-29 | 1995-12-29 | Synchronizer in a multiprocessor environment |
Country Status (1)
Country | Link |
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KR (1) | KR970056902A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8683251B2 (en) | 2010-10-15 | 2014-03-25 | International Business Machines Corporation | Determining redundancy of power feeds connecting a server to a power supply |
US8688885B2 (en) | 2010-04-13 | 2014-04-01 | Samsung Electronics Co., Ltd. | Hardware acceleration apparatus, method and computer-readable medium efficiently processing multi-core synchronization |
-
1995
- 1995-12-29 KR KR1019950067113A patent/KR970056902A/en not_active Application Discontinuation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8688885B2 (en) | 2010-04-13 | 2014-04-01 | Samsung Electronics Co., Ltd. | Hardware acceleration apparatus, method and computer-readable medium efficiently processing multi-core synchronization |
US8683251B2 (en) | 2010-10-15 | 2014-03-25 | International Business Machines Corporation | Determining redundancy of power feeds connecting a server to a power supply |
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