KR970030635A - Device Separation Method of Nonvolatile Memory Device - Google Patents

Device Separation Method of Nonvolatile Memory Device Download PDF

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Publication number
KR970030635A
KR970030635A KR1019950040695A KR19950040695A KR970030635A KR 970030635 A KR970030635 A KR 970030635A KR 1019950040695 A KR1019950040695 A KR 1019950040695A KR 19950040695 A KR19950040695 A KR 19950040695A KR 970030635 A KR970030635 A KR 970030635A
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KR
South Korea
Prior art keywords
oxide film
film
ion implantation
forming
region
Prior art date
Application number
KR1019950040695A
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Korean (ko)
Inventor
손문
정칠희
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950040695A priority Critical patent/KR970030635A/en
Publication of KR970030635A publication Critical patent/KR970030635A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass

Abstract

본 발명은 필드트랜지스터의 임계전압의 감소와 내압전압의 특성저하를 동시에 방지할 수 있는 불휘발성 메모리 장치의 소자분리방법에 관하여 개시한다. 본 발명의 불휘발성 메모리 장치의 소자분리방법에 의하면, 셀어레이지역은 1,2차의 불순물 이온주입에 의한 소자분리(channel stop)를 진행함으로써 1차의 불순물 이온주입 후 필드산화막의 성장시 편석현상에 의한 불순물 손실을 2차의 이온주입으로 보완해 줌에 따라 칩의 동작시 셀-어레이 지역의 제어게이트에 인가되는 고전압에 의한 인접 셀(cell)들과의 간섭현상을 막아주며, 1차 불순물 이온주입이 되지 않은 고전압회로지역은 필드산화막 성장 후 셀어레이 지역에 진행되는 2차 불순물 이온주입의 사진공정을 이용하여 동시에 불순물을 이온주입함에 따라 필드산화막 성장시의 불순물의 수평확산과 편석현상을 모두 감소시킬 수 있다.The present invention discloses a device isolation method of a nonvolatile memory device capable of simultaneously preventing the reduction of the threshold voltage of the field transistor and the deterioration of characteristics of the breakdown voltage. According to the device isolation method of the nonvolatile memory device of the present invention, the cell array region is segregated during the growth of the field oxide film after the primary impurity ion implantation by performing channel stop by the first and second impurity ion implantation. As the impurity loss caused by the phenomenon is compensated by the secondary ion implantation, it prevents the interference with adjacent cells due to the high voltage applied to the control gate in the cell-array region during the operation of the chip. In the high voltage circuit region where impurity ion implantation is not performed, the horizontal diffusion and segregation of impurities during field oxide film growth are performed by implanting impurities at the same time by using the secondary impurity ion implantation process performed in the cell array region after the field oxide film growth. Can be reduced.

Description

불휘발성 메모리 장치의 소자분리방법Device Separation Method of Nonvolatile Memory Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 의하여 셀어레이지역 및 주변회로지역을 갖는 불휘발성 메모리 장치의 소자분리방법을 설명하기 위한 평면도이다.1 is a plan view illustrating a device isolation method of a nonvolatile memory device having a cell array region and a peripheral circuit region according to the present invention.

Claims (1)

셀어레이지역과, 고전압회로지역 및 기타회로지역을 갖는 주변회로지역으로 구성된 불휘발성 메모리 장치의 소자분리방법에 있어서, 반도체 기판 상에 패드산화막, 비정질실리콘막 및 질화막을 형성한 후 패터닝하여 필드지역과 액티브지역을 한정하는 단계; 상기 셀어레이지역과 기타회로지역의 필드지역을 오픈하는 제1감광막 패턴을 형성하는 단계; 상기 제1감광막 패턴을 마스크로 1차 소자분리를 위한 이온주입을 실시하는 단계; 상기 1차로 이온주입된 상기 기판을 산화시켜 필드산화막을 형성하는 단계; 상기 질화막, 비정질실리콘막 및 패드산화막을 제거하는 단계; 상기 주변회로지역에 게이트산화막을 형성하는 단계; 상기 기판의 전면에 산화막 및 제1도전막을 형성하는 단계; 상기 제1도전막상에 상기 셀어레이지역 및 고전압회로지역에 형성된 상기 필드산화막의 일부분을 노출하는 제2감광막 패턴을 형성하는 단계; 상기 제2감광막 패턴을 마스크로 상기 제1도전막 및 산화막을 식각하여 부유게이트 및 터널산화막을 형성하는 단계; 상기 제2감광막 패턴을 마스크로 2차 소자분리를 의한 이온주입을 실시하는 단계; 상기 감광막 패턴을 제거하는 단계; 상기 기판의 전면에 절연막을 형성하는 단계; 상기 주변회로지역에 형성된 상기 절연막 및 제1도전막을 제거하는 단계; 상기 주변회로지역의 게이트산화막을 성장시키는 단계; 및 상기 기판의 전면에 제2도전층을 형성한 후 패터닝하여 제어게이트를 형성하는 단계를 구비하는 것을 특징으로 하는 불휘발성 메모리 장치의 소자분리방법.In the device isolation method of a nonvolatile memory device comprising a cell array region and a peripheral circuit region having a high voltage circuit region and other circuit regions, a pad oxide film, an amorphous silicon film, and a nitride film are formed on a semiconductor substrate and then patterned to form a field region. Defining an active area; Forming a first photoresist pattern for opening a field region of the cell array region and the other circuit region; Performing ion implantation for primary device isolation using the first photoresist pattern as a mask; Oxidizing the first ion implanted substrate to form a field oxide film; Removing the nitride film, the amorphous silicon film, and the pad oxide film; Forming a gate oxide film in the peripheral circuit area; Forming an oxide film and a first conductive film on the entire surface of the substrate; Forming a second photoresist pattern on the first conductive film to expose a portion of the field oxide film formed in the cell array region and the high voltage circuit region; Etching the first conductive layer and the oxide layer using the second photoresist pattern as a mask to form a floating gate and a tunnel oxide layer; Performing ion implantation by secondary device isolation using the second photoresist pattern as a mask; Removing the photoresist pattern; Forming an insulating film on the entire surface of the substrate; Removing the insulating film and the first conductive film formed in the peripheral circuit area; Growing a gate oxide film of the peripheral circuit region; And forming a control gate by forming a second conductive layer on the entire surface of the substrate and then patterning the second conductive layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950040695A 1995-11-10 1995-11-10 Device Separation Method of Nonvolatile Memory Device KR970030635A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950040695A KR970030635A (en) 1995-11-10 1995-11-10 Device Separation Method of Nonvolatile Memory Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950040695A KR970030635A (en) 1995-11-10 1995-11-10 Device Separation Method of Nonvolatile Memory Device

Publications (1)

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KR970030635A true KR970030635A (en) 1997-06-26

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KR1019950040695A KR970030635A (en) 1995-11-10 1995-11-10 Device Separation Method of Nonvolatile Memory Device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100298498B1 (en) * 1998-07-17 2001-08-07 아끼구사 나오유끼 Correlator and Delay Lock Loop Circuitry

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100298498B1 (en) * 1998-07-17 2001-08-07 아끼구사 나오유끼 Correlator and Delay Lock Loop Circuitry

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