KR970030333A - Method for manufacturing conductive wiring contact of semiconductor device - Google Patents

Method for manufacturing conductive wiring contact of semiconductor device Download PDF

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Publication number
KR970030333A
KR970030333A KR1019950039691A KR19950039691A KR970030333A KR 970030333 A KR970030333 A KR 970030333A KR 1019950039691 A KR1019950039691 A KR 1019950039691A KR 19950039691 A KR19950039691 A KR 19950039691A KR 970030333 A KR970030333 A KR 970030333A
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South Korea
Prior art keywords
conductive wiring
layer
oxide film
lower conductive
metal layer
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KR1019950039691A
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Korean (ko)
Inventor
김헌도
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950039691A priority Critical patent/KR970030333A/en
Publication of KR970030333A publication Critical patent/KR970030333A/en

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Abstract

본 발명은 반도체소자의 도전배선 콘택 제조방법에 관한 것으로서, 소정의 기판상에 형성되어있는 하측 도전배선을 노출시키는 콘택홀을 구비하는 층간절연막을 형성하고, 전처리 공정 없이 장벽금속층인 Ti층을 형성하며 소정의 온도에서 열처리하여 하측 금속층과 Ti층의 사이에 타이타늄 산화막을 형성한 후, 상기 콘택홀을 통하여 하측 도전배선과 연결되는 상측 도전배선을 형성하였으므로, 타이타늄 산화막이 확산방지막의 일부가 되어 확산 방지 효과가 증가되고, 콘택 저항이 감소되며, 하측 도전배선 표면에 형성되는 산화막이 타이타늄 산화막의 일부로 전환되므로 전처리 공정이 불필요하여 공정수율을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a conductive wiring contact of a semiconductor device, comprising forming an interlayer insulating film having a contact hole exposing a lower conductive wiring formed on a predetermined substrate, and forming a Ti layer as a barrier metal layer without a pretreatment process. Heat treatment at a predetermined temperature to form a titanium oxide film between the lower metal layer and the Ti layer, and then formed an upper conductive wiring connected to the lower conductive wiring through the contact hole. The prevention effect is increased, the contact resistance is reduced, and the oxide film formed on the lower conductive wiring surface is converted to a part of the titanium oxide film, so that the pretreatment process is unnecessary, thereby improving the process yield.

Description

반도체소자의 도저 배선 콘택 제조방법Method for manufacturing doser wiring contact of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1c도 내지 제1d도는 본 발명의 제1실시예에 따른 반도체소자의 도전배선 콘택 제조공정도.1C to 1D are process diagrams for manufacturing a conductive wiring contact of a semiconductor device according to a first embodiment of the present invention.

Claims (10)

소정의 기판상에 하측 도전배선을 형성하는 공정과, 상기 하측 도전배선에서 콘택으로 예정되어있는 부분을 노출시키는 콘택홀을 구비하는 층간절연막을 형성하는 공정과, 상기 구조의 전표면에 Ti 층을 포함하는 장벽금속층을 형성하는 공정과, 상기 구조의 기판을 열처리하여 상기 노출된 하측 도전배선과 Ti층의 사이에 타이타늄 산화막을 형성하는 공정과, 상기 장벽금속층상에 주금속층을 형성하는 공정과, 상기 주금속층과 장벽금속층을 패턴닝하여 상측 도전배선을 형성하는 공정을 구비하는 반도체소자의 도전배선 콘택 제조방법.Forming a lower conductive wiring on a predetermined substrate; forming an interlayer insulating film having a contact hole exposing a portion intended for contact in the lower conductive wiring; and forming a Ti layer on the entire surface of the structure. Forming a barrier metal layer comprising: forming a titanium oxide film between the exposed lower conductive wiring and the Ti layer by heat-treating the substrate having the structure; forming a main metal layer on the barrier metal layer; And patterning the main metal layer and the barrier metal layer to form upper conductive wiring. 제1항에 있어서, 상기 하측 도전배선이 반도체기판이나 하측 금속배선인 것을 특징으로 하는 반도체소자의 도전배선 콘택 제조방법.The method for manufacturing a conductive wiring contact of a semiconductor device according to claim 1, wherein the lower conductive wiring is a semiconductor substrate or a lower metal wiring. 제2항에 있어서, 상기 하측 도전배선이 반도체기판인 경우 열처리 공정시 콘택홀 부분에 형성된 자연산화막이 타이타늄 산화막의 일부로 변환하는 것을 특징으로 하는 반도체소자의 도전배선 콘택 제조방법.The method of claim 2, wherein when the lower conductive wiring is a semiconductor substrate, the natural oxide film formed in the contact hole portion is converted to a part of the titanium oxide film during the heat treatment process. 제1항 또는 제3항에 있어서, 상기 하측 도전배선이 반도체기판인 경우 장벽 금속층을 Ti층/TiN층의 적층구조로 형성하는 것을 특징으로 하는 반도체소자의 도전배선 콘택 제조방법.The method for manufacturing a conductive wiring contact of a semiconductor device according to claim 1 or 3, wherein when the lower conductive wiring is a semiconductor substrate, a barrier metal layer is formed in a stacked structure of a Ti layer and a TiN layer. 제2항에 있어서,상기 하측 도전배선이 하측 금속배선으로서 Al 계열 합금층인 경우 열처리 공정시 콘택홀 부분에 형성된 Al 산화막이 타이타늄 산화막의 일부로 변환되는 것을 특징으로 하는 반도체소자의 도전배선 콘택 제조방법.The method of claim 2, wherein when the lower conductive wiring is an Al-based alloy layer as the lower metal wiring, an Al oxide film formed in the contact hole portion is converted into a part of the titanium oxide film during the heat treatment process. . 제1항 또는 제2항에 있어서, 상기 하측 도전배선이 하측 도전배선으로서 Al 계열 합금층인 경우 장벽 금속층을 Ti층의 단층으로 형성하는 것을 특징으로 하는 반도체소자의 도전배선 콘택 제조방법.The method for manufacturing a conductive wiring contact of a semiconductor device according to claim 1 or 2, wherein when the lower conductive wiring is an Al-based alloy layer as the lower conductive wiring, a barrier metal layer is formed of a single layer of a Ti layer. 제1항에 있어서, 상기 열처리 공정을 튜브나 급속열처리기에서 400~700℃ 온도에서 실시하는 것을 특징으로 하는 반도체소자의 도전배선 콘택 제조방법.The method of claim 1, wherein the heat treatment is performed at a temperature of 400 ° C. to 700 ° C. in a tube or a rapid heat processor. 제1항에 있어서, 상기 타이타늄 산화막을 20~100Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 도전배선 콘택 제조방법.2. The method of claim 1, wherein the titanium oxide film is formed to a thickness of 20 to 100 kHz. 제1항에 있어서, 상기 콘택홀내에 장벽금속층 상에 콘택 플러그를 형성하고 상측 도전배선을 형성하는 것을 특징으로 하는 반도체소자의 도전배선 콘택 제조방법.The method of claim 1, wherein a contact plug is formed on the barrier metal layer in the contact hole, and an upper conductive wiring is formed. 제9항에 있어서, 상기 콘택 플러그를 선택적 W이나 W-플러그로 형성하는 것을 특징으로 하는 반도체소자의 도전배선 콘택 제조방법.10. The method of claim 9, wherein the contact plug is formed of a selective W or a W-plug.
KR1019950039691A 1995-11-03 1995-11-03 Method for manufacturing conductive wiring contact of semiconductor device KR970030333A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10833199B2 (en) 2016-11-18 2020-11-10 Acorn Semi, Llc Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height
US10872964B2 (en) 2016-06-17 2020-12-22 Acorn Semi, Llc MIS contact structure with metal oxide conductor
US10879366B2 (en) 2011-11-23 2020-12-29 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US10937880B2 (en) 2002-08-12 2021-03-02 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US11043571B2 (en) 2002-08-12 2021-06-22 Acorn Semi, Llc Insulated gate field effect transistor having passivated schottky barriers to the channel

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11043571B2 (en) 2002-08-12 2021-06-22 Acorn Semi, Llc Insulated gate field effect transistor having passivated schottky barriers to the channel
US10937880B2 (en) 2002-08-12 2021-03-02 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US10950707B2 (en) 2002-08-12 2021-03-16 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US11018237B2 (en) 2002-08-12 2021-05-25 Acorn Semi, Llc Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US11056569B2 (en) 2002-08-12 2021-07-06 Acorn Semi, Llc Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US11355613B2 (en) 2002-08-12 2022-06-07 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US10879366B2 (en) 2011-11-23 2020-12-29 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US11610974B2 (en) 2011-11-23 2023-03-21 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US11804533B2 (en) 2011-11-23 2023-10-31 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US10872964B2 (en) 2016-06-17 2020-12-22 Acorn Semi, Llc MIS contact structure with metal oxide conductor
US11843040B2 (en) 2016-06-17 2023-12-12 Acorn Semi, Llc MIS contact structure with metal oxide conductor
US10833199B2 (en) 2016-11-18 2020-11-10 Acorn Semi, Llc Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height
US11462643B2 (en) 2016-11-18 2022-10-04 Acorn Semi, Llc Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height

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