KR970030333A - Method for manufacturing conductive wiring contact of semiconductor device - Google Patents
Method for manufacturing conductive wiring contact of semiconductor device Download PDFInfo
- Publication number
- KR970030333A KR970030333A KR1019950039691A KR19950039691A KR970030333A KR 970030333 A KR970030333 A KR 970030333A KR 1019950039691 A KR1019950039691 A KR 1019950039691A KR 19950039691 A KR19950039691 A KR 19950039691A KR 970030333 A KR970030333 A KR 970030333A
- Authority
- KR
- South Korea
- Prior art keywords
- conductive wiring
- layer
- oxide film
- lower conductive
- metal layer
- Prior art date
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자의 도전배선 콘택 제조방법에 관한 것으로서, 소정의 기판상에 형성되어있는 하측 도전배선을 노출시키는 콘택홀을 구비하는 층간절연막을 형성하고, 전처리 공정 없이 장벽금속층인 Ti층을 형성하며 소정의 온도에서 열처리하여 하측 금속층과 Ti층의 사이에 타이타늄 산화막을 형성한 후, 상기 콘택홀을 통하여 하측 도전배선과 연결되는 상측 도전배선을 형성하였으므로, 타이타늄 산화막이 확산방지막의 일부가 되어 확산 방지 효과가 증가되고, 콘택 저항이 감소되며, 하측 도전배선 표면에 형성되는 산화막이 타이타늄 산화막의 일부로 전환되므로 전처리 공정이 불필요하여 공정수율을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a conductive wiring contact of a semiconductor device, comprising forming an interlayer insulating film having a contact hole exposing a lower conductive wiring formed on a predetermined substrate, and forming a Ti layer as a barrier metal layer without a pretreatment process. Heat treatment at a predetermined temperature to form a titanium oxide film between the lower metal layer and the Ti layer, and then formed an upper conductive wiring connected to the lower conductive wiring through the contact hole. The prevention effect is increased, the contact resistance is reduced, and the oxide film formed on the lower conductive wiring surface is converted to a part of the titanium oxide film, so that the pretreatment process is unnecessary, thereby improving the process yield.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제1c도 내지 제1d도는 본 발명의 제1실시예에 따른 반도체소자의 도전배선 콘택 제조공정도.1C to 1D are process diagrams for manufacturing a conductive wiring contact of a semiconductor device according to a first embodiment of the present invention.
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950039691A KR970030333A (en) | 1995-11-03 | 1995-11-03 | Method for manufacturing conductive wiring contact of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950039691A KR970030333A (en) | 1995-11-03 | 1995-11-03 | Method for manufacturing conductive wiring contact of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970030333A true KR970030333A (en) | 1997-06-26 |
Family
ID=66587417
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950039691A KR970030333A (en) | 1995-11-03 | 1995-11-03 | Method for manufacturing conductive wiring contact of semiconductor device |
Country Status (1)
Country | Link |
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KR (1) | KR970030333A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10833199B2 (en) | 2016-11-18 | 2020-11-10 | Acorn Semi, Llc | Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height |
US10872964B2 (en) | 2016-06-17 | 2020-12-22 | Acorn Semi, Llc | MIS contact structure with metal oxide conductor |
US10879366B2 (en) | 2011-11-23 | 2020-12-29 | Acorn Semi, Llc | Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers |
US10937880B2 (en) | 2002-08-12 | 2021-03-02 | Acorn Semi, Llc | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
US11043571B2 (en) | 2002-08-12 | 2021-06-22 | Acorn Semi, Llc | Insulated gate field effect transistor having passivated schottky barriers to the channel |
-
1995
- 1995-11-03 KR KR1019950039691A patent/KR970030333A/en not_active Application Discontinuation
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11043571B2 (en) | 2002-08-12 | 2021-06-22 | Acorn Semi, Llc | Insulated gate field effect transistor having passivated schottky barriers to the channel |
US10937880B2 (en) | 2002-08-12 | 2021-03-02 | Acorn Semi, Llc | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
US10950707B2 (en) | 2002-08-12 | 2021-03-16 | Acorn Semi, Llc | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
US11018237B2 (en) | 2002-08-12 | 2021-05-25 | Acorn Semi, Llc | Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
US11056569B2 (en) | 2002-08-12 | 2021-07-06 | Acorn Semi, Llc | Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
US11355613B2 (en) | 2002-08-12 | 2022-06-07 | Acorn Semi, Llc | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
US10879366B2 (en) | 2011-11-23 | 2020-12-29 | Acorn Semi, Llc | Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers |
US11610974B2 (en) | 2011-11-23 | 2023-03-21 | Acorn Semi, Llc | Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers |
US11804533B2 (en) | 2011-11-23 | 2023-10-31 | Acorn Semi, Llc | Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers |
US10872964B2 (en) | 2016-06-17 | 2020-12-22 | Acorn Semi, Llc | MIS contact structure with metal oxide conductor |
US11843040B2 (en) | 2016-06-17 | 2023-12-12 | Acorn Semi, Llc | MIS contact structure with metal oxide conductor |
US10833199B2 (en) | 2016-11-18 | 2020-11-10 | Acorn Semi, Llc | Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height |
US11462643B2 (en) | 2016-11-18 | 2022-10-04 | Acorn Semi, Llc | Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height |
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Legal Events
Date | Code | Title | Description |
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A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E601 | Decision to refuse application |