KR970025267A - Integrated Structure of CDL and SSW of Digital Electronic Switching System - Google Patents

Integrated Structure of CDL and SSW of Digital Electronic Switching System Download PDF

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Publication number
KR970025267A
KR970025267A KR1019950038863A KR19950038863A KR970025267A KR 970025267 A KR970025267 A KR 970025267A KR 1019950038863 A KR1019950038863 A KR 1019950038863A KR 19950038863 A KR19950038863 A KR 19950038863A KR 970025267 A KR970025267 A KR 970025267A
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KR
South Korea
Prior art keywords
space
link
data
clock
cdl
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KR1019950038863A
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Korean (ko)
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KR0171760B1 (en
Inventor
정란기
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유기범
대우통신 주식회사
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Priority to KR1019950038863A priority Critical patent/KR0171760B1/en
Publication of KR970025267A publication Critical patent/KR970025267A/en
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Publication of KR0171760B1 publication Critical patent/KR0171760B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005—Switch and router aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005—Switch and router aspects
    • H04Q2011/0007—Construction
    • H04Q2011/0024—Construction using space switching

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

본 발명에 따른 디지탈 전전자교환기의 CDL과 SSW의통합구조는 국부 데이타 링크블럭(LDL)으로부터 광링크를 통해 광전변환하여 하이웨이데이타를 수신하고, 스페이스 교환된 하이웨이 데이타를 전광변환하여 광링크로상으로 출력하는 광송수신부(211); 상기 광송수신부(211)로부터 전기적인 신호로 변환된 하이웨이 데이타를 입력받아 출력하는 개선된 스페이스 스위치 링크정합부(SLLA-N:212);상기 스페이스 스위치 링크 정합부(212)로부터 입력된 하이웨이 체이타를 제어 데이타에 따라 공간 스위칭하여 해당 스페이스 스위치 링크 정합부(212)로 출력하는 스페이스 매트릭스보드(SMXA:215); 망동기 블럭(NES:220)으로부터 합성클럭을 입력받아 재생된 클럭을 분배하는 개선된 클럭 및 프로세서정합부(CPLA-N:213); 상기 클럭 및 프로세서 정합부(213)로부터 클럭을 입력받고 스페이 스위치프로세서로부터 입력된 제어 정합 데이타를 상기 스페이스 매트릭스보드에 출력하는 개선된 프로세서 정합 제어부(PICA-N:214)로 구성되어 있다, 따라서 소용되는 회로팩이 감소되어 제조원가를 절감시킬 수 있고 신뢰성을 향상시킬 수 있는 효과가 있다.The integrated structure of the CDL and SSW of the digital electron exchanger according to the present invention receives the highway data by photoelectric conversion from the local data link block (LDL) through the optical link, and converts the space exchanged highway data into the optical link path. An optical transmission / reception unit 211 outputting the data; Improved space switch link matching unit (SLLA-N: 212) for receiving and outputting the highway data converted into an electrical signal from the optical transmission and reception unit 211; Highway body input from the space switch link matching unit 212 A space matrix board (SMXA: 215) for spatially switching the output according to the control data and outputting the space to the corresponding space switch link matching unit 212; An improved clock and processor matching unit (CPLA-N: 213) for receiving a synthesized clock from the network synchronizer block (NES) 220 and distributing a reproduced clock; And an improved processor matching controller (PICA-N) 214 that receives the clock from the clock and processor matching section 213 and outputs the control matching data input from the space switch processor to the space matrix board. Reduced circuit packs can reduce manufacturing costs and improve reliability.

Description

디지탈 전전자 교환기의 CDL과 SSW의 통합구조Integrated Structure of CDL and SSW of Digital Electronic Switching System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 CDL과 SSW의 통합구조를 도시한 블럭도,2 is a block diagram showing an integrated structure of a CDL and an SSW according to the present invention;

제4도는 본 발명에 다른 실장도이다.4 is a mounting diagram according to the present invention.

Claims (2)

ASS LDL블럭과 광링크를 통해 중앙데이타링크(CDL)블럭이 상호 접속되고, 이 중앙데이타링크(CDL)를 통해 입력된 하이웨이를 스페이스 스위치블럭(SSW)에서 공간분할 교환한 후 해당 중앙데이타링크(CDL)로 출력하도록 된 디지탈 전전자 교환기의 스위치구조에 있어서, 상기 중앙데이타링크(CDL)블럭과 상기 스페이스 스위치 블럭(SSW)이 통합되어 구성되는 것을 특징으로 하는 디지탈 전전자교환기의 CDL과 SSW의 통합구조.The central data link (CDL) block is interconnected through the ASS LDL block and the optical link, and the highway inputted through the central data link (CDL) is space-divided and exchanged in the space switch block (SSW), and then the corresponding central data link In the switch structure of the digital electronic switching device, which is output to the CDL), the central data link (CDL) block and the space switch block (SSW) are integrated. Integrated structure. 제1항에 있어서, CDL과 SSW가 통합된 스페이스 스위치부가, 국부 데이타 링크블럭(LDL)으로부터 광링크를 통해 광전변환하여 하이웨이데이타를 수신하고, 스페이스 교환된 하이웨이 데이타를 광전변환하여 광링크상으로 출력하는 광송수신부(211); 상기 광송수신부(211)로부터 전기적인 신호로 변환된 하이웨이 데이타를 입력받아 출력하는 개선된 스페이스 스위치 링크정합부(SLIA-N : 212); 상기 스페이스 스위치 링크 정합부(212)로부터 입력된 하이웨이 데이타를 제어 데이타에 따라 공간 스위칭하여 해당 스페이스 스위치 링크 정합부(212)로 출력하는 스페이스 매트릭스보드(SMXA:215); 망동기 블럭(NES:220)으로부터 합성클럭을 입력받아 재생된 클럭을 분배하는 개선된 클럭 및 프로세서정합부(CPLA-A:213); 상기 클럭 및 프로세서 정합부(213)로부터 클럭을 입력받고 스페이 스위치프로세서로부터 입력된 제어 데이타를 상기 스펭;TM 매트릭스보드에 출력하는 개선된 프로세서 정합 제어부(PICA-N:214)로 구성되는 것을 특징으로 하는 디지탈 전전자교환기의 CDL과 SSW의 통합구조.The space switch unit of claim 1, wherein the space switch unit in which the CDL and the SSW are integrated, receives the highway data by photoelectric conversion from the local data link block (LDL) through the optical link, and converts the space-exchanged highway data into the optical link. An optical transmitting and receiving unit 211 for outputting; An improved space switch link matching unit (SLIA-N: 212) for receiving and outputting highway data converted into an electrical signal from the optical transmitter / receiver 211; A space matrix board (SMXA: 215) for spatially switching highway data input from the space switch link matching unit 212 according to control data and outputting the space data to the corresponding space switch link matching unit 212; An improved clock and processor matching unit (CPLA-A: 213) for receiving a synthesized clock from the network synchronizer block (NES) 220 and distributing a reproduced clock; And an improved processor matching controller (PICA-N) 214 that receives a clock from the clock and processor matching unit 213 and outputs control data input from the space switch processor to the Spang; TM matrix board. Integrated structure of CDL and SSW of digital electronic exchanger.
KR1019950038863A 1995-10-31 1995-10-31 Integral construction of digital full electronic switching system KR0171760B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950038863A KR0171760B1 (en) 1995-10-31 1995-10-31 Integral construction of digital full electronic switching system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950038863A KR0171760B1 (en) 1995-10-31 1995-10-31 Integral construction of digital full electronic switching system

Publications (2)

Publication Number Publication Date
KR970025267A true KR970025267A (en) 1997-05-30
KR0171760B1 KR0171760B1 (en) 1999-03-30

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100323108B1 (en) * 1999-12-30 2002-02-02 박종섭 The control data link circuit pack of full electronic exchanger

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100323108B1 (en) * 1999-12-30 2002-02-02 박종섭 The control data link circuit pack of full electronic exchanger

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Publication number Publication date
KR0171760B1 (en) 1999-03-30

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