KR970012784A - Semiconductor memory device with normal / test bonding pad - Google Patents
Semiconductor memory device with normal / test bonding pad Download PDFInfo
- Publication number
- KR970012784A KR970012784A KR1019950026275A KR19950026275A KR970012784A KR 970012784 A KR970012784 A KR 970012784A KR 1019950026275 A KR1019950026275 A KR 1019950026275A KR 19950026275 A KR19950026275 A KR 19950026275A KR 970012784 A KR970012784 A KR 970012784A
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- KR
- South Korea
- Prior art keywords
- test
- bonding pad
- pad
- bonding
- normal mode
- Prior art date
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- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
Abstract
본 발명은 반도체 메모리 장치에 관한 것으로서, 특히 반도체 메모리 장치에 있어서, 노말모드에서는 데이타 입출력 패드로 사용되고 테스트 모드에서는 특정 테스트용 패드로 겸용 사용되는 적어도 하나 이상의 제1본딩패드; 노말모드 및 테스트모드를 선택하기 위한 바이어스 신호가 인가되는 적어도 하나 이상의 제2본딩패드; 적어도 하나 이상의 제2본딩패드 중 대응하는 제2본딩패드에 인가되는 바이어스신호에 응답하여 대응하는 제1본딩패드와 데이타 입출력 버퍼를 노말모드에서는 연결하고 테스트 모드에서는 분리하기 위한 적어도 하나 이상의 제1분리회로부; 및 적어도 하나 이상의 제2본딩패드 중 대응하는 제2본딩패드에 인가되는 바이어스신호에 응답하여 대응하는 제1본딩 패드와 테스트 대상이 되는 내부 회로부를 노말모드에서는 분리하고 테스트 모드에서는 연결하기 위한 적어도 하나 이상의 제2분리회로부를 구비한 것을 특징으로 한다.The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device, comprising: at least one first bonding pad used as a data input / output pad in a normal mode and a specific test pad in a test mode; At least one second bonding pad to which a bias signal for selecting a normal mode and a test mode is applied; At least one first separation for connecting the corresponding first bonding pad and the data input / output buffer in the normal mode and disconnecting in the test mode in response to a bias signal applied to the corresponding second bonding pad among the at least one second bonding pad. Circuit section; And at least one of the at least one second bonding pads for separating the corresponding first bonding pads and the internal circuit unit to be tested in the normal mode and connecting them in the test mode in response to a bias signal applied to the corresponding second bonding pads. The above-mentioned second separation circuit section is provided.
따라서, 본 발명에서는 본딩 패드를 노말/테스트 겸용으로 사용할 수 있어서 본딩 패드의 수를 감축할 수 있다.Therefore, in the present invention, the bonding pad can be used as a normal / test combination, thereby reducing the number of bonding pads.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제4도는 본 발명에 의한 노말/테스트 겸용 본딩 패드를 가진 반도체 메모리 장치의 회로 구성을 나타낸 회로도.4 is a circuit diagram showing a circuit configuration of a semiconductor memory device having a normal / test double bond pad according to the present invention.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950026275A KR970012784A (en) | 1995-08-24 | 1995-08-24 | Semiconductor memory device with normal / test bonding pad |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950026275A KR970012784A (en) | 1995-08-24 | 1995-08-24 | Semiconductor memory device with normal / test bonding pad |
Publications (1)
Publication Number | Publication Date |
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KR970012784A true KR970012784A (en) | 1997-03-29 |
Family
ID=66596062
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950026275A KR970012784A (en) | 1995-08-24 | 1995-08-24 | Semiconductor memory device with normal / test bonding pad |
Country Status (1)
Country | Link |
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KR (1) | KR970012784A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100532391B1 (en) * | 1998-08-27 | 2006-01-27 | 삼성전자주식회사 | Test control circuit having minimum number of pad |
KR100557225B1 (en) * | 2004-11-04 | 2006-03-07 | 삼성전자주식회사 | Data input/output method of semiconductor memory device and semiconductor memory device for the same |
KR100900921B1 (en) * | 2001-09-14 | 2009-06-03 | 후지쯔 마이크로일렉트로닉스 가부시키가이샤 | Semiconductor device |
-
1995
- 1995-08-24 KR KR1019950026275A patent/KR970012784A/en not_active Application Discontinuation
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100532391B1 (en) * | 1998-08-27 | 2006-01-27 | 삼성전자주식회사 | Test control circuit having minimum number of pad |
KR100900921B1 (en) * | 2001-09-14 | 2009-06-03 | 후지쯔 마이크로일렉트로닉스 가부시키가이샤 | Semiconductor device |
KR100557225B1 (en) * | 2004-11-04 | 2006-03-07 | 삼성전자주식회사 | Data input/output method of semiconductor memory device and semiconductor memory device for the same |
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