KR970011699B1 - Caption image interpolation system for satellite broadcasting - Google Patents

Abstract

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Description

Satellite broadcasting subtitle superimposition system

The present invention relates to a kind of satellite broadcasting subtitle superposition system, and more particularly, to a satellite broadcasting subtitle superposition system capable of performing an accurate subtitle display operation by a subtitle superposition method without artificially monitoring and adjusting subtitles. .

In Taiwan, Japanese satellite television programs can be viewed simply by installing a satellite receiver. However, most people do not understand Japanese, so it is rare to actually install satellite receivers.

With the rapid spread of cable televisions and co-receiving antennas in complexes, viewers can enjoy satellite broadcasting without installing receivers.

Movies are generally the most welcoming program among television programs, and some Japanese satellite television stations have subzeros as their main program. Nevertheless, it is a pity that such a beautiful movie cannot be enjoyed because it does not know the Japanese subtitles.

In addition, some cable stations embed Chinese subtitle cartridges into satellite television movies. However, since there is no synchronization signal, it is necessary to continuously monitor during the airing process, and it is necessary to adjust the state of captions. In addition, Chinese subtitles needed to be transmitted by a specific transmission network to a receiving terminal of each required system. For cable television companies, satellite broadcasting is the main source of programmes, and companies and foundations interested in the management of this field frequently invest large amounts of money to borrow satellite frequency converters to provide the program content.

The present invention has been proposed to solve the above problems, and has a main purpose to provide a satellite broadcasting subtitle superimposition system that does not need to artificially monitor subtitles of a screen and does not need to accurately adjust subtitles.

1 is a block diagram of a satellite broadcasting subtitle overlapping system of the present invention.

2 is a block diagram of a time code processor of the present invention.

3 is a schematic diagram of a SMPTE time code of the present invention;

4 is an explanatory diagram of a style of Chinese code of the present invention.

Fig. 5 is a flow chart showing synchronization, code decoding and code embedding operations based on the SMPTE timecode format of the microprocessor circuit of the present invention.

FIG. 6 is an explanatory diagram showing a radio signal referred to in the flowchart of FIG. 5 of the present invention; FIG.

Fig. 7 is an operation flowchart of the caption processing software computer of the present invention.

Eighth, more detailed flowchart of subtitle processing software operation of the present invention.

Fig. 9 is a more detailed flowchart of the subtitle processing software operation of the present invention following Fig. 8;

FIG. 10 is a more detailed flowchart of the subtitle processing software operation of the present invention following FIG. 9; FIG.

Fig. 11 is a flowchart showing operation of the caption inserter of the present invention.

12 is a block diagram of a caption superimposition circuit of the present invention;

* Explanation of symbols for main parts of the drawings

11: video signal processor, 12: time code processor,

13: subtitle file disk, 14: transmit antenna,

15: terrestrial reception system, 16: subtitle inserter,

17 subtitle processing software computer, 18 synchronization satellite,

19: receiving antenna, 21: input interface circuit,

22: analog signal splitting circuit, 23: microprocessor circuit,

24: digital signal forming circuit, 25: output interface circuit,

26: timing generating circuit, 31: RS232-C interface,

32: time code format conversion and comparison, 33: subtitle file processing,

34: subtitle display parameter, 35: subtitle inserter interface

41: printer port interface circuit, 42: microprocessor circuit,

43: modulation code incorporation circuit, 44: return period insertion circuit,

45: output interface, 46: synchronous disconnect circuit,

47: timing generating circuit, 51: address code decoding circuit,

52: microprocessor, 53: address generator,

54: character memory, 56: address selector,

57: data selector, 58: timing generator,

110: terrestrial receiving system, 111: subtitle overlapper,

112: TV tuner, 113: satellite broadcasting system,

510: data selector, 511: data code decoding circuit,

512: background data expander, 513: foreground transfer register,

514: background transfer register, 515: color selector,

516: synchronous separation circuit, 517: image insertion circuit,

L515-L518: RGB Signal, L518: Dot Data,

L520: Image signal, L521: Line,

L52: vertical sync signal, L53: horizontal sync signal,

VD: video signal, L55: data bus,

L54, L56, L58: Address Bus

The present invention for effectively achieving the above object mainly comprises a video signal processor 1, a time code processor 12, a caption inserter 16, a caption file disk 13, and a caption processing software computer 17 Pre-devices of the terrestrial transmission system 15 in the satellite broadcasting system 113, the subtitle supervisor 111, the television tuner 112, the satellite broadcasting system 113, and It is composed by tuning.

In the transposition device of the terrestrial transmission system 15, the video signal and the audible signal are sent from the video signal processor 11 to the time code processor 12 and the subtitle inserter 16, respectively. The form and electrical characteristics of the time code output by the video signal processor 1 are converted into a digital signal that can be received by the caption processing software computer 17.

The subtitle file disc 13 stores the display time and the subtitle contents of the tape subtitles in a single character file, with the time code as a reference index, when the video tape passes. The caption processing software computer 17 compares and contrasts the text file with the time code, and recomposes the digital caption data required by the caption inserter 16 so that it is exactly on the retrace line of the vertical retrace period of the image frame. Put it in. For example, in the present invention, the caption data is embedded on the two scanning lines of the 19th and 20th of the vertical retrace period.

The satellite broadcasting system 113 transmits and receives the caption data from the vertical retrace period in the image frame via the caption superimposition 11, and adds the Chinese font corresponding to the caption data to the data in the image frame. The television tuner 112 modulates the subtitles and audible signals in the basic frequency state into carrier waves of a certain high frequency television channel, mixes them with other CATV channel carriers, and transmits them to the viewers of the CATV.

The video signal VD including the caption data is input to the video signal input impedance matcher by the terrestrial reception system 11. Thereafter, it is sent to the synchronous separation circuit 516, the image insertion circuit 517, and the video signal data decoding circuit 511. The synchronizing separation circuit 516 extracts the horizontal synchronizing signal L53 and the vertical synchronizing signal L25 from the video signal. This video signal also supplies an input video signal used for the image insertion circuit 517. The code decoding circuit of the video signal data also reads the caption data by the video signal, and reads the caption data by the data bus L55 based on the time of the horizontal synchronization signal by the microprocessor. read in) In the present invention described above, the Chinese character code of Big-5 is adopted, and therefore the caption data also includes the control code for the Chinese character code of Big-5 and other display captions.

The received Big-5 numerical values compared by the microprocessor 52 designate a memory address on the address bus L54, take out Chinese character types by the character memory 54, and place them in the video signal memory 59. . This is the part that acquires Chinese character type.

The portion in which the Chinese character data of the video signal memory 59 is displayed on the video screen is called a display form. When the circuit is in display mode, the address of the video signal memory 59 is designated by the address generator 53, and the Chinese character data on the designated video signal memory 59 is transferred to the foreground via the address buses L56 and L58. A register 513 and a background data expander 512 are sent to the color selector 515 after image processing. Finally, the color and image processed character type is inserted on the signal of the video signal, and then output through the video signal amplifier.

1 is a block diagram of a satellite broadcasting subtitle superimposition system of the present invention. As shown in the figure, the present invention mainly includes a video signal processor 11, a time code processor 12, a caption file disk 13, a caption processing software computer 17, and a caption inserter 16. And the caption superimposing unit 111, the television tuner 112, and the satellite broadcasting system 113. FIG.

Among them, the satellite broadcasting system 113 is constituted by a terrestrial transmission system 15, a synchronous satellite 18 and a terrestrial reception system 110, which are satellites that rotate in the same cycle as the rotation of the earth. The video signal and the audible signal of the basic frequency television program are modulated and amplified by the terrestrial signal system 15, and then aimed at the synchronization satellite 18 using a high gain transmission antenna 14. Send. The TV carrier signal of the subtitle overlapper is received by the antenna of the synchronization satellite 18 and then amplified via the frequency converter, and sets the terrestrial broadcast zone by the positioning antenna. The terrestrial receiving system 11 includes a receiving antenna 19 and receives an electromagnetic wave signal transmitted by the synchronization satellite 18. The terrestrial reception system 110 amplifies the received signal, processes it at an intermediate frequency, and detects a video signal and an audible signal of a television in a basic frequency state by a detector. Thus, the viewer can receive this program only if he has a monitor of the television.

The transposition device of the terrestrial transmission system 15 sends a video signal and an audible signal from the video signal processor 11 to the time code processor 12 and the subtitle inserter 16, respectively, and the time code processor 12 transmits the video. The form and electrical characteristics of the time code output by the signal processor 11 are converted into a digital signal that can be received by the caption processing software computer 17. The subtitle file disc 13 stores the display time and the subtitle contents of the tape subtitles in a single character file by using the time code as a reference index when the video tape passes. The caption processing software computer 17 compares and contrasts this character file with the time code, and also reorganizes the digital caption data required by the caption inserter 16, and exactly on the retrace line of the vertical retrace period of the image frame. Put it in. For example, in the present invention, the caption data is embedded on the two scanning lines of the 19th and 20th of the vertical retrace period.

Further, through the transmission and reception of the satellite broadcasting system 113 and the caption superimposing unit 111, the caption data is extracted from the vertical return period in the image frame, and the Chinese font corresponding to the caption data is added to the data in the image frame. In addition, the TV tuner 112 modulates the subtitles and audible signals in the basic frequency state into carriers of a certain high frequency television channel, and transmits them to the viewers of CATV mixed with other CATV channel carriers.

Next, referring to the block diagram of the signal code processor 12 of the present invention of FIG. As shown in Fig. 2, the input of the input interface circuit 21 is the SMPLE time code of the video. This signal wave is shown in FIG.

The input interface circuit 21 utilizes one differential amplifing circuit, converts the SMPTE signal into a reference signal for the ground of a single pole, and also uses an analog signal. Although the dividing circuit 22 passes through, the analog splitting circuit 22 uses two comparator circuits to input the analog signal inputted by two large and small floating electrical level signals. signal) and read into the microprocessor circuit 23. This microprocessor circuit 23 is composed of a microprocessor of the PIC16C54 and a correlated clock circuit. In addition, operations such as bit discrimination, level, code decoding, and code embedding are performed in a software manner. The flowchart of this software is as shown in the figure. The microprocessor circuit 23 detects the signal level sent by the analog signal splitting circuit 22 to determine the bit. Reference is made to the propagation signal of FIG. 6. This is the task of determining the value of each bit based on the calculation of the time between two transitions by the microprocessor 23, for example (416.7us + 208.4us) / z = 313us. It is a standard. If the calculated value is larger than 313us, it is " 0 ", and if smaller than 313us, a bit " 1 " is formed. The microprocessor circuit 23 reads the value of each bit in a serial manner, stores it in a register therein, and then synchronizes, decodes, and embeds the code based on the SMPTE time code form of FIG. Do the work of. Step 4 in the main flow chart of Fig. 5 sets each parameter value. From step (3) to step (8), the phase acquisition operation is performed to compare and contrast the contents of the automatic recording with the SMPTE synchronization, and determine whether or not synchronization. However, step 4 resets the watchdog timer. Its purpose is to determine and warn that a microprocessor has failed based on this if the synchronization is not reached even after the timer has elapsed, and prevents an error caused by a time code error. Step 9 indicates that synchronization has been acquired.

Since the caption processing software computer 17 only needs picture frames, seconds, minutes, hours and synchronization data from within the SMPTE time code, it is necessary to discard any SMPTE bits. This is as shown from step 11 to step 18.

The microprocessor circuit 23 performs code embedding of each code in addition to discriminating bits and decoding hour, minute and second image frames, thereby facilitating discrimination and reception of the subtitle processing software computer 17. That is, the microprocessor circuit 23 combines the codes of the hour, minute, second, etc. into seven bits, and sends them to the data digital signal forming circuit 24 in a parallel manner. The form of the Chinese code is as shown in FIG.

In the digital signal forming circuit 24, the microprocessor circuit 28 converts the digital signal in series in a parallel manner and adds a start bit. In addition, the data transmission speed rate (speed ratio) is set to 2400 bps in order to comply with the RS 232-C communication protocol of the caption processing software computer 17.

The main task of the output interface circuit 25 is to switch the signal level of the communication signal. That is, the TTL level is switched to the communication signal level (+/- 12V) of the caption processing software computer 17. The signal output from this circuit is an electrical characteristic which the RS 232-C port of the caption processing software computer 17 accepts, and this data format also conforms to the provisions of the caption processing software computer 17.

The timing generator 26 generates a clock signal of 307.2 KHz required for the microprocessor 23 and a clock signal of 2.4 KHz used for communication of RS 232-C by vibration of the crystal vibrator of 2.4576 MHz.

7 is a flowchart of the operation of the caption processing software computer 17 of the present invention. As shown in Fig. 7, the main task of the caption processing software computer 17 is to receive the time code sent from the time code processor 12 and store the time code previously stored in the internal disk. Compared with the subtitle file, the correlation data of one subtitle is calculated and put into the subtitle inserter 16. One of them becomes the communication serial interface 31 (RS 232-C). The process in this section sets the parameter values of RS 232-C, receives the time spent by the time code processor 12, and also compares the RS 232-C communication serial interface 31 as a code form switcher. Converts the received timecode format to the timecode format of the subtitle file for comparison. In addition, the subtitle file processor 23 determines whether or not the comparison of the timecode at the time is consistent. If this is correct, the display time and the caption data are read out, and if there are two rows of caption data, division of labor is always performed. Further, the caption display position of the row is calculated from the data processed by the calculation of the caption display parameter 34, and is based on the receiver film overlap. In addition, the subtitle inserter interface 35 sends the parameter control code of the display and the already processed subtitle data from the printer port to the subtitle inserter 16.

8 is a flowchart of the caption processing software. Steps 2 to 7 of Fig. 8 are the RS 232-C interface processing. From step 8 to step 10, comparison and switching of the timecode form is performed. Steps 11 and 12 perform subtitle file processing. Step 13 calculates caption display parameters. Steps 14 to 20 are the subtitle inserter interface processing process, and if there are two subtitles, the process is performed in steps 21 and 22.

11 is a block diagram of a subtitle inserter of the present invention. As shown in the figure, the input portion of the caption inserter 16 sends the video signal input of the video signal processor 11 and the printer port data from the caption processing software computer 17 to the printer port interface 41. . This printer port interface 41 is formed by a buffer circuit and a handshake circuit, receives subtitle data sent from the printer port of the subtitle processing software computer 17, and the microprocessor circuit 42 ) To handle. This microprocessor circuit 42 is constituted by the 8051 single-chip microprocessor and calculates the scan bow in the vertical retrace period based on the synchronization signal from the modulation separation circuit 46. When the 19th and 20th scanning lines are calculated, the mask signal is output, transmitted during the retrace period, inserted into the analog switching switch in the circuit 44, the video signal is separated, and the caption data is inserted. The modulation code embedding circuit 43 converts the caption data output from the microprocessor 42 from parallel to serial based on the 12 MHz clock signal of the timing generating circuit 47 and the synchronization signal of the synchronization separating circuit. After the signal 2, it is delayed by 11us to start with a modulation carrier frequency of 1us and sequentially transmits the caption data to the 22-interval insertion circuit 44.

The synchronizing separation circuit 46 separates the horizontal synchronizing signal 2 from the input video signal of the video signal processor 11, and the microprocessor circuit 42 calculates the vertical retrace period scan player. This horizontal synchronizing signal is also a timing reference point of the modulation code embedding circuit 43. In addition, the 12 MHz clock signal generated by the timing generator circuit 47 is provided to the microprocessor circuit 42 and the modulation code embedding circuit 43.

The retrace period insertion circuit 44 inserts subtitle data on the 19th and 20th scan lines of the vertical retrace period of the video signal based on the scan number calculated by the microprocessor circuit 42. The caveat of this part of the circuit is that there should be no errors in the preceding inputs.

The output interface circuit 45 transmits the video signal in the basic frequency state of the caption data V included therein to the terrestrial transmission system via a buffer amplifier circuit.

12 is a block diagram of a caption superimposition circuit. This circuit is also a technical element of the present invention. The video signal acquired by the terrestrial receiver compares and compares Chinese subtitle data to find a corresponding Chinese character type and simultaneously controls subtitle superimposition based on a control code. Before further explaining the principle of operation of this circuit, the function of each block in Fig. 12 will be briefly described. First, the microprocessor 52 is provided with a central processing unit (CPU), and performs a coordinated operation between each circuit. The microprocessor 52 calculates the current screen by the vertical synchronization signal L52 of the synchronization separation circuit 516. In addition, by synchronizing with the horizontal synchronizing signal L53 of the synchronizing separation circuit 516, the current horizontal scanning line is known, thereby obtaining caption data on the 19th and 20th horizontal scanning lines. In addition, appropriate data are given to these data. For example, display of subtitles, color change, height of position, and so on. In addition, the video signal memory (VRAM) 59 is controlled by the image insertion circuit 517 at an appropriate time to achieve the purpose of subtitle display.

The video signal memory 59 is constituted by a RAM 62256 of 3 KB. This is a memory required for the CPU to operate, and provides the screen insertion circuit 517 with internal data including the foreground and background data when the circuit is switched to the display mode, and the subtitles are displayed on the screen of the television. Decide

The character memory 54 provides Chinese character data of code incorporation in Big-5 code. The interpretation degree for each character is 24x24 bits, and the total 13405 characters can be saved.

The address generator 53 is an image of the synchronous separation circuit 516 because the video signal memory 59 needs to transfer the internal data to the screen insertion circuit 517 to insert an image when the circuit switches to the display mode. It synchronizes with the synchronization signal L53 and the image point clock signal 57 of the timing generator 58, and automatically generates one 15-bit address data and supplies it to the video signal memory 59, and provides a suitable foreground and background. Send the data.

The address selector 56 appropriately distributes the address right control of the video signal memory 59. That is, since the video signal memory 59 can provide and use the microprocessor 52 and the image insertion circuit 517, the right of use of the video signal memory 59 can be determined through the data selector 510. In the case of the display mode, the selector is switched to the address generator 53 to produce the dress L56 or otherwise to the address L54 of the microprocessor.

The data selector 57 determines whether or not the video signal memory 59 provides read / write to the microprocessor 52 and also sends data of the video signal memory 59 to the image insertion circuit 517. Determine whether or not.

In addition, the timing generator 58 determines whether or not to send data from the video signal memory 59 to the image insertion circuit 517, and in addition to the timing required by the address generator 53, the foreground and background registers 513 514 transmits data from the video signal memory 59 at 10 MHz in series and corresponds to the horizontal scan line of the television.

The background register 514 also converts the background data from the microprocessor 52 in a serial fashion by the frequency of the timing generator 58 in a parallel fashion and sends it to the color selector circuit 515.

In addition, the background data expander 512 determines the colors of the foreground and the background, respectively, by three bits of RGB data. In addition to the determination of the color, point data for insertion is sent to the image insertion circuit 517. The image insertion circuit 517 properly processes the RGB signals L515-L518 from the color selector 515, tunes to the insertion point data L518, and scans them appropriately based on the external image signal L520. It is inserted on the line and outputs one image signal via (L521).

In addition, the sync separation circuit 516 separates the horizontal and vertical sync signals by an image signal from the outside, and includes a microprocessor 52, an address generator 53, a background transfer register 514, and an image insertion circuit 517. Contribute to use.

In addition, the output, input control of the external data port 55 provides an 8-bit output, input control signal and contributes to external use.

Further, the video signal data decoding circuit 511 synchronizes with the horizontal synchronization signal and the image signal, puts the data on the 19th and 20 sets of horizontal synchronization signals, decodes the data via the address code decoding circuit 51, and then the microprocessor ( 52) to send and process. When the microprocessor reads / writes the unit data in each circuit, all of them pass through this address code decoding circuit 51 to control data transfer.

The video signal data decoding circuit 511 is designed to correspond to the modulation code embedding circuit 43 in the subtitle inserter 16 of the transmitting apparatus. Further, caption data in the video signal data is read out, and digital caption data of lus period is discriminated at a sampling frequency of 12 MHz. The data after the code decoding is converted into a parallel circuit through the internal serial circuit, and the center of the subtitle insertion circuit sent to the microprocessor 52 is the microprocessor 52, which is received by the video signal data decoding circuit 511. According to the caption data, the Chinese character type is taken out into the character type memory 54 and stored in the video signal memory 59. The microprocessor 52 also stores and retrieves each memory circuit via the address code decoder 51.

As described above, according to the present invention, it is possible to provide a satellite broadcasting subtitle superposition system that does not need to artificially monitor subtitles of a screen and does not need to accurately adjust subtitles.

Claims (2)

A satellite broadcasting subtitle superimposition system comprising a satellite transmission system for transmitting a satellite broadcasting signal in which subtitles are inserted and a satellite reception system for displaying the satellite broadcasting signal transmitted from the satellite transmission system on a television screen so that subtitles overlap. A video signal processor for outputting a video signal, an audible signal, and a time code signal constituting a satellite broadcast signal to be transmitted; A time code processor for converting a form and an electrical characteristic of the signal of the time code output from the video signal processor into a digital signal; A caption file disk for storing the time at which tape captions appear when the video tape passes and the contents of the captions in one text file; A caption processing software computer for comparing and comparing the text file stored in the caption file disk with the time code information output from the time code processor to reorganize digital caption data accordingly; The digital caption data provided by the caption processing software computer is inserted on a blank scanning line in a vertical blanking period in an image frame of the video signal output from the video signal processor, and the video signal into which the caption data is inserted is inserted into the satellite. A subtitle inserter for outputting to a transmission system; Extracting the caption data inserted in the vertical retrace period in the image frame of the video signal received through the satellite receiving system, and outputting the Chinese font corresponding to the caption data superimposed on the image frame surface data; A subtitle overlapper for comparing and comparing Chinese subtitle data in the video signal received through the satellite reception system and searching for a corresponding Chinese character type and controlling a superimposition function of the subtitles based on a control code; And a TV tuner configured to modulate the subtitles and audible signals output through the subtitle overlapper into a television carrier signal of any one specific high frequency, and mix the modulated signals with other channel reflection waves and transmit them through a cable. Broadcast subtitle overlay system. 2. The apparatus of claim 1, wherein the subtitle supervisor calculates the current image plane by the vertical synchronization signal separated by the synchronization separation circuit, and recognizes the current horizontal scanning line by tuning to the flat synchronization signal separated by the synchronization separation circuit. A microprocessor which obtains caption data on the nineteenth and twentieth horizontal scanning lines and controls the video signal memory vram through an image embedding circuit; Provided to the image embedding circuit including the foreground data and the background data when the microprocessor operates or when the circuit switches the display mode, and provides Chinese character data of an embedded code in Big-5 code. A character memory for storing a total of 13,405 characters with 24 and 24 bits for each Chinese character type; When the circuit switches to the display mode, the video signal memory automatically synchronizes one 15 bit by synchronizing with the synchronization signal separated by the synchronization separation circuit and the image point clock signal of the timing generator to send data therein to the image insertion circuit. An address generator for generating address data of the address data and providing the address data to the video signal memory; Using the circuitry and appropriately distributing address control of the video signal memory, determining the right to use the video signal memory through a data selector so that the video signal memory can contribute to the use of the microprocessor and the picture insertion signal, An address selector configured to select an address from which the address generator occurs or an address of a microprocessor in a display form; Another data selector for determining whether the video signal memory provides read / write to the microprocessor, and for determining whether to send video signal memory data to the image embedding circuit; In addition to determining whether to send the data of the video signal memory to the image insertion circuit, and providing the timing required by the address generator, the foreground and background data from the microprocessor may be transferred in parallel to serial manner. A timing generator for outputting data from the video signal memory in a serial manner to the foreground and background registers to be converted and output, and corresponding to the horizontal scan line of the television; The background data expander automatically sends the background data every one bit from the horizontal direction to both sides, expands two points each, and enhances the effect around the letter when a letter type is displayed; The foreground and background colors are respectively determined by three bits of RGB data, and point data requiring insertion other than the determination of the color is sent to the image embedding circuit, which is adapted to properly transmit the RGB signal from the color selector. In addition to processing, it is tuned to the insertion point data, and is appropriately inserted on the scan line based on an external image signal, and the horizontal and vertical synchronization signals are separated, and the microprocessor, address generator, foreground, background transfer register and image A color selector adapted to contribute to the use in the insertion circuit; The horizontal synchronizing signal and the image signal are decoded and placed in 19, 20 sets of data on the horizontal synchronizing signal, and processed by the microprocessor through the decoding of the address code decoding circuit. However, the microprocessor reads and writes each unit data in each circuit. In this case, the data transmission is controlled through this address code decoding circuit, and designed to correspond to the modulation code incorporation circuit in the subtitle inserter on the transmitting side, and to read caption data in the video signal data, and at a sampling frequency of 12 MHz. The digital subtitle data of the lus period is determined, and the data after the decoding is sent to the microprocessor through a circuit changed from an internal serial to a parallel circuit, which is the center of the subtitle insertion circuit, which is a video signal. The letters in view of the subtitle data received by the data decoding signal Chinese characters are taken out from the memory and stored in the video signal memory, and the subtitles in the video signal data are read out corresponding to the modulation code incorporation circuit in the subtitle inserter on the transmitting side, and digital subtitles of 1 us period are performed at a sample frequency of 12 MHz. Data is discriminated and the data after the code decoding is sent to the microprocessor through the parallel circuit conversion of the serial circuit, which is the center of the subtitle inserting circuit, and the video signal data decoding circuit receives the subtitle data to form a character memory. And a video signal data decoding circuit configured to store the Chinese character type in a video signal memory according to the order of extracting Chinese characters from the satellite broadcasting subtitles.