KR970002664A - Control signal supply circuit - Google Patents
Control signal supply circuit Download PDFInfo
- Publication number
- KR970002664A KR970002664A KR1019950016761A KR19950016761A KR970002664A KR 970002664 A KR970002664 A KR 970002664A KR 1019950016761 A KR1019950016761 A KR 1019950016761A KR 19950016761 A KR19950016761 A KR 19950016761A KR 970002664 A KR970002664 A KR 970002664A
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- KR
- South Korea
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- signal
- control
- control signal
- slave
- output
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Abstract
본 발명은 마스터(Master)와 다수 블레이브(Slave)를 가진 시스템에서 마스터의 제어신호가 다수의 슬레이브와 연결되어 있을 경우 현재 슬레이브에서의 데이타처리가 이후의 데이타 처리 속도에 영향을 주지 않도록 한 제어신호 공급회로에 관한 것으로 시스템 클럭 및 동기를 위해 사용되는 신호를 클럭신호로 하여 상기 슬레이브(2)에서 발생되는 입력제어신호(control input)를 데이타로 입력받는 플립플롭(3)과, 상기 플립플롭(3)의 출력신호를 인에이블 신호로 받고 상기 입력제어신호(control input)를 받아 출력제어신호(control output)를 출력하는 출력버퍼(4)를 구비하는 것을 특징으로 하여 간단한 회로구성으로 개별적인 인에이블을 위한 칩면적이 적고 각 슬레이브가 개별적인 인에이블 시간을 가지므로 중첩된 제어신호의 경우 중재시간이 불필요하며 현재 슬레이브의 액세스가 끝나면 이미 다음 사이클 액세스 준비가 끝난 상태로 사이클간의 잠복시간을 줄여 시스템 속도를 높이는 효과가 있다.In the present invention, when a master control signal is connected to a plurality of slaves in a system having a master and a plurality of slaves, the control is performed such that the data processing in the current slave does not affect the subsequent data processing speed. A flip-flop (3) for receiving a control input (control input) generated from the slave (2) as data using a signal used for the system clock and synchronization as a clock signal, and the flip-flop An output buffer (4) for receiving the output signal of (3) as an enable signal and receiving the input control signal (control input) and outputting an output control signal (control output); Since the chip area for the enable is small and each slave has an individual enable time, arbitration time is unnecessary for the superimposed control signals. After the slave has finished accessing, it is already ready for the next cycle access, reducing the latency between cycles, which speeds up the system.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 본 발명이 적용되는 시스템 구성 블럭도, 제2도는 본 발명에 따른 제어신호 공급 회로도.1 is a block diagram of a system configuration to which the present invention is applied, and FIG. 2 is a control signal supply circuit diagram according to the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950016761A KR970002664A (en) | 1995-06-21 | 1995-06-21 | Control signal supply circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950016761A KR970002664A (en) | 1995-06-21 | 1995-06-21 | Control signal supply circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970002664A true KR970002664A (en) | 1997-01-28 |
Family
ID=66524581
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950016761A KR970002664A (en) | 1995-06-21 | 1995-06-21 | Control signal supply circuit |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970002664A (en) |
-
1995
- 1995-06-21 KR KR1019950016761A patent/KR970002664A/en not_active Application Discontinuation
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Legal Events
Date | Code | Title | Description |
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WITN | Withdrawal due to no request for examination |