KR970000758B1 - Frame rate conversion device combined with video decoder - Google Patents

Abstract

An apparatus, which is connected with a video decoder, for concerting frame rate by a frame compensation is disclosed. The apparatus includes variable length decoding(VLD) and demuliplexing means(12); reverse quantizing means(13) for reverse quantizing a signal from the VLD and demultiplexing means(12); IDCT(Inverse Discrete Cosine Transform) means(14) for IDCTing a signal from the reverse quantizing means(13); motion compensating means(21) for compensating a motion by using a motion information from the VLD and demuliplexing means(12); adding means(18) for adding two signals from each of the IDCT means(14) and the motion compensating means(21); frame memory means(19) for storing the signal from the adding means(18) and for outputting the signal to the motion compensating means(21); and frame rate converting means for converting frame rates of signals from the VLD and demultiplexing means(12) or the IDCT means(14) and the adding means(18).

Description

Frame rate converter combined with video decoder

1 is a block diagram of an image decoder applied to the present invention.

2 is a unit structure diagram of an image signal for coding.

3 is a block diagram of a frame rate converter according to the present invention.

4 is a view showing an embodiment of the frame converter of FIG.

5 is a signal waveform diagram of each part of FIG.

6 is another embodiment of the frame converter of FIG.

7 is a signal waveform diagram of each part of FIG.

FIG. 8 is a detailed configuration diagram of the frame region dividing unit of FIGS. 4 and 6.

9 is an interpolation process diagram through motion compensation of the frame rate converter of FIG.

10 is a frame region division display using an error signal and a macroblock type signal.

11 is a flowchart illustrating a frame interpolation process of the frame rate converter of FIG. 3.

* Explanation of symbols for main parts of the drawings

11 input 12: VLD and demultiplexing unit

13: inverse quantization unit 14: IDCT unit

15,17,22: Latch 16: Totalizer

18: Adder 19: Frame Memory

20 flame rate converter 21: motion compensation unit

The present invention relates to a frame rate converting apparatus combined with an image decoder for converting a frame rate through frame interpolation.

In general, high compression is required to transmit images digitally.

For example, there are multipurpose MPEG II, such as H.261 for teleconferencing, MPEGI for multimedia, digital TV, and HDTV compression methods. To eliminate this problem, we apply the compression method through motion compensation. In the United States, HDTV compression is being studied to be compatible with MPEG II.

In general, in H.261 and MPEG I, in addition to the concept described above, the decimation is performed on the time axis to reduce the frame rate in order to increase the compression rate.

In other words, the compression rate is lowered to 25HZ or 30HZ.

Even if compression is performed as described above, the final display stage must convert the frame rate back to 50HZ or 60HZ.

In US HDTV, Youngsan Source is designing to accommodate various formats.

In particular, it is a rule to accommodate a frame rate of 24HZ or 30HZ which is a film mode.

In the final display stage, it should be converted to 60HZ and displayed on the monitor.

As mentioned earlier, this conversion method must be interpolated with motion compensation to eliminate eye strain.

Accordingly, an object of the present invention is to provide a frame rate conversion apparatus combined with an image decoder for interpolating and converting a frame rate through motion compensation using signals transmitted to the image decoder.

In order to achieve the above object, the present invention provides an inverse quantization using a signal output from the VLD (Variable Length Decoding) and demultiplexing means for restoring and classifying an input bitstream into a meaningful signal. A motion compensating means for compensating motion by using quantization means, IDCT means for processing an inverse discrete cosine transform (IDCT) signal output from the inverse quantization means, and motion information output from the VLD and demultiplexing means, and the IDCT means; Adding means for adding a signal output from the motion compensating means, a frame memory means for storing the signal output from the adding means and outputting the signal to the motion compensating means, and outputting from the VLD and demultiplexing means or IDCT means and adding means. To convert the frame rate to the input signal Frame rate and being composed of converting means.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a block diagram of an image decoder according to an embodiment of the present invention, and FIG. 2 is a unit structure diagram of an image signal for coding, where 1 is an input terminal, 2 is a variable length decoding (VLD) and demultiplexing unit, and 3 is an inverse quantization unit. 4 denotes an inverse discrete cosine transform (IDCT) unit 5, an adder, 6 a frame memory, 7 a motion compensation unit, 8 a frame, 9 a slice, and 10 a macroblock.

As shown in FIG. 1, the image decoder connects an inverse quantizer 3 to a VLD and a demultiplexer 1 to which a compressed bitstream coming through the input terminal 1 is input, and the inverse quantizer ( 3) an IDCT unit 4, a motion compensation unit 7 to the VLD and demultiplexing unit 2, a frame memory 6 to the motion compensation unit 7, and The adder 5 is connected to the frame memory 6 and the IDCT 4, and the frame memory 6 is connected to the output terminal of the adder 5.

The video decoder receives the compressed bitstream, reconstructs it into a meaningful signal in the variable length decoding (VLD) and demultiplexer 2, and classifies the signal into several signals.

The output signal of the VLD and demultiplexing unit 2 passes through an inverse quantization unit and an Inverse Discrete Cosine Transform (IDCT) unit 4, and then combines the signal with the motion compensation signal to compensate for the motion of the next frame. Is stored in the frame memory 6 for this purpose.

Signals output from the VLD and demultiplexing unit 2 may include motion information, macroblock types, quantization levels, coefficient signals, and the like.

As shown in FIG. 2, the basic unit for coding is the macroblock 10. The motion information, the macroblock type signal, etc. are transmitted in the macroblock 10 unit, and the transmitted coefficient is the difference between the frames, It will be an error signal.

The macroblocks 10 are gathered to form a slice 9, and the slices 9 are gathered to form a frame. In the present invention, a slice corresponding to one horizontal whole of the macroblock 10 is defined as a slice.

3 is a block diagram of an apparatus for converting a frame combined with an image decoder according to the present invention, 11 is an input terminal, 12 is a VLD and demultiplexing unit, 13 is an inverse quantization unit, 14 is an Inverse Discrete Cosine Transform (IDCT) unit, 15 , 17 and 22 are latches, 16 are adders, 18 are adders, 19 are frame memories, 20 are frame rate converters, and 21 are motion compensation units.

In the frame rate converting apparatus combined with the image decoder according to the present invention, the inverse quantization unit 13 is connected to the VLD and the demultiplexing unit 12 into which the bitstream is input, as shown in FIG. An IDCT unit 14 is connected to the 13, a latch 22 and a motion compensator 21 are connected to the VLD and the demultiplexing unit 12, and a frame memory is connected to the motion compensator 21. 19), the adder 18 to the frame memory 19 and the IDCT unit 14, the frame memory 19 to the output terminal of the adder 18, the IDCT unit 14 Is connected to the summer 16, the latch 17 is connected to the summer 16, and the latch 15 is connected to the VLD and demultiplexing unit 12.

The VLD and demultiplexing unit 12 receives the compressed bitstream from the input terminal 11, reconstructs it into a meaningful signal, and classifies the signal into several signals.

The inverse quantization unit 13 dequantizes the signal necessary for quantization from the VLD and the demultiplexing unit 12, and the IDCT unit 14 processes the inverse discrete cosine transform (IDCT). do.

In addition, the adder 18 combines the signal output from the IDCT unit 14 with the motion compensated signal, and stores the same in the frame memory 19 to compensate for the motion of the next frame and outputs it to the frame rate converter 20. do.

The latch 15 receives and latches a macroblock type signal from the VLD and demultiplexing unit 12, and the latch 22 receives and latches a motion information signal from the VLD and demultiplexing unit 12. Output to the rate converter 20.

The adder 16 receives an error signal from the IDCT unit 14 and adds the error signal to the latch 17, and the latch 17 latches the signal output from the adder 16 to the frame. Output to the rate converter 20.

That is, the sum signal of the macroblock type, the motion information, and the error signal in the macroblock unit is input to the frame rate converter 20, and the latches 15, 17, and 22 are inputted by the summer 16. The delay caused by calculating the sum of error signals is compensated for and synchronized in units of macroblocks.

FIG. 4 is an internal configuration diagram showing an embodiment of the frame converter 20 of FIG. 3, and FIG. 5 is a signal waveform diagram of each part of FIG. 4, where 23, 24, 25, and 26 are input terminals, 17, 30, 34, 37 and 38 are frame memories, 28 and 33 are 1 / 2-minute periods, 29 and 42 are comparators, 32 are motion compensation interpolators, 32 are adders, 35 are frame area separators, 38 and 39 are multiplexers, and 40 are Delay compensation unit 41 denotes a summer.

As shown in FIG. 4, the frame converter 20 connects another frame memory 30 to a frame memory 27 that receives a signal output from the adder 18, and the frame memory 27 And an output terminal of the comparator 29 to which an adder 32 is connected to the adder 32, a 1/2 divider 33 is connected to the adder 32, and an error signal and a threshold are input from the latch 17. Dividing the macro block type signal input terminal 26 input from the latch 15, the macro block type signal input terminal 26 input from the latch 15, and the motion information signal input from the latch 22 into 1/2 The output terminal of the 1/2 divider 28 is connected to the input terminal of the frame region divider 35, and the 1/2 divider 28, the frame region divider 35, and the frame memory 27 move. The compensation part interpolator 31 is connected, and the frame memory 34 is connected to the motion compensation part interpolator 31. ), A multiplexer 36 is connected to the frame memories 27, 30, 34, 1/2 divider 33, and frame region separator 35, and a frame memory is connected to the frame memory 27. (37), a frame memory (38) to the multiplexer (36), a summer (41) to the comparator (29), and a comparator at the output and threshold input of the summer (41). And a delay compensator 40 connected to the comparator 42 and a multiplexer 39 connected to the frame memories 37 and 38 and the delay compensator 40.

The output signal of the decoder is stored in the frame memory 27, and the motion information signal is shifted by half by dividing in half frequency divider 28, and the error signal is thresholded in the comparator 29. And the output signal and the macroblock type signal of the comparator 29 are input to the frame region separator 35 to distinguish the frame region.

The frame region divided by the frame region separator 35 is a stop, a covered region, an uncovered region, and a motion compensator.

If the frame area is a motion compensator, the frame area divider 35 controls the multiplexer 36 so that the divided motion information is input to the motion compensator interpolator 31 to move by half of the actual motion. The signal is interpolated to select a signal stored and output in the frame memory 34.

If the frame area divided by the frame area divider 35 is a stop, the frame area divider 35 is configured to control the interpolation of the signals passing through the frame memories 27 and 30 so that the frame area divider 35 can interpolate to an average value of both frames. The selection of the multiplexer 36 is controlled such that the output of the half divider 33 which is an average is output.

If the frame area divided by the frame area divider 35 is an open portion, the frame area divider 35 outputs a signal of the previous frame, that is, the output of the frame memory 27 so that it is read from the previous frame. The selection of the multiplexer 36 is controlled to be output.

Since the compensation operation is performed for one frame period, delay compensation is necessary.

Therefore, the output of the frame memory 27 is subjected to delay compensation through the frame memory 30 again and interpolated according to the above-mentioned various areas.

The signal output by selecting the interpolation method suitable for the region as described above is stored in the frame memory 38 through the multiplexer 36, and the input signal of the previous frame, that is, the signal stored in the frame memories 37 and 38, is The multiplexer 39 converts the final output form.

That is, the data is read twice in one frame period of input, and the outputs of the frame memories 37 and 38 are read alternately in one frame period. The signal waveforms of the respective parts are shown in FIG.

The output of the comparator 29 is input to the summer 41, the output is again compared with a threshold at the comparator 42, and the result is input to the delay compensator 40 to provide the multiplexer 39. Control the selection.

That is, if the number of macroblocks in which the error signal is larger than a certain threshold is greater than a certain threshold in one frame, it is determined that a scene change has occurred and the output of the frame memory 38 that is the interpolated frame is selected by the multiplexer 39. Instead, it adjusts so that only the output of the frame memory 37 is repeatedly selected twice.

FIG. 6 is a detailed block diagram showing another embodiment of the frame rate converter 20 of FIG. 4, and FIG. 7 is a signal waveform of each part of FIG. 6, and 53, 54, 55, 56 are input terminals 57, 60, 65 is frame memory, 58, 62 is 1/2 divider, 59, 70 is comparator, 61 is adder, 363 is motion compensation interpolation, 64 frame area divider, 66, 68 is multiplexer, 67 is summer, 69 denotes a delay compensator, respectively.

The frame rate converter 20 connects the frame memory 57 to a frame memory 57 which receives a signal output from the adder 18 as shown in FIG. An adder 61 is connected to an output terminal of 58, a 1/2 divider 62 is connected to the adder 61, and an input terminal 54 to which a motion information signal output from the latch 22 is input. A 1/2 divider 56 is connected, a comparator 59 in which a threshold value is input to an input terminal to which an error signal input from the latch 17 is input, and a 1/2 divider 58 and a comparator are connected. A frame area divider 64 is connected to an input terminal 56 to which a macroblock type signal is input from the 59 and the latch 15, and the 1/2 divider 58 and the frame area divider 64 are connected. And a motion compensation part interpolator 63 to the frame memory 60, and a frame method to the motion compensation part interpolator 63. A multiplexer 66 to a frame memory 57, 60, 65, a 1/2 divider 62, and a frame region divider 64, and to the comparison 59. A summer 67 is connected, a comparator 70 having a threshold value input thereto is connected to the summer 67, a delay compensator 69 is connected to the comparator 70, and the delay compensator 69 is connected to the comparator 70. By connecting the multiplexer 68 to the frame memory 60 and the multiplexer 66, the number of frame memories can be reduced by operating at an output frame rate rather than an input rate.

That is, one frame is repeatedly read twice during one frame period of input, and is stored in another frame memory 60 one frame later and then read at twice the speed.

The output signal of the decoder is stored in the frame memory 57, and the motion information signal is divided by half in two divisions 58 and moved only by half. The error signal is compared with a threshold in the comparator 59. Compared with each other, the output signal and the macroblock type signal of the comparator 59 are input to the frame region separator 64 to distinguish the frame region.

The operations and processes of the frame area divider 64 and the operations and processes of the adder 67, the comparator 70, and the delay compensator 69 are the same as those of the frame rate converter 20.

The signal output from the multiplexer 66 and the signal output from the frame memory 60 are finally output directly through the multiplexer 68 without passing through the frame memory.

That is, during the half frame period of the input, the motion compensation part is interpolated, stored in the frame 65 and read out, and at the same time, the inter-frame average, that is, the output of the half frequency divider 62 and the value read in the previous frame, are synchronized. The values read from the frames, and, are input to the multiplexer 66.

In addition, the frame region separator 64 selects one of the inputs corresponding to the region from the input of the multiplexer 66 and inputs it to the rear multiplexer 68 by using a macroblock type signal, an error signal, and motion information. .

In addition, an input signal stored in the frame memory 60 is also input to the multiplexer 68 to select an input frame during the first half frame period of the input and output the multiplexer 66 during the remaining half frame period, that is, an interpolated frame. To select it.

Also, the multiplexer 68 is adjusted to repeatedly select an input frame twice without selecting an interpolated frame if a scene change occurs by calculating the number of macroblocks in which the error signal is larger than a threshold in units of frames. .

Signal waveforms showing the operation of the frame rate converter 20 operating as described above are shown in FIG.

First, when the macroblock type signal is Motion Compensated and the error signal is smaller than the threshold value, the motion compensation area is determined as the motion compensation area only when the signal is 48 and the motion information is transferred to the motion compensation area recording unit 49 using the motion information. The recorded memory output is combined with the delay compensated macroblock type signal to be judged by the final multiplexer selection control unit 50 to select one of the inputs of the multiplexers 36 and 66.

8 is a detailed configuration diagram of the frame area separators 35 and 64 of FIGS. 4 and 6, where 43, 44, and 45 are input terminals, 46 is a macroblock type classification unit, 47 and 51 are delay compensation units, and An AND gate, 49 denotes a motion compensation region recording unit, 50 denotes a multiplexer selection control unit, and 52 denotes an inverter.

The frame area separators 35 and 64 connect the macroblock type classifier 46 to the input terminal 43 to which the macroblock type signal is input, as shown in FIG. 8, and the comparators 29 and 59. Inverter 52 is connected to an input terminal 44 through which an error path is inputted, a delay compensator 47 is connected to the macroblock type classification unit 46 and the inverter 52, and the inverter 52 is connected. And an AND terminal 48 connected to the macroblock type classification unit 46, and an input terminal 45 to which a motion information signal output from the AND gate 48 and the 1/2 dividers 28 and 58 is input. A motion compensation region recorder 49, a multiplexer 36, 66, and a selection controller 50 to the delay compensator 47 and the motion compensation region recorder 49. The delay compensator 51 is connected to the unit 50, and the output of the AND gate 48 is output to the motion compensation interpolators 31 and 63. It constitutes connected to.

The macroblock type signal is transmitted from the macroblock type classification unit 46 to an intra-frame, motion-compressed, and non-motion-compressed interframe. It is classified and input to the delay compensator 47.

The delay portion 47 is controlled by the signal inverting the error signal, and the motion and non-motion signal of the macro block type signal is logic at the AND gate 48 together with the output signal of the inverter 52. Multiplied and output to the motion compensation region recording unit 49, and output to the multiplexer selection control unit 50 in accordance with the control of the motion information signal, the multiplexer selection control unit 50 is the macroblock type classification unit 46 The delay compensation unit 47 outputs the delay compensated signal from the delay compensation unit 47 to the delay compensation unit 51 according to the output of the motion compensation region recording unit 49.

First, when the macroblock type signal is Motion Compensated and the error signal is smaller than the threshold value, the motion compensation area is determined to be a motion compensation area (48) only. The recorded memory output is combined with the delay compensated macroblock type signal to be judged by the final multiplexer selection control unit 50 to select one of the inputs of the multiplexers 36 and 66.

9 is an interpolation process diagram through motion compensation of the frame rate converter 20 of FIG. 3.

In the case of inserting a frame through motion compensation, as shown in FIG. 9, the area of the frame to be interpolated is searched and interpolated into several areas.

That is, the motion compensator with unchanged stop motion exists between both frames (n ^ht and (n + 1) ^th ), and is hidden behind as the moving part moves to the next frame ((n + 1) ^th ). It is classified as a Covered Region that appears and an Uncovered Region that is covered as the moving part moves to the next frame ((n + 1) ^th ).

By replacing the classification stop unit if both the average inter-frame or front or the rear frame in the manner described above, if the motion compensator is part binary interpolation using the motion information, and covered reading in the next frame ((n + 1) ^th) Interpolation is performed with the ON signal, and in the case of an open denial, interpolation is performed using a signal read from the previous frame n ^th .

FIG. 10 is a frame region classification indicator using an error signal and a macroblock type signal. Referring to FIG. 10, a method of classifying frame regions is as follows.

If the error signal is larger than a certain threshold, it is determined as an open area unconditionally. If the error signal is smaller than the threshold, the signal is classified according to the macroblock type signal.

That is, if it is indicated that the macroblock type signal is an intra frame coding mode, it is determined to be open, and if it is indicated to be a motion compensated inter frame mode, it is determined as a stop.

FIG. 11 is a flowchart illustrating a frame interpolation process of the frame rate converter 20 of FIG. 3. Referring to FIG. 11, the frame interpolation process is described below.

First, it is searched whether the error is equal to or greater than the set threshold (100). If the threshold is greater than or equal to the threshold, the previous frame (n ^th ) is read (107).

If it is still, interpolate to the average value of both frames (102), if not, search for macroblock type intra frame mode (103); if it is intra frame mode, read from the previous frame (n ^th ); Search if it is a covered area (104).

If it is a covered area, it reads from the rear frame ((n + 1) ^th ) (105). If not, it performs interpolation through motion compensation (106).

The present invention constructed and operated as described above has an effect of easily interpolating frames by dividing frame regions by using error signals output from a decoder, and can be efficiently applied to HDTV receivers, video phones, video conferencing systems, and multimedia. Can be.

Claims (10)

Dequantization means for inverse quantization by using a signal output from the VLD (Variable Length Decoding) and the demultiplexing means 12 and the VLD and the demultiplexing means 12 for restoring and classifying the input bitstream into a meaningful signal ( 13) the motion is compensated by using the motion information output from the IDCT means 14, the VLD and the demultiplexing means 12, which process an IDCT (Inverse Discrete Cosine Transform) signal output from the inverse quantization means (13). The motion compensating means 21, the adding means 18 for adding the signals output from the IDCT means 14 and the motion compensating means 12, the signal output from the adding means 18, and storing the motion compensation. A frame memory means 19 for outputting to the means 21, the VLD and demultiplexing means or a signal output from the IDCT means and the adding means 18 for converting the frame rate into an input; Frame rate conversion apparatus combined with a video decoder, characterized in that the frame rate conversion means 20. 2. The frame rate converter (20) according to claim 1, wherein the frame rate converting apparatus (20) receives the first frame memory (27) and the output signal of the first frame memory (27) as inputs. The second frame memory 30, the adder 32 for outputting an average signal of the output signals of the first and second frame memories 27 and 30, the first and second dividers 33, and the motion information are inputted. And divided second 1/2 divider 28, the first comparator 29 to compare the error signal and the set threshold, the output signal of the first comparator 29 and the second 1/2 divider 28 And a frame area classification means 35 for dividing the frame area by inputting a macroblock type signal, and outputted from the first frame memory 27, the second 1/2 divider 28, and the frame area classification means 35. The output signal of the motion compensation part interpolation means 31 and the motion compensation part interpolation means 31 which interpolate through motion compensation by using the signal. Means for outputting the output signals of the third frame memory 34, the first, second and third frame memories 27, 30, 34 and the first 1/2 divider 33 Output of the first multiplexer 36 to select and output under the control of (35), the fourth frame memory 37 to input the output signal of the first frame memory 27, and the first multiplexer 36 A fifth frame memory 38 for inputting a signal, an adder 41 for adding up the output signals of the first comparator 29, and an output signal for comparing the output signal of the adder 41 with a set threshold value; The second comparator 42, the delay compensator 40 which takes an output of the second comparator 42 as an input, and outputs the output signals of the fourth and fifth frame memories 37 and 38 to the delay compensator 40. And a second multiplexer (39) for selecting and outputting according to the control of the frame rate converter. The frame rate converter (20) according to claim 1, wherein the frame rate converting apparatus (20) receives the first frame memory (57) and the output signal of the first frame memory (57) as inputs. The second frame memory 60, an adder 61 for outputting an average signal of the output signals of the first and second frame memories 57 and 60, and a first 1/2 divider 62, A second 1/2 divider 58 input and divided, an output of a first comparator 59 for comparing an error signal with a set threshold, and outputs of the first comparator 59 and the second 1/2 divider 58 A frame region discriminating means 64 for dividing a signal and a macroblock type signal into a frame region, and an output signal of the second frame memory 57 and the second 1/2 divider 58 and the frame region discriminating means 64; By using the motion compensation part interpolation means 63 interpolating through motion compensation, the output signal of the motion compensation part interpolation means 63 as an input Output signals of the three-frame memory 65, the first, second, and third frame memories 57, 60, 65 and the first and second dividers 62 are controlled by the frame area discriminating means 35. A second multiplexer 66 that selects and outputs the first multiplexer 66, an adder 67 that sums the output signals of the first comparator 59, and a second threshold that compares the output signal of the adder 67 with a predetermined threshold value as an input; The delay compensator 69 receives the output of the comparator 70, the second comparator 70 as an input, and outputs the output signals of the first multiplexer 66 and the second frame memory 60. And a second multiplexer (68) for selecting and outputting the control unit according to the control of the control unit. The apparatus of claim 2 or 3, wherein the frame area is divided into a stop part, a motion compensator, an open part, and a covered part. The inverter of claim 4, wherein the frame area discriminating means (35, 64) comprises an inverting means for inverting the output signal of the macro block type sorting means (46) and the first comparators (29, 59) into which the macro block type signal is input. 52), the first delay compensation means 47 for inputting the output signal of the macroblock type sorting means 46 and the inverter 52, the output signal of the inverter 52 and the macroblock type sorting means 46. Logical multiplication means (48) for inputting a motion signal outputted from the above, motion compensation area recording means (49) for inputting the logical multiplication means (48) and the motion information signal, and the first delay compensation means (47). And the output of the multiplexer selection adjusting means 50 and the multiplexer selecting adjusting means 50 for outputting a signal for controlling the selection of the multiplexers 36 and 66 by inputting the output signal of the motion compensation region recording means 49 as an input. To the second delay compensation means 51 for inputting a signal. Frame rate converter coupled to the video decoder, characterized in that configured. 5. The frame rate of claim 4, wherein the stop part has an error signal smaller than a predetermined threshold and the macroblock type is a non-motion-compressed inter-frame mode. Inverter. 5. The video decoder of claim 4, wherein the motion compensator is an area in which an error signal is smaller than a predetermined threshold, and a macroblock type is a motion-compensated mode and requires interpolation through motion compensation. 6. Frame rate inverter. The frame coupled to an image decoder according to claim 4, wherein the open part is an area in which an error signal is less than a set threshold and the macroblock type is an intra-frame mode or the error signal is larger than a set threshold. Rate inverter. 5. The apparatus of claim 4, wherein the covered portion is an area in which an error signal is smaller than a set threshold and the macroblock type is a motion-complied mode and no motion. The method of claim 5, wherein the multiplexer selection adjusting means (50) replaces the average between the two frames, the front frame (n ^th ), or the rear frame ((n + 1) ^th ) when the frame area is a stationary part. If the frame area is a motion compensation part, interpolation is performed using motion information. If the frame area is a covered part, interpolation is performed using a signal read from a rear frame ((n + 1) ^th ), and the frame in front of the open part surface ( and n ^th ) controlling the selection of the first multiplexer (36,66) to interpolate using the signal read from n ^th ).