KR960042416A - Max value selection circuit - Google Patents

Max value selection circuit Download PDF

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Publication number
KR960042416A
KR960042416A KR1019950011778A KR19950011778A KR960042416A KR 960042416 A KR960042416 A KR 960042416A KR 1019950011778 A KR1019950011778 A KR 1019950011778A KR 19950011778 A KR19950011778 A KR 19950011778A KR 960042416 A KR960042416 A KR 960042416A
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KR
South Korea
Prior art keywords
signal
maximum value
unit
carry
bit
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KR1019950011778A
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Korean (ko)
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KR0156152B1 (en
Inventor
박성휘
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문정환
Lg 반도체주식회사
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Priority to KR1019950011778A priority Critical patent/KR0156152B1/en
Priority to US08/644,417 priority patent/US5721809A/en
Priority to JP13974496A priority patent/JP3198379B2/en
Publication of KR960042416A publication Critical patent/KR960042416A/en
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Publication of KR0156152B1 publication Critical patent/KR0156152B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/02—Comparing digital values
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation

Abstract

본 발명은 최대값 선택회로에 관한 것으로, 특히 다수의 입력신호를 동시에 비교 처리하여 지연시간의 단축과 고속데이터 처리에 적당하도록 한 최대값 선택회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a maximum value selection circuit, and more particularly, to a maximum value selection circuit that is suitable for shortening delay time and high-speed data processing by comparing a plurality of input signals simultaneously.

이를 위한 본 발명의 최대값 선택회로는 n배트로 된 m개의 2진수 중 최대값을 선택하는 최대값 선택회로에 있어서, m개의 2진수의 단위비트와 캐리신호를 각각 비트단위로 비교하여 얻은 최대값 지성신호를 그 다음 하위비트의 캐리신호로 출력하도록 직렬접속되는 n개의 단위비트 병렬비교기와, 상기 최하위 비트의 단위비트 병렬비교기(7n)에서 출력되는 최대값 지성신호에 따라 입력되는 m개의 2진수 중에 최대값을 최종적으로 출력하는 멀티플렉서를 포함하여 구성된 것이다.The maximum value selection circuit of the present invention is a maximum value selection circuit for selecting the maximum value of m binary numbers of n batts, and the maximum value obtained by comparing the unit bits of the m binary numbers and the carry signal with each bit unit. N unit bit parallel comparators connected in series to output the value intelligence signal as a carry signal of the next lower bit, and m 2 inputs according to the maximum value intelligence signal output from the least significant unit bit parallel comparator 7n. It consists of a multiplexer that finally outputs the maximum value during launch.

Description

최대값 선택회로Max value selection circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 최대값 선택회로의 구성블럭도, 제4도는 본 발명에 따른 단위비트 병렬비교기를 나타낸 회로도.3 is a block diagram of a maximum value selection circuit of the present invention, and FIG. 4 is a circuit diagram showing a unit bit parallel comparator according to the present invention.

Claims (5)

n비트로된 m개의 12진수 중 최대값을 선택하는 최대값 선택회로에 있어서, m개의 2진수의 단위비트와 캐리신호를 각각 비트단위로 비교하여 얻은 최대값 지성신호를 그 다음 하위비트의 캐리신호로 출력하도록 직렬접속되는 n개의 단위비트 병렬비교기와, 상기 최하위 비트의 단위비트 병렬비교기(7n)에서 출력되는 최대값 지성신호에 따라 입력되는 m개의 2진수 중에 최대값을 최종적으로 출력하는 멀티플렉서를 포함하여 구성됨을 특징으로 하는 최대값 선택회로.A maximum value selecting circuit for selecting the maximum value of m digits of n bits, wherein the maximum value intelligence signal obtained by comparing m binary unit bits and carry signals in bit units, respectively, is the next lower bit carry signal. A n-bit parallel comparator serially connected to output a signal and a multiplexer for finally outputting a maximum value out of m binary numbers input according to a maximum-value intelligence signal output from the least-bit unit bit parallel comparator 7n. Maximum value selection circuit comprising a. 제1항에 있어서, 각 단위비트 병렬비교기는 m개의 n비트 2진수의 각 단위비트 입력값을 논리합 연산하여 출력하는 제1노아 게이트와, 상기 입력되는 캐리값을 논리합 연산하여 출력하는 제2노아 게이트와, 상기 제1, 제2노아 게이트의 출력신호와 2진수의 단위비트 및 해당 캐리신호를 1차 논리연산하고 그 결과와 그밖의 다른 m-1개의 단위비트와 캐리신호들을 2차 논리연산하여 단위비트중 최대값임을 지정하여 출력하는 m개의 논리 연산부로 구성됨을 특징으로 하는 최대값 선택회로.The apparatus of claim 1, wherein each of the unit bit parallel comparators comprises: a first NOR gate for performing an OR operation on each of the unit bits input values of m n-bit binary numbers, and a second NOR for performing an OR operation on the input carry value. First-order logic operation on the gate, the output signals of the first and second Noah gates, the unit bits of the binary number, and the corresponding carry signal, and the second-order logic operation on the resultant and other m-1 unit bits and carry signals. The maximum value selection circuit, characterized in that it consists of m logic operation unit outputting by specifying the maximum value of the unit bit. 제2항에 있어서, 제1, 제2노아 게이트 및 각 논리연산부는 해당 단위비트와 해당 캐리신호가 동시에 "1"이면 다른 입력단에 입력되는 단위비트 및 캐리신호에 관계없이 최대값 지성신호(Am)로 "1"를 출력하고, 해당 단위비트가 "1"이고, 해당 캐리신호가 "0"일때는 다른 입력단에 입력되는 캐리 입력이 하나라도 "1"이면 최대값 지성신호로 "0"를 출력하고, 다른 입력단의 캐리 입력이 모두 "0"이면 최대값 지성신호로 "1"를 출력하며, 해당 단위비트가 "0"이고 해당 캐리신호가 "1"일때는 다른 단위비트 이벽값과 캐리 입력이 동시에 "1"일 경우 최대값 선택신호로 "0"를 출력하고, 다른 단위비트 입력값과 캐리 입력이 동시에 "1"이 되지 않으면 최대값 지성신호로 "1"를 출력하고, 해당 단위비트가 "0"이고 해당 캐리신호가 "0"일때는 다른 모든 단위비트는 입력값과 캐리 입력이 "0"일 경우에만 최대값 지성신호로 "1"를 출력하고, 다른 모든 단위비트 입력값과 캐리 입력 중 하나라도 "1"인 경우에는 최대값 지성신호로 "0"를 출력하도록 구성됨을 특징으로 하는 최대값 선택회로.The intelligent signal signal of claim 2, wherein the first and second NOR gates and the logic operation unit are each configured to have a maximum intelligence signal Am regardless of the unit bit and the carry signal input to the other input terminal when the corresponding unit bit and the carry signal are simultaneously "1". Outputs "1", and if the corresponding unit bit is "1" and the corresponding carry signal is "0", if one carry input is input to other input terminal "1", the maximum value intelligence signal is set to "0". If the carry inputs of other input terminals are all "0", it outputs "1" as the maximum value intelligence signal. If the corresponding unit bit is "0" and the carry signal is "1", the other unit bit wall value and carry If the input is "1" at the same time, it outputs "0" as the maximum value selection signal. If the other unit bit input value and the carry input are not "1" at the same time, it outputs "1" as the maximum value intelligence signal. If bit is "0" and the corresponding carry signal is "0", all other unit bits are It is configured to output "1" as the maximum value intelligence signal only when the input is "0", and to output "0" as the maximum value intelligence signal when any one of all other unit bit input values and the carry input is "1". Maximum value selection circuit, characterized in that. 제3항에 있어서, 5개의 n비트 2진수의 단위비트를 A, B, C, D, E라 하고, 해당 캐리값을 Ac, Bc, Cc, Dc, Ec라 할 때, 제1, 제2노아게이트 및 각 논리연산부는 의 논리값을 갖도록 구성됨을 특징으로 하는 최대값 선택회로.The method according to claim 3, wherein the unit bits of five n-bit binary numbers are A, B, C, D, and E, and the carry values are Ac, Bc, Cc, Dc, and Ec. Noah gate and each logical operation part Maximum value selection circuit, characterized in that configured to have a logic value of. 제2항에 있어서, 각 논리연산부는 상기 제1노아 게이트의 출력과 일 단위비트의 입력값을 논리 연산하여 출력하는 제1오아 게이트와, 상기 제1오아 게이트의 출력신호와 상기 제2노아 게이트의 출력신호를 논리 연산하여 출력하는 제1앤드 게이트와, 상기 일 단위비트 입력값과 해당 캐리값을 논리 연산하여 출력하는 제1낸드 게이트와, 상기 제1낸드 게이트의 출력을 반전시키는 인버터와, 상기 해당 논리연산부의 제1낸드 게이트의 출력신호를 제외한 다른 논리연산부의 제1낸드 게이트의 출력신호와 상기 해당 논리연산부의 캐리입력 신호를 논리연산하는 제2앤드 게이트와, 상기 제1앤드 게이트, 상기 인버터 및 상기 제2앤드 게이트의 출력신호를 논리 연산하여 출력하는 제2오아 게이트로 구성됨을 특징으로 하는 최대값 선택회로.3. The logic circuit of claim 2, wherein each logic operation unit comprises: a first or gate gate configured to logically output an output value of the first node gate and an input value of one unit bit, an output signal of the first or gate gate, and the second node gate; A first end gate for performing a logic operation on the output signal of the first and second gates, a first NAND gate for performing a logic operation on the one-bit input value and a carry value, and an inverter for inverting the output of the first NAND gate; A second end gate for performing a logic operation on the output signal of the first NAND gate of the other logic operation unit except the output signal of the first NAND gate of the logic operation unit and the carry input signal of the logic operation unit, the first end gate, And a second OR gate configured to logically output an output signal of the inverter and the second AND gate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950011778A 1995-05-12 1995-05-12 Maximum value selecting circuit KR0156152B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019950011778A KR0156152B1 (en) 1995-05-12 1995-05-12 Maximum value selecting circuit
US08/644,417 US5721809A (en) 1995-05-12 1996-05-10 Maximum value selector
JP13974496A JP3198379B2 (en) 1995-05-12 1996-05-10 Maximum value selection circuit

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JPH08339291A (en) 1996-12-24
US5721809A (en) 1998-02-24
KR0156152B1 (en) 1998-11-16
JP3198379B2 (en) 2001-08-13

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