KR960030009A - Communication device using shared memory - Google Patents

Communication device using shared memory Download PDF

Info

Publication number
KR960030009A
KR960030009A KR1019950000767A KR19950000767A KR960030009A KR 960030009 A KR960030009 A KR 960030009A KR 1019950000767 A KR1019950000767 A KR 1019950000767A KR 19950000767 A KR19950000767 A KR 19950000767A KR 960030009 A KR960030009 A KR 960030009A
Authority
KR
South Korea
Prior art keywords
signal
central processing
level
processing means
control signal
Prior art date
Application number
KR1019950000767A
Other languages
Korean (ko)
Other versions
KR0165505B1 (en
Inventor
서호석
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950000767A priority Critical patent/KR0165505B1/en
Publication of KR960030009A publication Critical patent/KR960030009A/en
Application granted granted Critical
Publication of KR0165505B1 publication Critical patent/KR0165505B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

본 발명은 공유메모리를 사용한 통신장치를 공개한다. 그 장치는 소정의 비트들로 구성된 제1주소를 발생하고, 제1대기신호가 제1레벨인 경우에만 데이타를 전송 및 수신하는 제1중앙처리수단과, 소정의 비트들로 구성된 제2주소를 발생하고, 제2대기신호가 제1레벨인 경우에만 데이타를 전송 및 수신하는 제2중앙처리수단과, 제1제어신호가 제2레벨이면 제1중앙처리수단과 데이타를 엑세스할 수 있고, 제2제어신호가 제2레벨이면 제2중앙처리수단과 데이타를 엑세스할 수 있고, 제2중앙처리수단과 엑세스할 경우, 제1상태신호를 발생하고, 제1중앙처리수단과 엑세스할 경우, 제2상태신호를 발생하는 공유메모리수단과, 제1 및 제2주소와, 제1 및 제2상태신호를 입력하여, 주소들이 같은 경우, 제1중앙처리수단과 제2중앙처리수단 사이의 데이타 전송을 원활히 하기 위해서 제1 및 제2제어신호들과, 제1 및 제2대기신호들을 발생하는 통신제어수단을 구비하는 것을 특징으로 하고, 데이타 통신 방식에 있어서, 8비트 데이타 버스를 통해 16비트 이상의 데이타를 주고 받기 위해서는 플레그(Flag)를 이용한 프로토콜(protocol) 또는 어떠한 형태의 프로토콜이 필요없이 프로토콜을 사용하지 않고도 16비트 크기의 데이타를 두 중앙처리장치간에 데이타의 충돌이나 오류없이 주고 받을 수 있는 효과가 있다.The present invention discloses a communication device using a shared memory. The apparatus generates a first address composed of predetermined bits, and includes first central processing means for transmitting and receiving data only when the first standby signal is at a first level, and a second address composed of predetermined bits. Second central processing means for transmitting and receiving data only when the second standby signal is at a first level, and when the first control signal is at a second level, the first central processing means and data can be accessed. When the second control signal is at the second level, the second central processing means and the data can be accessed, and when accessing with the second central processing means, a first status signal is generated, and when the second central processing means is accessed, Shared memory means for generating a two-state signal, first and second addresses, and first and second state signals are inputted, and if the addresses are the same, data transfer between the first central processing means and the second central processing means. The first and second control signals and the first and second standby And a communication control means for generating signals, and in a data communication method, a protocol or any form of protocol using a flag to send and receive data of 16 bits or more through an 8-bit data bus. Without this protocol, 16-bit data can be exchanged between two CPUs without data collision or error.

Description

공유메모리를 사용한 통신 장치Communication device using shared memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제6도는 제5도에 도시된 본 발명에 의한 공유메모리를 사용한 통신장치의 세부적인 블럭도이다.6 is a detailed block diagram of a communication apparatus using a shared memory according to the present invention shown in FIG.

Claims (6)

공유메모리를 사용한 통신 장치에 있어서, 소정의 비트들로 구성된 제1주소를 발생하고, 제1대기신호가 제1레벨인 경우에만 데이타를 전송 및 수신하는 제1중앙처리수단; 소정의 비트들로 구성된 제2주소를 발생하고, 제2대기신호가 상기 제1레벨인 경우에만 상기 데이타를 전송 및 수신하는 제2중앙처리수단; 제1제어신호가 제2레벨이면 상기 제1중앙처리수단과 상기 데이타를 엑세스할 수 있고, 제2제어신호가 상기 제2레벨이면 상기 제2중앙처리수단과 상기 데이타를 엑세스 할 수 있고, 상기 제2중앙처리수단과 엑세스 할 경우, 제1상태신호를 발생하고, 상기 제1중앙처리수단과 엑세스 할 경우, 제2상태신호를 발생하는 공유메모리수단; 상기 제1 및 제2주소와, 상기 제1 및 제2상태신호를 입력하여, 상기 주소들이 같은 경우, 상기 제1중앙처리수단과 상기 제2중앙처리수단 사이의 데이타 전송을 원활히 하기 위해서 상기 제1 및 제2제어신호들과, 상기 제1 및 제2대기신호들을 발생하는 통신제어수단을 구비하는 것을 특징으로 하는 공유메모리를 사용한 통신장치.A communication apparatus using a shared memory, comprising: first central processing means for generating a first address consisting of predetermined bits and transmitting and receiving data only when the first standby signal is at a first level; Second central processing means for generating a second address consisting of predetermined bits and transmitting and receiving the data only when the second standby signal is at the first level; The first central processing means and the data can be accessed when the first control signal is at the second level. The second central processing means and the data can be accessed when the second control signal is at the second level. Shared memory means for generating a first state signal when accessing the second central processing means and generating a second state signal when accessing the first central processing means; Inputting the first and second addresses and the first and second status signals, and if the addresses are the same, to facilitate data transfer between the first central processing means and the second central processing means. And first and second control signals and communication control means for generating the first and second standby signals. 제1항에 있어서, 상기 통신제어수단은 상기 제1 및 제2주소를 입력하여 비교후 같으면 제3제어신호를 발생하는 주소비교수단; 상기 제1주소를 입력하여 복호화한 후에 제4제어신호를 발생하는 제1디코더수단; 상기 제2주소를 입력하여 복호화한 후에 제5제어신호를 발생하는 제2디코더수단; 상기 제4제어신호에 응답하여 상기 제1주소중 임의의 비트를 입력하여, 제3상태신호를 발생하는 제1상태수단; 상기 제5제어신호에 응답하여 상기 제2주소중 임의의 비트를 입력하여 제4상태신호를 발생하는 제2상태수단; 상기 제1,2,3 및 4상태신호와, 상기 제3,4 및 제5제어신호를 입력하여 상기 제1 및 제2대기신호 및 상기 제1 및 제2제어신호들을 출력하는 신호발생수단을 구비하는 것을 특징으로 하는 공유메모리를 사용한 통신장치.2. The apparatus of claim 1, wherein the communication control means comprises: address comparison means for generating a third control signal if the first and second addresses are equal and after comparison; First decoder means for generating a fourth control signal after inputting and decoding the first address; Second decoder means for generating a fifth control signal after inputting and decoding the second address; First state means for generating a third state signal by inputting an arbitrary bit of the first address in response to the fourth control signal; Second state means for generating a fourth state signal by inputting an arbitrary bit of the second address in response to the fifth control signal; Signal generating means for inputting the first, second, third and fourth state signals and the third, fourth and fifth control signals to output the first and second standby signals and the first and second control signals; Communication device using a shared memory, characterized in that provided. 제1항에 있어서, 상기 제1제어신호는 상기 제3제어신호와 상기 제4상태신호가 모두 상기 제2레벨인 경우에는 상기 제1레벨로 되는 것을 특징으로 하는 공유 메모리를 사용한 통신장치.The communication apparatus according to claim 1, wherein the first control signal is set to the first level when both the third control signal and the fourth state signal are at the second level. 제1항에 있어서, 상기 제2제어신호는 상기 제3제어신호와 상기 제3상태신호가 모두 상기 제2레벨인 경우에는 상기 제1레벨로 되는 것을 특징으로 하는 공유메모리를 사용한 통신장치.The communication apparatus according to claim 1, wherein the second control signal becomes the first level when both the third control signal and the third state signal are the second level. 제1항에 있어서, 상기 제1대기신호는 상기 제4제어신호와, 상기 제4상태신호와, 상기 제3제어신호가 상기 제2레벨인 경우에만 상기 제2레벨로 되는 것을 특징으로 하는 공유메모리를 사용한 통신장치.The share of claim 1, wherein the first standby signal is set to the second level only when the fourth control signal, the fourth state signal, and the third control signal are the second level. Communication device using memory. 제1항에 있어서, 상기 제2대기신호는 상기 제5제어신호와, 상기 제3상태신호와, 상기 제3제어신호가 상기 제2레벨인 경우에만 상기 제2레벨로 되는 것을 특징으로 하는 공유메모리를 사용한 통신장치.The share of claim 1, wherein the second standby signal is set to the second level only when the fifth control signal, the third state signal, and the third control signal are at the second level. Communication device using memory. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950000767A 1995-01-18 1995-01-18 The communication apparatus using shared memory KR0165505B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950000767A KR0165505B1 (en) 1995-01-18 1995-01-18 The communication apparatus using shared memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950000767A KR0165505B1 (en) 1995-01-18 1995-01-18 The communication apparatus using shared memory

Publications (2)

Publication Number Publication Date
KR960030009A true KR960030009A (en) 1996-08-17
KR0165505B1 KR0165505B1 (en) 1999-01-15

Family

ID=19406874

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950000767A KR0165505B1 (en) 1995-01-18 1995-01-18 The communication apparatus using shared memory

Country Status (1)

Country Link
KR (1) KR0165505B1 (en)

Also Published As

Publication number Publication date
KR0165505B1 (en) 1999-01-15

Similar Documents

Publication Publication Date Title
KR850006652A (en) Integrated circuits with embedded processes and memory and systems using them
KR850007129A (en) Microcomputer system with bus control
KR900003756A (en) Communication systems
KR970071302A (en) Programmable Read / Write Access Signals from Processors and Methods of Forming The Signals
KR960035290A (en) Method and apparatus for bus loading distribution in a data processing system
KR970029768A (en) Semiconductor memory device with block write function
KR960030009A (en) Communication device using shared memory
KR970031616A (en) Communication system for selectively using multiple communication transmission methods
WO2000017757A3 (en) Redundant form address decoder for memory system
KR900005421B1 (en) Bus system for selective communication of data
KR920013146A (en) Fieldbus Interface Board
KR890005154B1 (en) Quod-watt chip selecting circuit
KR100243185B1 (en) Data communication system between processors using shared memory
KR100308146B1 (en) Method for processing message in speech recognition system
KR900001181A (en) Interfacing method between key phone system and key subscriber
JPS6352259A (en) Data communication method
KR970049679A (en) Data receiving device of personal computer
JPS62204362A (en) Shared memory system by network
KR880008569A (en) Signal Control Method between Digital Telephone and Asynchronous Data Terminal Access Device
KR920014047A (en) Data access circuits
JPH0652039A (en) Data transfer system
JPH0317756A (en) Storage access system
KR930014081A (en) Dual port memory interface and control method between network connector and central controller
JPH04195350A (en) Memory address control system
KR970022783A (en) High-Speed Transmission Interface Circuits Using Multiple Memory

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20060830

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee