KR960013400B1 - Sense-amplifier of semiconductor memory device - Google Patents

Abstract

The sense-amplifier is for embodying rapid operation with low power consumption caused by operating it near the threshold voltage. The sense-amplifier comprises: a first sense-amplifying device(11) having a first and a second output devices(S1, /S1) which, maintaining the definite potential difference, generate higher voltage signal over the threshold voltage of an ordinary transistor by receiving the data(DB, /DB) from the memory cell; a second sense-amplifying device(12) having a third and a fourth output devices(S2, /S2) which, maintaining the definite potential difference, generate the signal of lower voltage than the ban voltage by receiving the signal from the first sense-amplifying device(11); and a third sense-amplifying device(13) having a fifth output device(OUT) for generating the sense-amplified signal by receiving it from the second sense-amplifying device(13).

Description

Sense Amplifiers in Semiconductor Storage Devices

1 is a circuit diagram showing a sense amplifier of the present invention.

2 is an output waveform diagram of FIG.

* Explanation of symbols for main parts of the drawings

11: first detection amplification unit 12: second detection amplification unit

13: third sensing amplifier

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier of a semiconductor memory device. In particular, after the sense amplifier is divided into three parts, the output of each part is slightly lower than the voltage obtained by subtracting the threshold voltage of the transistor from the power supply voltage. The present invention relates to a sense amplifier that realizes a fast operation speed with the lowest power consumption by operating at or operating at a voltage slightly higher than the threshold voltage.

In general, a sense amplifier is a circuit for reading, sensing, and amplifying data stored in a cell array of a semiconductor memory device, and then transferring the data to a data output buffer. It is designed to sense, amplify in a short time and deliver to the next circuit.

There are many kinds of sense amplifiers according to the prior art, and among them, there are many kinds which mainly use equalize pulses. However, in the prior art using the equalizing pulse, there is a problem in that a circuit for outputting the equalizing pulse is required, and thus the circuit configuration becomes complicated and the operation speed of the sense amplifier is lowered due to the time difference between the circuits.

Therefore, in the present invention, without using an equalizing pulse as in the prior art, the sense amplifier is divided into three parts, and then the output of each part is operated at a voltage slightly lower than the voltage obtained by subtracting the threshold voltage of a typical transistor from the power supply voltage. It is an object of the present invention to provide a sense amplifier capable of operating at a voltage slightly higher than the threshold voltage, thereby achieving a high operating speed with the lowest power consumption.

The sense amplifier of the present invention for achieving the above object, as a data (DB / DB) read from the memory cell as an input, and outputs a signal having a voltage higher than the threshold voltage of a conventional transistor while maintaining a constant potential difference The first sensing amplifier having first and second output stages S1 and / S1 and a signal output through the first and second output stages of the first sensing amplifier are used as inputs. A second sensing amplifier having third and fourth output terminals S2 and / S2 for outputting a signal having a voltage lower than a voltage obtained by subtracting the threshold voltage of the transistor from the power supply voltage; and the second sensing amplifier of the second sensing amplifier. And a third sensing amplifier having a fifth output terminal SOUT for outputting sensed and amplified read data using the signal output through the third and fourth output terminals as an input.

In order to minimize the amount of current flowing through each part of the sense amplifier of the present invention in the above-described configuration, assuming that the current flowing through each sense amplifier is I ₀ + ΔI, In denotes that the output is Vcc-Vt ( Vcc: power supply voltage, Vt: transistor threshold voltage), and in case of NMOS transistor, the output becomes minimum when Vt, so the output of each part in the sense amplifier of the present invention is below Vcc-V or above Vt. Operate.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram illustrating a sense amplifier of a semiconductor memory device according to an exemplary embodiment of the present invention, wherein the first sense amplifier 11, the second sense amplifier 12, and the third sense amplifier 13 are separated from each other. Consists of parts.

First, the first sense amplifier 11 includes transistors Q4 and Q5 to which the respective drains are commonly connected and the cell data signals DB / DB are input to the gates, and the source and the ground voltage of the transistor Q4. A transistor Q8 connected between and having a gate connected to the source of the transistor Q5, and a transistor Q9 having the transistor Q5 connected between the source and the ground voltage and a gate connected to the source of the transistor Q4 And a transistor Q3 connected between a power supply voltage and a common drain of the transistors Q4 and Q5 and to which a sense amplifier enable signal / SAE inverted to a gate is applied, and the transistors Q4 and Q5. As shown in the output waveform diagram of FIG. 2, the output nodes S1 and / S1, which are the source stages of N2, maintain a voltage of about 0.8V and a high level of about 1.1V.

The second sense amplifier 12 includes transistors Q1 and Q2 having a drain and a gate cross coupled to each other, and a source connected to a power supply voltage, and a drain connected to each other and a gate connected to the first sense amplifier. Transistors Q6 and Q7 connected to the output nodes S1 and S1 of (11) and each source connected to the drains of the transistors Q1 and Q2, respectively, and a common drain of the transistors Q6 and Q7. And a transistor Q10 connected between a ground signal and a ground voltage and to which a sense amplifier enable signal SAE is applied to a gate, and output nodes S2 and S2 of the source terminals of the transistors Q6 and Q7 are formed. As shown in the output waveform diagram of 2 degrees, the low level maintains a voltage of about 1.7V and the high level of about 2.2V.

The outputs S2 and / S2 of the second sensing amplifier 12 maintain the previous position ΔV between the two outputs at a voltage slightly lower than Vcc-Vt.

The third sensing amplifier 13 is connected between a transistor Q13 and Q14 having a current mirror structure, a power supply voltage, and a drain of the transistors Q13 and 14, respectively, and a gate of the third sensing amplifier 13 is amplified. The sense amplifier enable signal SAE is connected to a gate and is connected between the transistors 1QQ and Q12 connected to the output nodes S2 and / S2 of the unit 12 and the common source and ground voltages of the transistors Q13 and Q14, respectively. And an output SOUT, which is a node to which the transistor Q12 and Q14 are connected, has a cell data signal DB, / DB as shown in FIG. After being applied, it is output after a time of about 2 ns has elapsed.

The output waveform shown in FIG. 2 is the result at the power supply voltage of 3V and the temperature at 90 ° C.

Since the waveform of the output SOUT is not an exhaustive CMOS level, the waveform is converted to a desired CMOS level through the inversion gate Q16 and output to the output terminal / SOUT.

The transistors Q10 and Q15 are power transistors of the sense amplifiers, and are controlled by the sense amplifier enable signal SAE to control the operation of the sense amplifier.

Hereinafter, an operation of the sense amplifier illustrated in FIG. 1 will be described in more detail with reference to the output waveform diagram of FIG. 2.

First, if the data stored in the memory cell of the semiconductor memory device is high data, the DB, / DB has a high, low level (relative value), so that the transistor Q4 is larger than the transistor Q5 Since the current is transmitted to the output node S1, the output S1 of the first sensing amplifier 11 has a high level and the output S has a low level.

Subsequently, when the transistor Q7 is turned on more strongly than the transistor Q6 by the outputs S1 and / S1 having high and low levels, the output S2 of the second sensing amplifier 12 is high. Level, output (/ S2) will have a low level.

In addition, when the transistor Q12 is turned on more strongly than the transistor Q11 by the outputs S2 and / S2 having high and low levels, the output SOUT of the third sensing amplifier 13 is Level, and the inversion signal / SOUT has a low level.

On the other hand, in the case where the data stored in the cell is low data, the opposite operation as in the case of the high data is performed to output the low data to the output SOUT.

2 shows an output waveform when data transferred from a cell is converted from high data to low data.

As described above, when the data stored in the cell array is read using the sense amplifier of the present invention described with reference to FIGS. 1 and 2, the power consumption of the memory device operating at a low power supply voltage can be reduced to a minimum. Rather, it has the effect of obtaining the fastest detection speed.

In addition, since there is no need for a transistor to equalize each node as in the prior art, the number of transistors constituting the circuit can be even reduced.

Preferred embodiments of the present invention are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, substitutions, and additions through the spirit and scope of the present invention as set forth in the appended claims.

Claims (4)

First and second output stages S1 for outputting a signal having a voltage higher than the threshold voltage of a conventional transistor while maintaining a constant electric potential value as data DB, / DB read from a memory cell as an input. (S1) and a signal output through the first and second output stages of the first sensing amplification unit as input, the threshold voltage of the transistor at the power supply voltage while maintaining a constant potential difference A second sensing amplifier having third and fourth output terminals S2 and S2 / for outputting a signal having a voltage lower than the voltage, and a signal output through the third and fourth output terminals of the second sensing amplifier unit; And a third sensing amplifier having a fifth output terminal (OUT) for outputting sensed and amplified read data as an input. 2. The first and second NMOS transistors of claim 1, wherein the first sensing amplifier comprises first and second NMOS transistors in which drains are commonly connected and data signals read from memory cells are respectively input to gates. A sense amplifier connected between the source of the transistor and the ground potential, and the respective gates are cross-coupled to each other to connect the third and fourth NMOS transistors and the supply voltage and a common drain of the first and second NMOS transistors. And a first PMOS transistor to which an enable signal (SAE) is applied. The first and second PMOS transistors of claim 1, wherein each of the drain and gate are cross-coupled with each other, and each source is connected to a power supply voltage. A third and fourth PMOS transistors having gates connected to the first and second output terminals S1 and / S1 of the first sensing amplifier and having respective sources connected to drains of the first and second PMOS transistors; And a first NMOS transistor connected between a common drain and a ground voltage of the third and fourth PMOS transistors and to which a sense amplifier enable signal (SAE) is applied to a gate. 2. The first and second NMOS transistors of claim 1, wherein the third sensing amplifiers are connected between first and second NMOS transistors having a current mirror structure, and a power supply voltage and drains of the first and second NMOS transistors, respectively. A gate is connected between the first and second PMOS transistors connected to the third and fourth output terminals S2 and / S2 of the second sensing amplifier unit, the common source and the ground voltage of the first and second NMOS transistors, respectively. And a third NMOS transistor to which a sense amplifier enable signal (SAE) is applied to the gate.