KR960011421B1 - Channel equalizer - Google Patents

Abstract

The equalizer for improving the speed of convergence by adding shadow banks to an FIR filter, includes an error generator detecting errors from the FIR filter, a filter coefficient updater updating the coefficients from the errors to provide them for the FIR filter , the FIR filter filtering an input signal to generate filter coefficients and including sub components such as a buffer storing the coefficient data and addresses temporarily , shadow banks storing the coefficient data and the addresses from the buffer, a work bank loading the coefficient data from the shadow banks, a multiply/accumulator multiplying the input signal by the coefficients data to accumulate them. The equalizer improves the speed of convergence not by incrementing the operation frequency.

Description

Channel equalizer

1 is a block diagram illustrating one embodiment of a general channel equalizer.

FIG. 2 is a diagram for explaining the conventional operation of the FIR filter shown in FIG.

3 is a view for explaining the operation according to the method proposed in the present invention with respect to the FIR filter shown in FIG.

FIG. 4 is a diagram showing an example of data loaded in the first and second shadow banks and the working bank in FIG.

5 is a block diagram according to one embodiment of the applied FIR filter of the present invention in FIG.

* Explanation of symbols for main parts of the drawings

1: FIR filter 3: Error generating unit

5: Clock coefficient update unit 7: Clock generator

11,12: 1st, 2nd buffer 13,14: 1st, 2nd shadow bank

17: Odds and Accumulators

The present invention relates to a channel equalizer, and more particularly to a channel equalizer suitable for improving the convergence speed of the equalizer by further adding a shadow bank in the FIR filter.

In general, in order to transmit a digital video signal having a wide bandwidth in the same bandwidth as that of an NTSC signal, compression of a signal by source coding is required. Deterioration of the signal due to various distortions occurring in the system should be compensated.

Factors that cause distortion include Gaussian thermal noise, impulse, noise, and additive or multiplication noise due to fading, deformation due to frequency variation, nonlinearity, and time dispersion.

Such distortion appears in the picture quality due to distortion in the analog TV system, but in digital transmission HDTV, distortion may cause bit detection error at the receiver, making it impossible to restore the entire screen or display a completely different image. have. In particular, multiple paths due to time delay and phase change of the transmission signal cause severe intersymbol interference, which is a major cause of bit detection error.

On the other hand, channel equalization is a technique for reducing the bit detection error at the receiving side by compensating for distortion caused by the non-ideal transmission channel.

In particular, adaptive channel equalization refers to an equalization technique that can adaptively cope with a variable channel by various factors such as the location, distance, terrain, buildings, and weather of a transceiver.

The ideal channel equalization technique is to find the inverse function of the channel and completely recover the received signal without degradation by the channel.

Many equalization techniques have been studied, but they are classified according to the structural form of the equalizer, the characteristics of the algorithm, or the presence or absence of a training signal used before transmitting the actual data.

The decision feedback equalizer of the channel equalization technique is an equalizer that improves performance by adding a tracked part to the LMS (Least Mean Square) equalizer, and consists of two parts, a feed forward part and a feedback part.

On the other hand, the blind equalizer is a method of equalizing without using a training signal, the performance of which depends on the selection of the nonlinear function to be used.

In this regard, FIG. 1 is a block diagram showing an embodiment of a general channel equalizer, which comprises a complex FIR (Finite Impulse Responce) filter (1) having N taps and an output signal of the FIR filter (1). In order to minimize the intersymbol interference from the error generator 3 generating an error signal, the error signal e output from the error generator 3, and the input signal X to be transmitted, the FIR filter 1 A filter coefficient updater 5 for repeatedly updating the coefficients, and a clock generator 7 for generating a system clock for loading the equalizer filter coefficients in synchronization with the input signal X.

In the channel equalizer configured as described above, first, the filter coefficient is updated in the filter coefficient updating unit 5 by the following expression (1).

w (n + 1) = w (n) + μeX (1)

In the first equation, w (n) and w (n + 1) are coefficients of the FIR filter 1, μ is an equalization convergence constant, e is an error signal output from the error generator 3, and X is an FIR filter (1). And the input signal of the filter coefficient update unit 5, respectively.

On the other hand, in order for the equalizer to operate ideally, both error calculation and coefficient update must be completed between X _k and X _{k + 1} .

However, in practice there are the following limitations.

First, since error calculation takes time, it takes time to calculate the next coefficient w (n + 1). Second, most FIR filters (1) used in the equalizer read only one coefficient at a time. The effective coefficient is delayed by the number of taps.

Degrading the performance of the equalizer due to such a restriction, first, it is assumed that the number of taps of the FIR filter 1 is N and the new clock required for the error calculation is M clock.

During the first N clocks at the start point, the input signal (X) fills the taps of the FIR filter (1), and during the next M clocks, the error is calculated, which is input to the FIR filter (1) during this M clock. The signal X is ignored.

The filter coefficient is then loaded for the next N clocks.

On the other hand, most of the FIR filters have a part for reading coefficients and a part for performing an actual multiplication operation. For example, in the case of ZR33288, a 288-tap digital filter, a shadow bank for reading coefficients and a multiplication operation are performed. It is divided into working banks.

Therefore, once all the coefficients have been loaded into the shadow bank, the loading signal is then put on the working bank.

This operation is shown in FIG.

As described above, since the effective coefficient of the channel equalizer is loaded once every N + M clocks, the equalization convergence time is delayed by N + M times as compared with the ideal case.

Therefore, to improve the convergence speed of the equalizer, a method of reducing the error calculation time (M) and a method (N) of loading the filter coefficient are introduced. However, since reducing the error calculation time (M) depends on the type of communication system, it will not be described here, and the following two methods for reducing the time (N) required to load the filter coefficient will be described.

First, parallel processing is performed using several filters instead of one filter. For example, four N / 4 tap filters are implemented rather than one equalizer using one N tap filter. Increase the loading speed four times.

However, the use of four filters increases the cost and area, and there is a problem that a circuit for controlling each filter must be added separately.

Second, the filter coefficient loading synchronization is not synchronized to the input signal X, and a local clock for only filter coefficient loading is separately set to synchronize the filter coefficient loading.

In other words, if the synchronization to the local clock is twice as fast as the input signal (X) period, the equalization convergence speed is increased by (N + M) / 2 than the ideal case can improve the performance of the equalizer.

This requires a high level of filter manufacturing technology, which increases costs.

The present invention has been made to solve the above-mentioned drawbacks, and an object of the present invention is to provide a channel equalizer capable of improving the convergence speed of the equalizer by further adding a shadow bank in the FIR filter.

In order to achieve the above object, the present invention has N taps, an FIR filter for filtering an input signal with a predetermined filter coefficient, and an error for detecting and outputting an error from a signal filtered and output from the FIR filter. And a filter coefficient updating unit for updating a filter coefficient from the input signal and the error signal output from the error generating unit and supplying the filter coefficient to the FIR filter, wherein the FIR filter includes the filter coefficient updating unit. Buffer means for temporarily storing coefficient data and addresses outputted from a plurality of shadow banks for storing address data and addresses outputted from the buffer means, and a working bank for loading coefficient data output from the plurality of shadow banks Multiplying the input signal of the FIR filter and the coefficient data output from the working bank; And a multiplication / accumulator for outputting to the next stage and the error generating unit.

Hereinafter, described in detail by the accompanying drawings an embodiment of the present invention as follows.

Referring to FIG. 3, FIG. 3 is a diagram illustrating a FIR filter applied to a channel equalizer according to the present invention. FIG. 3 (a) shows a system clock, and FIG. 3 (b) shows an inverted system clock. FIG. 3 (c) shows an address, FIG. 3 (d) shows an address input to a first address buffer, FIG. 3 (e) shows an address input to a second address buffer, and FIG. 3 (f) shows coefficient data, FIG. 3 (g) shows coefficient data input to the first data buffer, and FIG. 3 (h) shows coefficient data input to the second data buffer, i is the first shadow bank, j is the second shadow bank, and k is Represent each working bank.

4 shows an example of data loaded in the first and second shadow banks (i, j) and the working bank (k) in FIG. 3, and FIG. 4 (a) shows the first shadow bank (i). Fig. 4 (b) is data loaded in the second shadow bank j, and Fig. 4c is data loaded in the working bank k, and is loaded in the first shadow bank i. It is data obtained by oring the loaded data a and the data b loaded in the second shadow bank j.

5 is a block diagram according to an embodiment of the FIR filter 1 applied to the present invention in FIG. 1, which includes first and second buffers 11 and 12 for temporarily storing coefficient data and addresses; A first shadow bank 13 for loading the coefficient data and the address output from the first buffer 11, a second shadow bank 14 for loading the coefficient data and the address output from the second buffer 12, An oragate OR1 for ringing the output data of the first shadow bank 13 and the output data of the second shadow bank 14, a work bank 15 for loading the output signal of the oragate OR1, A multiplier / cumulative accumulator 17 for multiplying and accumulating the data input unit 16 for temporarily storing the input signal and the input data output from the data input unit 16 and counting the coefficient data output from the working bank 15. It is composed of

Referring to the accompanying drawings of the present invention configured as described above, first, comparing FIG. 2 and FIG. 3, it can be seen that the address and coefficient data in FIG. 3 are transmitted at twice the speed of FIG. .

However, since it is difficult to operate at the double speed in the equalizer, the speed is adjusted by placing the first and second buffers 11 and 12 with respect to the coefficient data and the address output from the filter coefficient updating unit 5.

The system clock (FIG. 3A) fetches the coefficient data (FIG. 4A) and the addresses stored in the first buffer 11 and stores them in the first shadow bank 13.

On the other hand, the inverted system clock (FIG. 3B) with respect to the system clock (FIG. 3A) fetches the address and the coefficient data stored in the second buffer 12 (FIG. 4B) and the address. 2 is stored in the shadow bank 14.

At this time, the first and second shadow banks 13 and 14 have the same capacities as the shadow banks shown in FIG.

In other words, in the case of an N tap FIR filter, N coefficients can be stored.

After all of the data (FIG. 4 (c)) that stores the data stored in the first and second shadow banks 13 and 14 are loaded into the working bank 15, the first and second shadow banks 13 and 14 are stored. Reset

On the other hand, the data input unit 16 temporarily stores the input signal, and the multiplication / accumulator 17 multiplies and accumulates the coefficient data output from the work bank 15 to the input signal output from the data input unit 16. Output to the next stage and error generator (3 in Fig. 1).

As described above, the channel equalizer according to the present invention increases the number of shadow banks in the FIR filter 1, divides the updated filter coefficient and the corresponding address into 1 / K, and stores them in the shadow bank. The advantage is that the convergence speed of the equalizer can be increased by K times without increasing the operating frequency of the equalizer.

Claims (1)

An FIR filter (1) for filtering an input signal with a predetermined filter coefficient, having a plurality of taps, and an error generator (3) for detecting and outputting an error from a signal filtered and output from the FIR filter (1). And a filter coefficient updater (5) for updating the filter coefficients from the input signal and the error signal output from the error generator (3) and supplying them to the FIR filter (1). The FIR filter (1) includes a plurality of buffer means for temporarily storing coefficient data and addresses which are divided into a plurality of outputs from the filter coefficient updating unit (5) and output respectively; A plurality of buffer means for storing each coefficient data and each address respectively output from the plurality of buffer means; A plurality of shadow banks for storing each coefficient data and each address respectively output from the plurality of buffer means; A work bank 15 for loading each coefficient data output from the plurality of shadow banks; And a multiplier / accumulator 17 for multiplying and accumulating the input signal of the FIR filter 1 and each coefficient data output from the working bank 15 and outputting the next stage and the error generator 3 to the next stage. Channel equalizer consisting of.