KR960011106B1 - Semiconductor memory device - Google Patents

Abstract

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Description

Semiconductor memory devices

1 is a circuit diagram of an example of an SRAM in the prior art.

FIG. 2 is a circuit diagram that includes FETs and other circuitry in critical portions of the memory cell array area of the SRAM of FIG.

3 is a plan view illustrating the interconnection form of the polycrystalline silicon interconnect layer in the critical portion of the memory cell array region.

4 is a cross sectional view along line X-X of FIGS. 2 and 3;

5 is a plot of measured FET gate length in SRAM of FIG.

6 is a graph showing the relationship between FET gate length and drain current.

7 is a voltage waveform diagram applied to a digit line of an SRAM and a read voltage.

8 is an SRAM embodying the present invention and a circuit diagram similar to that of FIG.

9 is a circuit diagram illustrating a polycrystalline silicon interconnect layer in an important portion of a memory cell array region.

FIG. 10 is a cross sectional view along line X-X of FIGS. 8 and 9;

FIG. 11 is a plot of measured gate length values of FETs in the SRAM of FIG. 8 over distance, as compared to the design values.

* Explanation of symbols for main parts of the drawings

W1, W2: Word line D1, D2: Digit line

T4, T5: switch transistor C, D: node

The present invention relates to the structure of a plurality of interconnect layers in a memory cell array region of a semiconductor memory device, in particular random access memory (hereinafter referred to as RAM).

In general, semiconductor memory devices are composed of memory cell arrays and peripheral circuits such as decoder circuits and selection circuits. Notably in the memory cell array region, there are memory cells composed of a plurality of regularly arranged MOS transistors.

On the other hand, for RAMs, especially static RAMs (SRAMs), the power lines (Vcc) and ground lines (GND) are required to be arranged between the memory cells in the memory cell array area, so that the MOS transistor array is locally near the connection line. It is forced to avoid regularity.

MOS transistors composed of memory cells are a plurality of interconnect layers each formed in a regular interconnection form of a memory cell array region, and the interconnect pattern should avoid local regularity near the connection line.

The inventors have found that the change in the design value is greater in the locally irregular pattern interconnect layer than in the regular pattern interconnect layer. The size of the polycrystalline silicon interconnect layer larger than the design value results in a larger gate length of the MOS transistor (FET) formed on the substrate than the design value leading to a reduction in the cross-conductance.

Reducing the transconductance of the transistors slows down the response speed of the memory device and possibly causes a delay as well as a delayed rise in the digit line potential.

It is therefore a primary object of the present invention to provide a semiconductor memory device of a structure which does not allow an increase in the gate length of the transistor due to the connection line arrangement near them in the memory cell array region, thereby reducing in mutual conductance and improving the response speed. Lowering, and the occurrence of malfunction is prevented.

A memory cell comprising a plurality of transistors in said memory cell array region on a semiconductor substrate composed of a plurality of interconnect layers separated by an insulating layer between an upper conductor layer and a lower interconnect layer of a transistor comprising an electrode region and a connection region. And a random access memory comprising a memory cell array having a plurality of memory cells arranged in rows and columns; Selecting means for electrically selecting a memory cell through the conductor layer in the array unit in the column and row directions; Data access means for placing data in said selected memory cell and controlling to obtain data therefrom; A semiconductor memory device comprising at least one component of said selection means and said data access means disposed in proximity to said memory cell array portion, said electrode cell portion and said connection region of said transistor, said memory cell array portion comprised of said transistor The first and second memory cell arrays of the memory cell array disposed in proximity to each other are formed in the lower conductor layer; A dummy connection zone having no electrical connection to the electrode zone and the connection zone is formed in the lower conductor layer between the cells of the first and second memory cell arrays; One of the selection means and the data access means is formed in the upper interconnect layer between the first and second memory cell arrays for electrically connecting between the dummy connection and the selection means.

Referring to FIG. 1, which shows a circuit diagram of a prior art SRAM including a memory cell including an nMOS transistor, the memory cells S11, S12, S21, S22 of the memory cell region in the row and column directions are located therein. Are arranged. Each memory cell is connected to a word line operating in the row direction, for example, S11 and S12 are connected to a word line W1 and S21 and S22 are connected to another word line W2. Each memory cell is also connected to digit lines D1 and D2 operating in the column direction, for example, memory cells S11 and S21 are connected to digit lines D1 and D2. A balance circuit composed of transistors T3 and a load circuit composed of transistors T1 and T2 are connected between the digit lines D1 and D2 at its gate electrode to which the signal ψ is input. Switch transistors T4 and T5 connected to the respective digit line pairs D1 and D2 to constitute a sense amplifier SAMP, and a column select circuit connected to the column select circuit to amplify the potential difference of the selected digit line pair. Is provided in part.

Each memory cell S11, S12, S13, S14, ... is made of a flip-flop circuit composed of a cross-coupled pair of inverters, one of which is a first inverter composed of a transistor M1 and a resistor R1. The other is a second inverter circuit composed of a transistor M2 and a resistor R2. Source, drain, and gate electrodes are connected to one input / output terminal of the flip-flop circuit or node C of the first inverter circuit, digit line D1, word line W1, and a moving gate (access) respectively. The transistor M3, and the source, drain, and gate electrodes are connected to the node D, the digit line D2, and the word line W1 of the other input / output terminal of the flip-flop circuit or the second inverter circuit, respectively. Another moving gate (access) transistor M4 to be connected is additionally provided.

The data of zero or one is stored in the memory cell depending on whether the conservative potentials of nodes C and D are respectively high, low or vice versa.

In the read mode of the SRAM, the selected word line taking W1 as an example is activated, the moving gate transistors M3 and M4 are turned on, and nodes C and D are connected to the digit lines D1 and D2, respectively. In the two digit lines of the potential, one is lowered in response to the data stored on the memory cell or the potential of the nodes of C and D to generate a potential difference between the two. The potential difference is amplified by a sense amplifier (SAMP) and sent to an output circuit (not shown).

In the write mode, a potential difference corresponding to the data is applied between the digit lines D1 and D2, whereby the mobile gate transistors M3 and M4 are turned on, whereby the nodes C and D are set to the potential.

The circuit form of the memory cell array region portion of the SRAM of FIG. 1 is shown in FIG. 2 in which the component and partial display by the figure character are the same as in FIG. 1, and the thin solid line is active assigned by the selective oxide field oxide film. Area refers to the polycrystalline silicon region in the upper layer associated with the active region, cross-hatching refers to the direct contact region in the polycrystalline region, the active region is located in direct contact with each other, and the thick solid line represents the polycrystalline silicon Refers to the aluminum interconnect in the top layer with respect to the area.

Transistor M1 is provided in active region 1, and its gate electrode G1 made of a polycrystalline silicon film is connected to drain region d2 (node D) of transistor M2 via direct contact 7. Connected. The source region SC1 is connected to the polycrystalline silicon region 11 via the direct contact 10, and the drain region d1 is made of the polycrystalline silicon film via the direct contact 8. Is connected to the gate electrode G2 (node C).

The transistor M2 is provided in the active region 2, and the source region scS2 is a ground made of an aluminum film via the polycrystalline silicon region 11 and the contact hole 4 via the direct contact 12. It is also connected to the line GND.

Transistor M3 is provided in the active region and its source and drain are in contact contact 5 (node A) connected to digit line D1 and in direct contact connected to gate electrode G2 of transistor M2. 9) (node C). The gate electrode G3 is formed like a region where a word line W1 made of a polycrystalline silicon film and an active region 3a are internally crossed.

The transistor M4 is provided in the active region 2a leading to the active region 2 and operates in parallel in the longitudinal direction of the active region 3a. The source and the drain are formed between the contact hole 6 (node B) connected to the digit line D2 and the direct contact 7 (node D) connected to the gate electrode G1 of the transistor M1. The gate electrode G4 is formed in a region where a word line W1 made of a polycrystalline silicon film and an active region 2a are internally crossed.

Except for the load resistors R1 and R2, the power line Vcc (which is not shown in FIG. 2) is a memory that is well known for processes such as the polycrystalline silicon film in a layer at a different level than the polycrystalline silicon film for producing the transistor. It is formed in the cell array region.

The memory cell S11 is composed of transistors M1 to M4, load registers R1 and R2, and interconnection among the circuit elements as described above. Memory cells S12, S21 and S22 having the same circuit appearance as S11 are formed in combination with S11 in the same process, and their detailed description is omitted.

In the memory cell array region of the SRAM, generally one power connection line Vcc and one ground connection line GND are provided between 6 to 12 memory cells. In the best aluminum interconnect layer associated with the active region and the polycrystalline silicon layer to operate longitudinally (first degree) between memory cells S11 and S12 and memory cells S21 and S22 in the SRAM shown in FIG. Is formed.

As described above, in the memory cell array region in which the memory cells are arranged in the row and column directions, a plurality of polycrystalline silicon regions are formed in the form of circuits in which the gate and word lines of the transistors are regular.

For the example of FIG. 2, a polycrystalline silicon region serving as a component of transistors M1, M2, M3 and M4 is formed in a regular interconnection form in the memory cell array region.

When referring to FIG. 3 showing only the interconnection form of the polycrystalline silicon layer in the portion of the memory cell array region including and near the region of FIG. 2, the region of FIG. 2 is indicated by reference numeral 200. And the interconnection form of the polycrystalline silicon layer in which the gate electrodes G1 and G2 of each of the transistors M1 and M2 are formed, which is defined by a dotted line, includes a zone including the region shown in FIG. Regular, except as line zone). In this zone, the arrangement of the transistors is not regular because of the placement of the ground line GND over the ground line zone in the higher level aluminum interconnect layer indicated by the dashed line in FIG.

For example, due to the arrangement of the ground line GND made of an aluminum film operating in the column direction between the memory cells S11 and S12 and S12 and S22 (FIG. 1), as described above with reference to FIG. For example, the width GP (FIG. 3) is formed between opposing polycrystalline silicon regions serving as gate electrodes G2 and G2 of transistors M2 and M2 of memory cells S11 and S12. Larger, in other words, the arrangement or interconnection form of the polycrystalline silicon region in the vicinity of the zone excludes regularity from the above mentioned particular viewpoint.

When referring to reference to FIG. 4, which is a cross section along the line X-X of FIGS. 2 and 3, in the active region 2 on the P-type silicon substrate 40, the memory cell S11 by diffusion. Source and drain regions represented by sc2 and d2 of transistor M2 are formed. Each of the gate electrodes G2 and G2 made of polycrystalline silicon is formed on the oxide film 41 serving as a gate insulating film on the surface of the substrate. The source, drain and gate regions of the transistor M2 of the memory cell S12 are formed in the same process as that of the transistor M2 of the memory cell S11. The width of the gate electrodes G2 and G2 of the transistor is called the gate length L. After completing the gate electrode G2 interconnection, all the surfaces of the chip are covered with an insulating layer 42, on which a number of digit lines made of an aluminum film operating in parallel between all pairs of digit lines D1, D1. D1 and ground line GND are stacked. There is no interconnection in the polycrystalline silicon layer under ground line GND, and therefore the distance GP between the opposing gate electrodes G2, G2 of the transistors M2, M2 of the memory cells S11, S12 is the ground line zone. As described above, the polycrystalline silicon interconnection pattern therefore excludes regularity.

In order to show the influence from the regularity or the above-mentioned and locally irregular interconnection shape on the design value of the size of the polycrystalline silicon layer, the graph of FIG. 5 shows the ground power line from the end of the polycrystalline silicon region in the figure, abscissa. The distance D to the GND (μm) and the ordinate are configured by the measurement result which is the gate length L (μm, FIG. 4) of the transistor M2 and the black point on the ordinate. It is apparent from FIG. 5 that the measurement result is not always the same as the design value GL of the gate length L. FIG. In other words, as shown in FIG. 5, the width L of the polycrystalline silicon region defining the gate length of the transistor M2 is closer to the ground line GND, so that from the design value GL becomes larger. The difference ΔL1 is shown. For example, assuming a design value of 0.8 mu m, the maximum value of DELTA L1 is 0.025 mu m.

A gate length L larger than the design value will lead to the following problem. As shown in FIG. 6, in which the gate length L (µm) is in abscissa and the drain current I is in ordinate, the gate length (3V) is used as a parameter. When L) is larger by ΔL1 (μm) than the design value GL (0.8 μm), the drain current I (k) will decrease by ΔI. Thus, for example, in a device that is deviceed to set the drain current to a desired value of 0.648 mA, the deviation of the gate length L, which is 0.025 μm larger than the design value, is due to 0.0325 mA or 5% of the desired value. The result is a reduction in drain current. It lowers the rise of the read output for the memory cell, and in turn causes a lot of the decrease in the response speed of the memory, as well as inducing the occurrence of a read error.

FIG. 7 shows a graph made by plotting time in abscissa and voltage in ordinate. As evident from FIG. 7, the above-mentioned damage in the operation of the transistor is (1) the potential change of the connected digit line (change from solid line to dashed line) to delay the transistor, and (2) delay the potential difference of the digit line. The output is taken from the amplified sense amplifier. As a result, (3) it delays by nsec to delay the potential difference of the SRAM, not only generates a read / write error but also significantly lowers the operation.

The problem is due to a change in the size of the active area. Lithography, which involves in the order of coating the above described photoresist films of the interconnect form from regularity, affects the exposure in a particular form via a mask, and is a polycrystalline silicon film, in particular one of the conditions for exposure. Optionally remove It is the cause of the size change of the polycrystalline silicon region that remains selectively after etching and avoids consistency in the gate length.

FIG. 8 shows a circuit form of an SRAM embodying the present invention, diagrammed in the same manner as in FIG. 2, where it is that of a prior art SRAM comprising memory cell pairs S11 / S12 and S21 / S22 composed of nMOS transistors. Components and parts in common with are represented by the same drawing character.

In contrast to the prior art example shown in FIG. 2, in this embodiment, the dummy region 100 is different from the transistors M2 and M2 under the ground line GND and on the opposite side of the ground line GND. It is arranged between the opposing gate electrodes G2 and G2 made of a crystalline silicon film.

Referring to FIG. 8 in conjunction with FIG. 9 of the polycrystalline silicon interconnect type programmed as in FIG. 3, the embodiment will be described below. In the process of forming the polycrystalline silicon interconnect layer (FIG. 9), one level is lower than the aluminum interconnect layer comprising a ground line (GND) separated by an insulating layer (it will be described below) between them, The dummy region 100 is combined with the gate electrodes G2, G2 (shown in the center portion in the right half of FIG. 8 and near the line X-X in FIG. 9) of the transistor described above and between the electrodes, It is formed under ground line GND. The dummy zone is connected to ground line GND via a contact hole 14.

Referring to FIG. 10, which is a cross section along line X-X of FIGS. 8 and 9, the field insulating film 43 is field-oxidized between the regions in which transistors M2 and M2 of memory cells S11 and S12 are manufactured. Is formed in the active region 2 fabricated on the P-type silicon substrate 40 by the process, and therefore the region is separated by the field insulating film 43. In the active region 2 of the memory cells S11 and S12, the source region sc2 and the drain region d2 of the transistor M2 are formed by diffusion. In addition, a gate electrode G2 made of a polycrystalline silicon film is formed on the oxide film 41 formed as the gate oxide film of the transistor.

Furthermore, a dummy region 100 of polycrystalline silicon is formed on the insulating film 43, between the two gate electrodes G2 and G2, together with the gate electrode in the same process. An insulating layer 41 is then formed to cover all surfaces of the two gate electrodes G2 and G2 and the dummy region 100, and on the insulating layer a pair of digit lines D1 and D1 and a ground power line ( GND) are arranged in the same direction as each other. In the above configuration of the embodiment, the polycrystalline silicon interconnection form is arranged by combining with the gate electrodes G2 and G2 of the pairs of transistors M2 and M2 adjacent to each other and formed in the same process therebetween. By being arranged above with a device structure comprising prior art, the polycrystalline silicon interconnect form is compensated for regularity, leading to a solution to the above-mentioned problems with a device structure comprising prior art.

In the abscissa, the distance D from the edge of the polycrystalline silicon region of the gate electrode G2 mentioned above to the ground line GNDD, the gate length L as in FIG. As is apparent from FIG. 11, the measurement results indicated by black spots are substantially in agreement with the design value GL. According to the present invention, the decrease in the cross-conductance of the transistors in the memory cell array region is prevented because of the increase in the gate length, so that problems such as a decrease in response speed and a readout error including the present SRAM can bring a solution.

The above described embodiment is an SRAM composed of nMOSs, and the present invention is applied similarly to SRAMs composed of pMOSs. For the latter, in the circuit form of FIG. 8, the ground line GND can be replaced by the power line Vcc connected to the power supply voltage Vcc. The present invention relates to memory cells in which memory cells are regularly arranged, such as dynamic RAM (DRAM), programmable read-only memory (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), moving registers, and CCD memory. It is finally evident by those skilled in the art that can be applied to SRAMs as well as to memories including memory cell arrays.

Although the present invention has been described with reference to specific embodiments, the above description is not meant to be interpreted in a limiting sense. Although described with reference to the disclosed embodiments, the description will be apparent to those skilled in the art of limiting sense. The claimed claims will cover modifications as such fall within the true scope of the invention.

Claims (7)

A memory cell comprising a plurality of transistors in the memory cell array region on a semiconductor substrate composed of a plurality of interconnect layers separated by an insulating layer between an upper conductor layer and a lower interconnect layer of a transistor consisting of an electrode region and a connection region. Random access memory including a memory cell array having a plurality of memory cells arranged in rows and columns, selection means for electrically selecting memory cells through the conductor layer in the array units in the column and row directions; A semiconductor memory device comprising data access means for placing data in a selected memory cell and controlling to obtain data therefrom, and at least one component of said selection means and said data access means disposed proximate to said memory cell array portion; In the transistor The first and second memory cell arrays of the memory cell array disposed in close proximity to an electrode region and a connection region, and a portion of the memory cell array composed of the transistors are formed in the lower conductor layer, and are formed in the electrode region and the connection region. A dummy connection area having no electrical connection is formed in the lower conductor layer between the cells of the first and second memory cell arrays, and one of the selection means and the data access means is provided between the dummy connection and the selection means. And formed in said upper interconnect layer between said first and second memory cell arrays for electrically connecting. 2. The semiconductor memory device according to claim 1, wherein the electrode region and the connection region of the transistor, the memory cell of the first and second memory cell arrays are composed of the transistor, and the dummy region has a similar shape. . The semiconductor memory device of claim 1, wherein the dummy connection region and the lower interconnect layer are in the same process at the same time. 4. The semiconductor memory device of claim 1, wherein the lower interconnect layer is made of polycrystalline silicon. 2. The memory cell of claim 1, wherein the first and second memory cell arrays are disposed on opposite surfaces of a connection line in the vicinity of the memory cell array portion, and each transistor corresponding to each other of the memory cells of the memory cell array is connected to the connection. And symmetrically arranged in a line. 2. The semiconductor memory device of claim 1, wherein the transistor of the memory cell is a MOS transistor. The memory cell of claim 1, wherein the memory cells in the first and second memory cell arrays disposed in the vicinity of the power line constituted by the gate electrode corresponding to each other of the MOS transistor and the MOS transistor are arranged in the vicinity of the connection line. And the distance between the gate electrode and the dummy connection region and the distance between the gate electrode and the gate electrode of the MOS transistor in the memory cell are substantially constant.