KR960010869B1 - Processor state management method of dbms - Google Patents

Abstract

(1) OMP(Operation and Maintenance Processor)'s sending a state test requesting message to a selected processor, operating a related timer, and testing the state of the processor; (2) when the processor is in normal state, sending a state test ending message to the OMP (1) to stop the timer, and sending a state test requesting message to the next processor to operate the related timer; (3) when the processor is in abnormal state, sending information indicating that the processor is abnormal to the OMP (1), and OMP's sending a processor audit message; (4) sending a message requesting for the state test of the next processor to operate the timer; and (5) repeating the procedures up to the last processor.

Description

Processor State Management and Audit Method in Distributed System

1 is a block diagram of an ATM switch processor to which the present invention is applied.

2 is a flowchart illustrating a method for managing and auditing a state of a processor according to the present invention.

* Explanation of symbols for main parts of the drawings

1: OMP (Operation and Maintenance Processor)

2: network synchronization control processor (NSCP)

3: MMCP (Man Machine Control Processor)

4,11: BCP (Broadcasing Call Processor)

5: CIMP (Central Interconnection Maintenance Processor)

6: RCIP (Remote Center Interface Processor)

7: Global Service Processor (GSP)

8,13: NTP (Number Translation Processor)

9: SCP (Subscriber Call Processor)

10: TCP Call Processor

12: ASMP (Access Switching Maintenance Processor)

14: SH (Signalling Handler)

The present invention relates to a processor state management and audit method for efficiently managing and monitoring processor status without load on an operation and maintenance processor (hereinafter referred to as OMP) in a distributed processing system such as an electronic switching system. will be.

In general, distributed processing systems, such as electronic switchboards, consist of tens or thousands of processors, which must be managed periodically and accurately managed with minimal system load. OMP performs the status management of each processor. In addition to the processor status management function, OMP is related to the operation and maintenance of the system, the system restart and operation control functions, test functions, various traffic information, statistics and billing information collection management functions, It takes a lot of load because it performs subscriber management functions. Therefore, in order to know which processor is in an abnormal state and to recover quickly, the test cycle should be faster, and for this, a state management method that can minimize the load of the OMP and an audit method that can check the abnormal state are required. That is, in the existing state management method, the OMP requires a state test to each processor each time, and the processor that is requested for the state test should send a response to the OMP every time whether the state is normal or abnormal. Therefore, the conventional method puts a lot of load and bottlenecks on the OMP that manages hundreds to thousands of processor states in a distributed system such as an exchange because all processors send and receive messages related to OMP and status tests. This overload makes it difficult to perform processor health tests frequently, making it difficult to pinpoint the processor's exact state and making it difficult to quickly detect and recover abnormal processors.

The present invention devised to solve all the problems of the prior art, the OMP is tested only in the state of the order of all the processors in the normal state of the processor, if no abnormality is found without giving any response to the OMP OMP only OMP The OMP, which receives abnormal processor information, sends a processor audit message to check if the processor is abnormal and performs a health test with the processor located next to the processor. The purpose of this paper is to provide a processor status management and auditing method in a distributed system in which the processor status test is performed using the same method until the status test of the last processor is completed.

In order to achieve the above object, the present invention provides: Operation and Maintenance Processor (OMP), Network Synchronization Control Processor (NSCP), Man Machine Control Processor (MMCP), Broadcasing Call Processor (BCP), Central Interconnection Maintenance Processor (CIMP), RCIP (Remote Center Interface Processor), Global Service Processor (GSP), Number Translation Processor (NTP), Subscriber Call Processor (SCP), Trunk Call Processor (TCP), Access Switching Maintenance Processor (ASMP), Signaling Handler (SH) A processor state management and audit method applied to an exchange, the OMP is a first step of operating a timer and testing the state of the processor while sending a state test request message to the selected processor for the state test; After performing the first step, if the processor state is normal, and stops the timer while sending a status test completion message to the OMP, the second step of operating the processor-related timer while sending a status test request message to the next processor located: After performing the first step, if the processor is abnormal, the processor transmits abnormal processor information to the OMP, and the OMP sends a processor audit message to check whether the processor is abnormal. A fourth step of starting a timer while sending a status test request message to a processor located next; And a fifth step after the second step and the fourth step are performed, which are performed after the last processor.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

FIG. 1 is a processor configuration diagram of each module of an ATM switch according to the present invention, and includes OMP (1), NSCP (2), MMCP (3), BCP (4), CLMP (5), RCIP (6), and GSP. (7), NTP (8), SCP (9), TCP (10), BCP (11), ASMP (12), NTP (13), SH (14).

OMP (1) oversees a series of operations and maintenance related functions in the system. Accordingly, the MT and the disc include general programs and data as auxiliary storage devices.

The NSCP 2 controls the network synchronizer device.

The MMCP 3 allows for dialogue between the operator and the system. For the conversation between the operator and the system, VDUs including the system console and printers for hard copying the output data are used. The local disk is used to supplement the visibility of the VDU, to store command files, and to store logging files.

BCP (4), (11) is a processor that manages call / access control for providing multi-access (broadcast) related services and is located in CIM (Central Interconnection Module) and ASM (Access Switching Module). Control the overall multiple access capabilities of the process.

The CIMP (5) is responsible for the control of maintenance tasks within the CIM, including fault collection and testing of hardware resources within the CIM.

The RCIP 6 controls communication with a remote operation center or a Telecommunication Management Network (TMN), and performs a protocol conversion function as necessary.

The GSP 7 responds to the number translation request from each SCP, TCP and BCP, and performs ASM number translation and the link ID received in each ASM.

SCP (9) is a processor that performs call processing of general subscriber using UNI protocol and performs overall traffic control such as call admission control, UPC, priority, control, and congestion control along with subscriber matching circuit.

TCP (10) is a processor that performs call processing with network using NNI protocol. It performs call / connection control on input / output call with relay line matching circuit and manages all functions necessary for matching with network. .

The ASMP 12 is responsible for controlling maintenance tasks in the ASM, such as fault collection and testing of hardware resources in the ASM.

The SH 14 terminates the signal information cell on the UNI / NNI protocol and processes the signal information with SCP, TCP or BCP.

Effects of the blocks having the above characteristics are as follows.

The OMP (1) sends a processor status test request message to the NSCP (2) to start a timer related to the NSCP.

NSCP (2) tests its processor status and if the status is normal, it sends a status test completion message to OMP (1) and if NSCP (2) is not in good condition (ie, the timer associated with NSCP (2) expires). If there is no response) OMP (1) (the processor that sent the status test request message, in this case OMP (1)) sends abnormal information to OMP (1), and sends the status test request message to MMCP (3). Activate the timer associated with (3).

OMP 1 sends a processor audit message to NSCP 2 to perform a processor audit.

After testing the processor status in the same way with the MMCP (3) that received the status test request message, and if the condition is good, the processor that sent the status test request message to the MMCP (3) sends the abnormality information to the OMP (1) and sends it to the BCP (4). The timer associated with the BCP (4) is started while sending a status test request message. The OMP 1 receiving the abnormal information sends a processor audit message to the MMCP 3 to perform the audit of the processor.

The OMP 1 has a table of information about the addresses and timers (time required to test the status information of each processor) for all processors.

2 is a process flow diagram for a processor state management and audit method in accordance with the present invention.

The OMP 1 starts the associated timer, sending a status test request message to the first located processor (15). After testing the processor's status (16), in the normal case, the timer is stopped by sending a status test completion message to the OMP (1) (17), and a status test request message is sent to the second located processor to reset the timer associated with the processor. Activate (18). If the timer expires and there is no response, the processor is abnormal and notified to OMP (1) (in this case, the processor that sent the status request message is OMP) (19), and OMP (1) tells the processor that A processor audit message is sent to check whether it is abnormal to perform a processor audit (20), and a timer is started while sending a status test request message to a processor located next (21). This is done until the last processor is terminated (22).

Similarly, the processor located in the second state tests the state, and if the first processor is normal, the status test completion message is sent to the first processor, and if abnormal, it is sent to OMP (1). Each processor that receives the status test request message from the processor located immediately before the test of its status, and sends a status test completion message to the processor located immediately before. If the status test completion message does not come until the timer expires, it means that the processor is abnormal, so the processor immediately located is notified to OMP (1) that the processor currently being tested is abnormal, and the received OMP (1) is an abnormal processor. A status test request message is sent to the processor located next to the timer, which starts the timer necessary to test and initiates recovery of the abnormal processor. This process is repeated repeatedly until the completion of the status test of the last processor located.

In the present invention as described above, the state information test is performed in the order of the processor position until the abnormal processor is found, and since the abnormal information is sent to the OMP 1 only when the abnormal processor is found, the conventional processor state management method is used. Less load on the OMP (1) and processor audit message can be used to perform the processor audit function so that accurate state detection is possible. Information about the faulty processor can be retrieved and the average propagation delay time can be known using a timer. In addition, since the load on the OMP 1 is reduced, the processor state test can be frequently performed, so that an abnormal processor can be found more quickly and the recovery process can be speeded up.

Claims (1)

Operation and Maintenance Processor (OMP) (1), Network Synchronization Control Processor (NSCP) (2), Man Machine Control Processor (MMCP) (3), Broadcasing Call Processor (BCP) (4,11), Central Interconnection Maintenance Processor (5), Remote Center Interface Processor (RCIP) (6), Global Service Processor (GSP) (7), Number Translation Processor (NTP) (8,13), Subscriber Call Processor (SCP) (9), TCP In the processor state management and auditing method applied to an exchange having a trunk call processor (10), an access switching maintenance processor (ASMP) 12, and a signaling handler (SH) 14, the OMP 1 is a state. A first step (15, 16) of operating a related timer and testing the state of the processor while sending a status test request message to the selected processor for testing; If the processor state is normal after performing the first steps (15, 16), the timer is stopped while sending a status test completion message to the OMP (1), and the status test request message is sent to the next processor located. Second step (17, 18) of operating the timer: After performing the first step (15, 16), if the processor is abnormal transmits the abnormal processor information to the OMP (1) and the OMP (1) Third step (19,20) of performing a processor audit by sending a processor audit message to check whether it is really abnormal: After performing the third step (19,20), while sending a status test request message to a processor located next A fourth step 21 of operating the timer; And a fifth step 22 of performing after the second step 17 and 18 and the fourth step 21 and ending with the last processor. Audit method.