KR960009667B1 - Common circuit for vesa local bus and isa bus - Google Patents

Common circuit for vesa local bus and isa bus Download PDF

Info

Publication number
KR960009667B1
KR960009667B1 KR94002811A KR19940002811A KR960009667B1 KR 960009667 B1 KR960009667 B1 KR 960009667B1 KR 94002811 A KR94002811 A KR 94002811A KR 19940002811 A KR19940002811 A KR 19940002811A KR 960009667 B1 KR960009667 B1 KR 960009667B1
Authority
KR
South Korea
Prior art keywords
signal
bus
decoder
cpu
receiving
Prior art date
Application number
KR94002811A
Other languages
Korean (ko)
Other versions
KR950025548A (en
Inventor
Sung-Hwan Ahn
Original Assignee
Lg Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lg Electronics Inc filed Critical Lg Electronics Inc
Priority to KR94002811A priority Critical patent/KR960009667B1/en
Publication of KR950025548A publication Critical patent/KR950025548A/en
Application granted granted Critical
Publication of KR960009667B1 publication Critical patent/KR960009667B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0018—Industry standard architecture [ISA]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G09G5/397—Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Microcomputers (AREA)
  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)

Abstract

a CPU; a ISA bus controller operated by a control signal, an address and a data from the CPU; a decoder(21) for receiving control signal from the CPU; a local bus RAM DAC(15) for receiving RAMDACW and RAMDACR signal from the decoder; a multiplexer(22) for outputting MLDEV signal to the ISA bus controller when RAMDACW signal indicats an operation after receiving LDEV signal from the decoder. The circuit performs overlay function without data conflicting.
KR94002811A 1994-02-17 1994-02-17 Common circuit for vesa local bus and isa bus KR960009667B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR94002811A KR960009667B1 (en) 1994-02-17 1994-02-17 Common circuit for vesa local bus and isa bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR94002811A KR960009667B1 (en) 1994-02-17 1994-02-17 Common circuit for vesa local bus and isa bus

Publications (2)

Publication Number Publication Date
KR950025548A KR950025548A (en) 1995-09-18
KR960009667B1 true KR960009667B1 (en) 1996-07-23

Family

ID=19377320

Family Applications (1)

Application Number Title Priority Date Filing Date
KR94002811A KR960009667B1 (en) 1994-02-17 1994-02-17 Common circuit for vesa local bus and isa bus

Country Status (1)

Country Link
KR (1) KR960009667B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000003700A (en) * 1998-06-29 2000-01-25 김형벽 Bus module apparatus

Also Published As

Publication number Publication date
KR950025548A (en) 1995-09-18

Similar Documents

Publication Publication Date Title
AU6046790A (en) Image processor
CA2059928A1 (en) Multimedia expansion unit
GB2349965A (en) Memory module including a memory module controller
CA2205830A1 (en) A processor for performing shift operations on packed data
CA2109682A1 (en) Multiple Bus Interface
EP0642103A3 (en) Computer graphics system.
AU5989494A (en) Text input font system
GB2396232A (en) Method and apparatus for regulating the voltage supplied to a computer system
TW367459B (en) Electronic apparatus
EP0624846A3 (en) Bus control apparatus.
EP0996267A3 (en) Interface device
HK1018832A1 (en) Method and system of data transfer
KR960009667B1 (en) Common circuit for vesa local bus and isa bus
CA2263856A1 (en) Control of brightness of text/graphics overlay
AU1030699A (en) Interface for a lamp operating device
KR870001514A (en) controller
JPS5391543A (en) Installation system for hdlc circuit
EP0326102A3 (en) Method and apparatus for selecting a keyboard on a computer system
MY115215A (en) Bnc/d-sub signal auto-selection circuit
MX9706005A (en) Servo motor control.
JPS5299737A (en) Multi computer control system
TW257848B (en) Adaptive display memory management system and method thereof
JPS6451793A (en) Telephone system
JPS57157363A (en) Address stop controlling circuit
JPS5578333A (en) Data transmission and receiving control system

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20010314

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee