KR960005358B1 - Semiconductor memory device - Google Patents

Abstract

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Description

Semiconductor memory device

1 is a block diagram showing a memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing one of the redundant memory cell blocks and the memory cell blocks shown in FIG.

3 is a block diagram illustrating a memory device according to another embodiment of the present invention.

FIG. 4 is a circuit diagram showing one of the redundant memory cell blocks and the memory cell blocks shown in FIG.

5 is a block diagram showing a conventional EEPROM device.

FIG. 6 is a diagram showing a circuit configuration of one of the redundant memory cell blocks and the memory cell blocks shown in FIG.

7 is a cross-sectional view of a typical memory cell transistor used in an EEPROM.

* Explanation of symbols for main parts of the drawings

CB: memory cell block DCB: redundant memory cell block

[Background of invention]

TECHNICAL FIELD The present invention relates to semiconductor memory devices, and more particularly, to an electrically erasable programmable read-only memory.

Recently, a so-called flash EEPROM has been developed that can simultaneously erase memory data stored in a plurality of memory cells. Similar to dynamic or static memory devices with high memory capacity, flash EEPROMs also have memory cell arrays divided into multiple memory cell blocks. In this case, the data erase operation is performed independently in each cell block. Also provided are redundant memory cell blocks having one or more redundant bit lines associated with redundant memory cells in a flash EEPROM. As is well known in the art, a redundant memory cell block is used in place of a memory cell block having the defective memory cell or cells when the defective memory cell is accessed. However, since the data erase operation is performed in the cell block unit, the redundant memory cell block used in place of any one of the memory cell blocks is used in place of any one of the memory cell blocks. It is required to erase the block at the same time.

Referring to FIG. 5, a typical flash EEPROM includes four memory cell blocks CB1, CB2, CB3 and CB4, and a redundant memory cell block DCB. The row decoder and word driver circuit WD decodes the row address signal set Add1 from the address buffer AB and expands the word line WL (two word lines WL1 and two) to the buckwheat cell blocks CB1, CB2, CB3 and CB4 and the redundant memory cell block DCB. WL2 selectively drives one line (shown). Memory cell blocks CB1, CB2, CB3, CB4 and redundant memory cell blocks DCB are associated with column selectors CB1, CB2, CB3 CB4, and CSD and transfer gate transistors TG1, TG2, TG3, TG4 and TGD, respectively.

6, the circuitry of the memory cell block CB1, the redundant memory cell block, and the DCB is shown. The other memory cell blocks CB2, CB3 and CB4 have the same configuration as the memory cell block CB1. The memory cell block CB1 has a plurality of memory cell transistors MCT111, MCT112, MCT11m, MCT121, and MCT122 arranged in a matrix, each of which is a gate connected to one line of the word line WL, one of the bit lines BL11, BL12, and BL1m. And a source connected to the source line SL1 connected to the common source line SL through the associated transfer gate transistor TG1. Each of the memory cell blocks CB has m bit lines BL11, BL12, ..., BL1m and one source line SL1.

In contrast, the redundant memory cell block DCB includes two redundant bit lines BLD1 and BLD2 and a plurality of memory cell transistors MCTD11 and MCTD12. Each transistor has a gate connected to its associated word line, a drain connected to one of two redundant bit lines BLD1, BLD2, and a source connected to a source line SLD.

The memory cell transistors MCT111, MCT112, MCT11m, MCT121, and MCT122 of each memory cell block CB and the memory cell transistors MCTD11, MCTD12 of the redundant memory cell block DCB are formed in the same configuration.

In detail, as shown in FIG. 7, each of the memory cell transistors and the redundant memory cell transistors is a MOS type formed in the semiconductor substrate SUB and includes a stacked gate including a control gate CGE and a floating gate FGE connected to the word line WL1. Have a national SGE. The source region SR and the drain region DR are connected to the source line SL1 and the bit line BL11, respectively.

As an example of the operation of such a device, the memory cell transistor, which is the transistor MCT112, can be described in a state of having a defect. In this case, a column address indicating a defective memory transistor MCT112 is programmed into the address latch circuit AL as the defective column address signal AddD1. Comparator COMP compares input column address signal Add2 with defective column address signal AddD1 and replaces address signal Add2 with column address signal AddR1 if they match each other. Therefore, the memory cell transistor MCTD11, which is, for example, one of the redundant memory cells, is used in place of the defective memory cell transistor MCT112.

In the program mode operation, when the address signal Add representing the memory cell transistor MCT111 is input, the row decoder and the word driver circuit WD are about 12V and drive the word line with the program voltage Vp supplied from the voltage controller VC1. The comparator COMP outputs the address signal Add2 as the column address signal Add3 to the column decoder CD. The program amplifier PA supplies a supply voltage Vcc of about 5V to the column selectors CS1, CS2, CS3, CS4 and CSD via the data line DL. The column decoder CD decodes the address signal Add3 and outputs the column select signal YS to the column selector CS1 for driving the bit line BL11 to the voltage Vcc. At the same time, the transfer gate transistor TG1 is challenged in accordance with the control signal SC1 from the source line controller SCC in response to the address signal Add3. The voltage controller VC2 supplies the ground voltage Vgnd to the common source line SL. As a result, the channel current flows to the designated memory cell transistor, causing a channel hot electron (CHE) near its drain operation DR. These channel hot electrons are transferred from the control gate nationwide CGE to the floating gate nationwide FGE according to the high voltage Vp and, for example, increase the threshold voltage Vt of the memory cell transistor from about 2V unprogrammed to about 7V programmed. do. This programmed state corresponds with logical memory data, for example " 1. " The program mode operation in any other memory cell block is performed in the same manner as above. In such a device, each transfer gate transistor TG1, TG2, TG3, TG4 and TGD is required to carry the channel current of only one cell transistor MCT111, MCT112, ..., MCTD11 or MCTD12, thus eliminating the need for It can be formed in a very small and common size with the same drive capacity for the degree of integration of the device.

In the read mode operation of reading data from the memory cell transistor MCT111, the word line WL1 is driven at the voltage Vcc and the bit line BL11 is connected to the data line DL in the same manner as above. The read amplifier RA supplies a read voltage Vr of about 1V to the data line DL. The voltage controller VC2 supplies the ground voltage Vgnd to the source line SL 1 through the common source line SL and the transfer transistor TG1. In this case, since the memory cell transistor MCT111 has its limit voltage Vt of about 7V, the channel current is not blurred there and the voltage levels at the bit line BL11 and the data line DL are maintained at the read voltage Vr. The read amplifier RA detects a voltage level on the data line DL and outputs a high level read data signal representing logical memory data " 1. "

In the erase mode operation, since the redundant memory cell block DCB operates as part of the memory cell block CB1 when the memory cell block CB1 is erased, the redundant memory cell block DCB must also be erased. Therefore, the input address signal Add2 represents the memory cell block CB1. The comparator COMP compares the information of the address signal Add2 representing the memory cell block CB1 with the information of the defective address signal Add1 representing the memory cell block CB1, and compares the address signal Add3 representing both the memory cell block CB1 and the redundant memory cell block DCB. Output Therefore, the column selectors CS1 and CSD connect all of these bit lines BL11, BL12 and redundant bit lines BLD1, BLD2 from the erase controller EC to the data line DL to which the ground voltage Vgnd is supplied. Source lines SL1 and SL2 are provided with an erase voltage Ve of about 12V from voltage controller VC2 through common source line SL and transfer gate transistors TG1 and TGD. In contrast, the row decoder and word driver circuit WD maintains all word lines WL1 and WL2 at ground voltage Vgnd. The semiconductor substrate SUB is held at the ground voltage Vgnd. Thus, electrons geared to the floating memory nation FGE of the redundant memory cell transistors MCTD11 and MCTD12 and the memory cell transistors MCT111, MCT112, MCT11m, MCT121, and MCT122 in the programmed state are transferred to their source region by the FN tunnel effect. In this way, all memory cell transistors MCT111, MCTD11, etc. of the cell blocks CB1 and DCB are adjusted so as not to be programmed. In this case, according to the conventional memory device, the current consumption of all the erase operations is caused only by the FN tunnel effect of each memory cell transistor which causes only a very small current. Therefore, the transfer gage transistors TG1 and TGD are required to transfer currents caused by the plurality of memory cell transistors MCT111, MCTD11, etc. from or to the common source line SL, and the transfer gate transistors TG1 and TGD are mentioned above. As is common, it is formed in a very small size.

However, in this conventional device of the present invention, the erase voltage Ve required to be a high level voltage such as 12V in order to cause FN tunneling also causes a current between the source region SR and the semiconductor substrate SUB. This current is believed to be the result of the tunneling effect at the PN junction, such as the source region SR and the substrate SUB. In particular, when the floating gate nationwide FGE is filled with electrons at the negative voltage in the programmed state, this current is generated more effectively (hereinafter referred to as PN tunneling current) and becomes significantly larger than the FN tunneling current. Therefore, in the erase mode operation, especially in the programmed state, each of the memory cell transistors MCT111, MCTD11, etc., generates a large current that will greatly increase the total current to be delivered through each of the source lines SL1, SL2, SL3, SL4, and SLD. Thus, the transfer gate transistors TG1, TG2, TG3, TG4 and TGD are formed in a common small size and have a very small drive capacity intended to hold each source line SL1, ..., SL4 and SLD at the erase voltage Ve. As such, the voltage levels at source lines SL1, ..., SL4 and SLD are reduced from the erase voltage during the erase mode operation. Moreover, the voltage reduction at each of the source lines SL1, SL2, SL3 and SL4 is even larger than in the source line SLD depending on the number of memory cell transistors MCT111, MCT112, MCT11m, etc., connected to. As a result, the erase mode operation in the memory cell block CB1, CB2, CB3 or CB4 in this device requires a considerably longer time compared to the redundant memory cell blur DCB. Thus, if one of the memory cell blocks CB1, CB2, CB3 and CB4 and the redundant memory cell block DCB is to be erased at the time as described above, the erase mode operation is performed in the memory cell block CB1, CB2, CB3 or CB4. The memory cell transistors MCTD11 and MCTD12 of the redundant memory cell block DCB are excessively erased. In other words, the electrons of the floating gate nationwide FGE are transferred to the source region SR more than necessary so that the redundant memory cell transistors MCTD11 and MCTD12 are in a depression state. Once any of the memory cell transistors MTTD11 and MCTD12 are depressed, their associated redundant bit lines BLD1 and BLD2 are connected electrically to source line SLD in series, regardless of the voltage at word lines WL1 and WL2, and they are brought to normal lows. It will not work, and the device's total reliability will be extremely low. In contrast, if the erase all operation is performed for a time sufficient to erase only the memory cell transistors MCTD11 and MCTD12 in the redundant memory cell block DCB, the memory cell transistors MCT11, MCT112 in the memory cell blocks CB1, CB2, CB3 or CB4. , MCT11m, etc., are not sufficiently erased, which impedes the normal functioning of the device.

[Summary of invention]

It is therefore an object of the present invention to provide a semiconductor memory device having a redundant memory cell block in which a data erase operation is performed with high reliability. The memory device according to the present invention is characterized in that the transfer gate provided in the memory cell array has a current driving capability greater than that of the transfer gate provided in the redundant memory cell array. With this feature, it is supplied to the required cell array by suppressing the transient current flowing through the redundant memory cell array. As a later feature, by suppressing the transient current flowing through the redundant memory cell array, the required current is supplied to the cell array. Hereinafter, with reference to the drawings will be described in more detail the above and other objects and advantages and features of the present description.

[Detailed Description of Appropriate Embodiments]

Referring to FIGS. 1 and 2, a memory device according to an embodiment of the present invention may include transfer gate transistors TG11, TG1n, TG21, each of which is shown in FIG. 1, in which memory cell blocks CB1, CB2, CB3, and CB4 are illustrated in FIG. 1. Multiple subblocks SB11, SB1n, SB21, SB2n, SB31, SB3n, SB41, and TG4n, respectively, associated with one of the transistors TB2n, TG31, TG3n, TG41, and TG4n, respectively. Except having SB21, SB2n, SB31, SB41, and SB4n, it has the same structure as the conventional apparatus. The memory cell block CB1 and the redundant memory cell block DCB are shown in detail in FIG. The other memory cell blocks CB2, CB3 and CB4 have the same configuration as the memory cell block CB1. As shown in FIG. 2, the redundant memory cell block DCB includes two redundant bit lines BLD1 and BLD2, and the memory cell block CB1 has two bit lines BL11 / 1 and BL11 / 2, ..., respectively. And n subblocks SB11, ..., SB1n comprising BL1n / 1 and BL1n / 2. That is, the memory cell block CB1 includes a plurality of memory cell transistors T11 / 11, ..., T11 / 22, such as transistors of the redundant memory cell block DCS. Each of the subblocks SB11, ..., SB1n of the memory cell block CB1 is associated with each of the source lines SL11, ..., SL1n. In each of the sub-blocks SB11, ..., SB1n, the sub-block SB11, which is typical for example, has the same method as each memory cell transistor T11 / 11, T11 / 12, T11 / 21 and T11 / 22 are shown in FIG. And a control gate nationwide CGE, drain region DR, and source region SR connected to one of word lines WL1 and WL2, one of bit lines BL11 / 1 and BL11 / 2, and source line SL11, respectively. Source line SL11 is selectively connected to common source line SL via transfer gate transistor TG11. Therefore, in this apparatus, the sub-blocks SB11, SB1n, SB2, SB2n, SB31, SB3n, SB41 and the transfer gate transistors TG11, TG1n, TG21, TG2n, TG31, TG3n, TG41, and TG4n associated with each, Each of the transfer gate transistors TGD associated with the redundant memory cell block DCB is formed in a small size with the same number of bit line angles, the same number of memory cell transistors, and with a common driving capability as described below.

Further, in the above apparatus, for example, if a memory cell transistor which is a transistor T11 / 11 has a defect, a column address signal representing the defective transistor is detected and programmed in advance in the address latch circuit AL as a defective address signal. Therefore, the input column address signal Add2 which is the same as the defective address signal is replaced by the duplicate column address signal AddR1 or AddR2. That is, the bit line BL11 / 1 is replaced with the redundant bit line BLD1 or BLD2.

Next, the program mode operation will be described with the same condition that the bit line BL11 / 1 is replaced by the redundant bit line BLD1. First, the clock generator CG outputs the high level control signal? 2 according to the external input signal PGM. The address buffer AB to which the address signal Add is supplied outputs the row address signal Add1 to the row decoder and the word sync circuit WD and the column address signal Add2. Output to comparator COMP. At the same time, the voltage controller VC1 supplies the program voltage Vp which is about 12V in accordance with the control signal? 2 to the row decoder and the word driver circuit WD for driving the word line WL1 to the voltage Vp in accordance with the row address signal Add1. Comparator COMP compares the input column addresser signal Add2 with a defective address and replaces the address signal with a duplicate address signal AddR1 as will be described later. Accordingly, the redundant memory cell block DCB serves as part of the memory cell block CB1 instead of the sub block SB11, for example. In the meantime, the program amplifier PA supplies the power supply voltage Vcc of the device, which is activated by the control signal? 2, to about 5V, to the column selectors CS1, CS2, CS3, CS4 and CSD via the data line DL. The column decoder CD decodes the address signal Add3 representing the redundant bit line BLD1 in place of the bit line BL11 / 1, and outputs the column select signal YS to the column selector CSD which drives the bit line BLD1 with the voltage Vcc. In contrast, the source controller SCC also decodes the address signal Add3, and outputs the control signal SCD to the transfer gate transistor TGD, which is thus switched to the conducting state. The voltage controller VC2 is a common source line SL electrically connected to the source line SLD of the redundant memory cell block DCB through the transfer gate transistor TGD, and supplies the ground voltage Vgnd according to the control signal ψ2. Therefore, the channel current flows in the redundant memory cell transistor MCTD11, causing a channel hot electron (CHF) near its drain region DR. These channel hot electrons are transferred from the control gate nationwide CGE to the floating gate nationwide FGE according to the high voltage Vp, for example as described above, from about 2V unprogrammed to about 7V programmed. Increase the threshold voltage Vt. The programmed state is for example consistent with logical memory data " 1. " In this case, similar to the conventional apparatus, the transfer gate transistor can be formed in a small size since it is required to transfer only the current generated by only one memory cell transistor MCT11.

In the read mode operation, the clock generator CG activates the dominant amplifier RA to supply a read voltage Vr of about 1 V to the column selector CSD through the data line DL when the address signal Add representing the memory cell transistors MCT11 / 11 is input. The control signal ψ3 is output in accordance with the external input signal OE. The column decoder CD and column selector CSD select the bit line BLD1 in the same manner as the program mode operation and supply the read voltage Vr. Further, word line WL1 is selected to be driven at voltage Vcc in accordance with address signal Add1 from address buffer AB, and memory cell transistor MCTD11 is selected. In this case, the source line controller SCC also selects the transfer gate transistor TGD in accordance with the address signal Add3. The voltage controller VC2 outputs the ground voltage Vgnd in accordance with the control signal ψ3. Thus, the source line SLD is maintained at ground voltage. In this case, the memory cell transistor MCTD11 is programmed to have a threshold voltage Vt of about 7V so that no channel current flows there. Thus, the voltage levels at bit line BLD1 and data line DL are maintained at read voltage Vr, so that read amplifier RA detects the voltage level at data line DL and outputs a high level read data signal representing logical memory data " 1. " . In this read mode operation, however, if the selected memory cell transistor MCTD11 is in an unprogrammed state, a channel current will be generated there, causing a voltage drop at the bit line BLD1 and the data line DL, and the read amplifier RA will generate a logical memory data “0”. Outputs the low level read data signal indicated.

In the erase mode operation, when the memory cell block CB1 is erased in the same manner as the conventional apparatus described above, the redundant memory cell block DCB acts in place of the sub-clock SB11 of the memory cell block CB1, so that the redundant memory cell block DCB must also be erased at the same time. That is, the clock generator CG first outputs the control signal ψ 1 according to the external input signal EE from the address buffer AB to the comparator COMP supplied with the address signal Add2. In this case, the address signal Add2 represents the memory cell block CB1. Therefore, the comparator COMP compares the information indicating the memory cell block CB1 included in the defective address signals AddD1 and AddD2 with the input address signal Add2 in accordance with the control signal? 1. That is, each defective address signal AddD1 and AddD2 is composed of a block address signal AddK1 or AddK2 representing a memory cell block CB1, and a bit line address signal AddT1 or AddT2 representing one line of the bit lines of the cell block CB1. The comparator COMP activated by the control signal ψ1 compares with the block address signal Add2 of each of the defective address signal AddD1 or AddD2, and if they coincide with each other, the address signal Add3 indicating both the memory cell block CB1 and the redundant memory cell block DCB. Outputs In response to the control signal ψ1 and the address signal Add3, the column decoder CD selects the bit lines BL11 / 1, BL11 / 2, ..., BL1n / 2 and the redundant bit lines BLD1, BLD2 and connects them to the data line DL. The column select YS is output to the block CB1 and the redundant memory cell block DCB. The data line DL is supplied with the ground voltage Vgnd from the erasing controller EC to which the control signal? 1 is supplied. In the meantime, the source line controller SCC according to the control signal ψ1 and the address signal Add3 has generated the transfer gate transistors TG11, ..., TG1n and transfer the control signals SC1 and SCD, so that the memory cell block CB1 is transferred to the common source line SL. The total current to be delivered to the common source line SL is significantly greater than the current caused by the redundant memory cell block. However, according to this embodiment, the memory cell transistors T11 / 11, ..., T1n / 22 of the memory cell block CB1 are n sub-blocks SB11, ..., SB1n associated with the transfer gate transistors TG11, ..., TG1n. A redundant memory cell block DCB associated with the transfer gate transistor TGD, each of which is divided into and includes the same number of memory cell transistors T / 11/11, ..., T11 / 22, and transfer gate transistors TG11, ..., Since TG1n and TGD are formed in the same size with the same driving capability between each other as mentioned above, the source lines SL11, ..., SL1n and SLD are almost close to the same voltage level as the erase voltage Ve and have the same voltage level between each other. Is maintained at. Thus, all the memory cell transistors T11 / 11, ..., T11 / 22 and MCTD11, ..., MCTD22 of the memory cell block CB1 and the redundant memory cell block DCB are adjusted so as not to be programmed at the same time. Therefore, according to the above embodiment, the memory cell block CB1 and the redundant memory cell block DCB have different numbers of memory cell transistors T11 / 11, ..., T1n / 22 and MCTD11, ..., MCTD22, respectively. The voltages in the source regions RE of the memory cell transistors T11 / 11, ..., T1n / 22 and MCTD11, ..., MCTD22 are maintained at the same level during the erase mode operation, so that all the memory cell transistors for which the erase mode operation is to be erased T11 / 11, ..., T1n / 22 and MCTD11, ..., MCTD22 are executed to be sufficient and normally erased simultaneously. As a result, the device of this embodiment can safely utilize a redundant memory cell block which makes the total operation reliability very high.

3 shows a memory device according to another embodiment of the present invention. The device has almost the same structure as the device of the first embodiment described above, except that the memory cell blocks CB1, CB2, CB3 and CB4 are each source line SL101, SL102, each connected to a respective transfer gate transistor TG101, TG102, TG103 or TG104. The only difference is that SL103 or SL104 is compared. Each memory cell block CB1, CB2, CB3 and CB4 (for example CB1) has K bit lines BL1 / 1, ..., BL1 / K, and the redundant memory cell block DCB has two bit lines BLD1 and BLD2. . That is, the memory cell block CB1 includes the memory cell transistors T1 / 1/1 /, ..., T1 / 2 / K which are K / 2 times the redundant memory cell block DCB as shown in FIG. In addition, the transfer gate transistor T101 has a driving capability K / 2 times larger than the transfer gate transistor TGD associated with the redundant memory cell block DCB. The memory cell blocks CB2, CB3 and CB4 and the transfer gate transistors TG102, TG103 and TG104 have the same configuration as the memory cell blocks CB1 and the transfer gate TG101. The driving capability of the transfer gate transistors TG101, TG102, TG103, TG104 and TGD, which are of the MOS type, is determined by adjusting the gate width in the channel region, the gate like, or the impurity concentration.

The operation of the apparatus is almost the same as the apparatus of the first embodiment. Therefore, in the erase mode operation according to this configuration, for example, when the memory cell block CB1 and the redundant memory cell block DCB are to be erased at the same time, the two memory cell blocks have different numbers of memory cell transistors T1 / 1/1 //, ..., T1 / 2 / K and MCTD11, ..., MCTD22, the voltage levels at source lines SL101 and SLD remain at the same level with the erase voltage Ve, despite the PN tunneling current. In addition, the device can safely utilize the redundant memory cell block, and can increase the operation reliability.

The present invention is not limited to the above embodiments, and various changes and modifications can be made without departing from the scope and spirit of the present invention.

Claims (9)

A semiconductor memory device comprising: a first memory cell array including a plurality of first memory cells, a second memory cell array including a plurality of second memory cells smaller in number than the first memory cell, and A first voltage generator operable to generate a voltage and a first current capability coupled between the first memory cell array and the voltage generator to operably supply the predetermined voltage to each of the first memory cells; Means and a second current capability less than the first current capability, coupled between the second memory cell array and the voltage generator to operatively supply the predetermined voltage to each of the second memory cells. And a means. 2. The apparatus of claim 1, wherein the first means comprises a plurality of first transfer transistors controlled by a first control signal such that each of the first means is in one of a conductive state and a non-conductive state simultaneously. And at least one second transfer gate transistor controlled by a control signal and smaller in number than the first transfer gate transistor. 3. The display device of claim 2, wherein each of the first transfer gate transistors is connected to an associated cell of the first memory cells, and wherein the associated cell of the first memory cell is connected to the at least one second transfer gate transistor. And the first transfer gate transistors each having a current capacity substantially equal to the current capacity of the at least one second transfer gate transistor. 2. The method of claim 1, wherein the first means comprises a first transfer gate transistor having the first current capability and the second means comprises a second transfer gate transistor having the second current capability. A semiconductor memory device. A semiconductor memory device, comprising: a memory cell array having a plurality of word lines, a plurality of bit lines, and a plurality of memory cells each connected to one of the word lines and one of the bit lines; The memory cell array is divided into a plurality of first memory cell blocks and a second memory cell block, and the second memory cell block includes a predetermined number and a second signal line connected to each of the memory cells and the memory cells included therein. Each of the first memory cell blocks is divided into a plurality of sub blocks each having a predetermined number of the memory cells, each of the sub blocks further comprising: a first signal line connected to each of the memory cells included in the block; A voltage controller operatively generating a control voltage at an output node thereof, the voltage signal being associated with said first signal line of said subblock. And a plurality of first transfer gates connected between a line and the output node of the voltage generator, and a second transfer gate connected between the second signal line and the output node of the voltage generator. . The memory cell of claim 1, wherein each of the memory cells comprises a control gate connected to a related one of the word lines, a drain connected to a related one of the bit lines, and a source connected to a related one of the first and second signal lines. And a memory cell transistor having the semiconductor memory device. 2. The semiconductor memory device of claim 1, wherein the current capability of each of the first transfer gates is the same as the second transfer gate. The semiconductor memory device of claim 1, wherein each of the first transfer gates is divided into a plurality of groups corresponding to a related block among the sub-blocks, and the first transfer gates of each group are simultaneously conductive to each other. . A semiconductor memory device, comprising: a memory cell array having a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to one of the word lines and one of the bit lines, respectively; The memory cell array is divided into a first memory cell block having a first plurality of the memory cells and a second memory cell block having a second plurality of the memory cells less than the first number, the first memory cell block having the first plurality of memory cells. Each of the memory cell blocks has a first signal line connected to each of the memory cells included in the memory cell block, and the second memory cell block may further include a second signal line connected to each other and a control voltage. A voltage generator operatively generated at an output node, one associated line of said first signal lines and said output node of said voltage generator, respectively And a plurality of first transfer gates having a first driving capability, and a second transfer gate having a second driving capability, connected between the second signal line and the output node of the voltage generation. And the ratio of the first driving capability to the second driving capability is equal to the ratio of the second number between the first number and the second number.