KR960004735B1 - Multiport memory - Google Patents

Abstract

No content.

Description

Multiport Memory

1 is a schematic diagram of an application of a two-port memory.

2 is a structural opening diagram of a conventional two-port memory.

3 is a partial schematic diagram of a peripheral circuit of a memory cell array of a conventional two-port memory.

4 is a partial schematic view of one memory cell of a conventional two-port memory.

5 is a partial schematic diagram of a peripheral circuit of a memory cell of a conventional four-port memory.

6 is a structural opening diagram of a two-port memory of the present invention.

7 is a partial schematic diagram of a peripheral circuit of a memory cell array of a two-port memory of the present invention.

8 is an operation explanatory diagram of a two-port memory of the present invention.

9 is a partial schematic diagram of a peripheral circuit of a memory cell array of a four-port memory of the present invention.

10 is a wiring diagram of respective ports and short-circuit transistors of the 4-port memory of the present invention.

The present invention is to prevent data write and write of a multiport memory, such as a so-called two-port memory, and to improve the reliability of data writing.

First, the background of the appearance of the multiport memory will be described. In a known conventional semiconductor memory, a pair of CPUs are connected to only one semiconductor memory, so that the processing is divided between the CPUs and the single semiconductor memory by a data bus line for transmitting and receiving information. However, when a plurality of CPUs share a common data busline, another CPU cannot naturally transmit data from this semiconductor memory while one CPU sends or receives data from the semiconductor memory. Therefore, even if a plurality of CPUs are connected to a normal semiconductor memory, a plurality of CPUs can never be simultaneously connected to a semiconductor memory in order to simultaneously transmit and receive data.

The multiport memory to which the present invention is applied can realize simultaneous data transmission by a plurality of CPUs that cannot be realized by the conventional semiconductor memory.

That is, the multiport memory has a plurality of ports for a single memory cell array, and the CPUs are connected to the respective ports so that the sharing processing is possible by each CPU. Multi-port memory is most commonly used as one port is provided on the left and right sides of the memory cell array and is called a 2-port memory.

The multiport memory will be described in more detail.

1 is an opening diagram of an application example of a conventional two-port memory. In FIG. 1, the two-port memory 22 has left and right ports not shown, and is connected to the left ported CPU 23 while the right port is connected to the CPU 24. In FIG. The CPU 23 is connected to a peripheral device 25 for processing, and the CPU 24 is connected to a peripheral device 26 for outputting a processing result.

As an example of the effect of the high speed processing by the two-port memory, a test of the semiconductor memory can be considered. For example, when testing a newly manufactured semiconductor memory, each cell must be sequentially checked in a wide memory cell array of the semiconductor memory so that the defective cells must skip over those defective cells. However, to complete the test quickly, it is important to continue the two tasks at the same time by skipping the defective cell and continuing the test for the normal cell. In this case, if the processing peripheral device 25 instructs not to test the combined cell, this instruction is sent to the two-port memory 22 for the write operation via the CPU 23. On the other hand, the test result can be output through the CPU 24 from the peripheral device 26 which reads the information stored in the 2-port memory 22 and outputs the processing result. In this case, the 2-port memory 22 generates a busy signal to stop any of the CPUs and delays the issuance of the instruction so that the write request and the read request are generated at the same address and write from the left port. The request and the read request from the right port are suppressed from being executed at the same time. In other cases, however, the access of each port is not the same address.

Therefore, the above-described two-port memory divides one data bus line into two CPUs, and one of the two CPUs transfers data to the memory cells, thereby making the access speed much higher than that of the conventional semiconductor memory device.

Conventional two-port memories are summarized as described above.

Next, the two-port memory 22 will be described in detail with reference to FIG. 2 is an explanatory view of a known two-port memory. In FIG. 2, memory cell arrays 2a, 2b, which operate as memory media in a two-port memory, are connected to many row select lines (word lines) and column select lines (bit lines), not shown. SRAM is formed by (static random access memory). Furthermore, the two-port memory has two row select lines (word lines) and two column select lines (bit lines) corresponding to the right and left ports. The right bit lines are connected to the right decoders 11a and 11b, the left bit lines are connected to the left column decoders 6a and 6b while the right word lines are to the right decoders 10 and the left word line to the left It is connected to the decoder 5. The left I / O buffer 4 is also connected to the left decoders 6a and 6b for data input via the left I / O circuits 7a and 7b. In the same way, the right I / O buffer 9 is supplied to the right column decoders 11a and 11b for data input via the right I / O circuits 12a and 12b and also through the left address buffer 3. It is also supplied to the left low decoder 5 and the left column decoders 6a and 6b. In order to simply improve the access speed of the memory throughout the specification, the memory cell array embedded in the non-isolated region is divided into cell arrays 2a and 2b and the right row decoder 10 and the left side between the arrays 2a and 2b. The low decoder 5 has been described as being provided. That is, as a whole, since the access speed of the memory is controlled by the access speed for the memory cell furthest from the decoder, it is necessary to have all the memory cells as lightest as possible in the decoder. In addition, the above-described configuration is effective to solve the problem that the load of the word lines increases as the distance between the low decoder and the word line increases, thereby reducing the reliability of reading and writing information from or to the memory cell.

Also, a part of a circuit in the memory cell arrays 2a and 2b will be described with reference to FIG.

In FIG. 3, a plurality of right bit line pairs B _{R R} extending in the vertical direction between the memory cells. ) And left bit line pairs (BL _L , ) And a plurality of right word lines WL _R extending in the horizontal direction and word lines WL _L , and the gates may include a left bit line pair BL _L , ), The upper end of the figure may be the left port. In the same way, the gates are the right bit line pair BL _R , ), The left end of the figure may be the right port. Data bus lines are independent on the right and left sides. At the upper end, that is, at the left port side, the left data bus line pair (DL _L , ) Is the left bit line pair (BL _L , ) At the lower end, ie on the right port side, the right data bus line pair (DB _R , ) Is the right bit line pair (BL _R , ) 4 is a detailed diagram of peripheral circuits of one mori cell. As shown in FIG. 4, a conventional multiport memory generally provides memory cells each having a flip-flop structure like a conventional SRAM. In Fig. 4, reference numerals 13 and 14 represent n-channel MOS transistors in which drain and gates are cross-coupled, and 15 and 16 represent load drops of n-channel MOS transistors 13 and 14. The memory cells 17 constituting the flip-flop are formed by these n-channel MOS transistors 13 and 14 and load resistors 15 and 16. WL _L denotes the word line of the left port, 18 and 19 denote the transfer gate transistor (n-channel MOS) of the left port, and BL _L , Are the bit lines of the left port, WL _R are the word lines of the right port, 20, 21 are the transfer gate transistors (n-channel MOS) of the right port, BL _R , Indicates the bit lines of the right port. According to such a memory cell 17, access from the left port can be realized by operating the word line WL _L and access from the right port can be realized by operating the word line WL _R.

In the two-port memory shown in FIG. 2 providing such a memory cell 17, when the addresses A _{OL to} An _L are input from the left port to the left address buffer 3, part of the address (row address) is _lost. The left row decoder 5 and the rest are sent to the left column decoders 6a and 6b. As a result, the left row decoder 5 selects the row specified by the row address and the left column decoders 6a and 6b select the column specified by the column address. Thereby, the memory cells designated by the addresses A _{OL to} An _L are selected. The selected memory cells are electrically connected to the left I / O circuits 7a and 7b to perform read and write operations. Here, the left I / O buffer 4 is a chip select signal ( ) And writable signal ( Is controlled to be readable and writable from the memory cells or through the left I / O circuits 7a and 7b thereto. Read and write operations may be performed on the memory cells in the same manner with respect to the right port.

FIG. 3 shows a plurality of rows and columns forming the memory cell array 17 shown in FIG. In FIG. 3, reference numerals 27 and 28 denote load transistors (n-channel MOS) for maintaining the level of the bit lines BL _L , of the left port, and 29 and 30 denote column select transistors ( n-channel MOS), Y _L is a column select signal for controlling the column select transistors 29, 30 ON / OFF state DB _L , Are data lines, 31, 32 are data bus lines (DB _L , Load transistors to maintain the level of?). Where the data bus lines (DB _L , The illustration of the sense amplifier connected to) is omitted.

Also, reference numerals 33 and 34 denote bit lines BL _R of the right port. Load transistors (n-channel MOS) to maintain the level of < RTI ID = 0.0 >),< / RTI > 35, 36 turn on the column select transistors (n-channel MOS), and Y _{R turn} on / off these column select transistors The column select signal for controlling to OFF state is DB _R , Are the data bus lines, 37, 38 are the data bus lines (DB _R , Load transistors (n-channel MOS) for maintaining the level of N, 39 are write circuits, 40-43 are n-channel MOS transistors, and IN _R and IN _R are write input terminals. Where the data bus lines (DB _R , The illustration of the sense amplifier connected to) is omitted.

Here, consider data writing from the right port to the memory cell 17. However, in this case, it is assumed that the left port does not select rows not writing from the right port. That is, assume that the H level is applied to the word line WL _RO and the L level is applied to the word line WL _LO . When the H data is written into the memory cell 17, the H level and the L level are respectively written in the write data IN _R ,. Is applied. In this case, when the n-channel MOS transistors 41 and 42 of the write circuit 39 are turned on and the n-channel MOS transistors 40 and 43 are turned off, the H level is thereby changed to the data bus line DB _R. And L-level data bus lines ) These meta buslines (DB _R , Levels of the bit lines BL _R , through the column select transistors 35 and 36. ) Is transferred to the bit line B _{R R} to H level. ) To L level. As a result, the node 44 of the memory cell 17 is at the H level, and the node 45 is at the L level. Thereby, the H data can be written into the memory cell 17.

In this case, the bit line where the L level is to be set ( ) Level of the bit line ( Load current and data bus line caused by the load transistor 34 of The level of floating level because the mutual conductance Gm of the load transistors 34 and 38 caused by the load transistor 38 of the C) is set smaller than that of the transistor 42 of the write circuit 39. Is very small, (usually around several hundred mV). As a result, in the data write mode, this level is transferred to the node 45 of the memory cell 17 through the transfer gate transistor 21.

This level is sufficient to turn off the transistor 13 cross-coupled with the transistor 14, so that a stable write operation can be ensured in this case.

However, even in the same row, when accessing different memory cells from the right and left ports, there is a risk of write-in. Such access is described below.

When writing data from the right port to the cell A located in the outermost column in the figure, the left port accesses the same row accessed by the right port. In this situation, the right word line WL _RO and the left word line WL _LO become the same H level. At that time, the terminals IN _R of the writing circuit 39 shown in the lower part of the figure are H level and the terminals ( ) Is at the L level, so that high data can be written into the cell 17.

In order to select the outermost column, Y _RO is set to H level to turn on the column select transistor, while the upper right word line WL _LO is set to H level to the right bit line pair BL _R ,. ) And the cell becomes conductive.

In the following description, the right bit line pair BL _R , Think only about the bit line (BL _R ). When the gate reaches the level of the input terminal IN _R , the right bit line ( ) Becomes the L level, so the L level is naturally transmitted to the node 45 of the cell. However, it should be noted that both the data busline and bitline are connected to the load transistors to maintain the level. Since the load transistors are connected to the gate and the cell side more than the column select transistor, when the column select transistor is turned on, the bit line ( ) Must descend to L level completely.

However, the V _CC level is transmitted through the load transistor and also the bit line ( ) Level is floated.

Further, consider simultaneously executing the read operation through the left port from the cell B in the same row as the cell to which data is written. In this case, the left word line WL _L of the row where the cell B is present must be on. However, since the left word line WL _L is also connected to the cell A in which data is to be written to the right port, the left bit line pair BL _L , of the column in which the cell A exists is present. ) Is connected to the cell (A). Left bit line pair (BL _L , ) Is also connected to the load transistor, so the above-mentioned problem of stray level is intensified.

In this case, the left word line WL _LO is set at the H level. For this reason, the current flows from the bit line (left) of the left port. 2) flows from the load transistor 28 of the load transistor 28 to the node 45 of the memory cell 17 through the transfer gate transistor 19 of the left port of the memory cell 17. In addition, when not only the same row but also the same column is selected by the right and left ports, the column select transistor 30 of the left port is turned on, so that the data bus line of the left port ( Current from the load transistor 32 also flows to the node 45 of the memory cell 17.

The current flowing from the left port to the node 45 is also absorbed by the write transistor 42 of the right port through the transfer gate transistor 21 of the right port of the memory cell 17 and the column select transistor 36 of the right port. . As described above, if both the lower right and left ports select the same low, the write transistor 42 must absorb a large portion of the load current, so that the bit line ( ) Level rises.

When the two bit lines are conductive to the cells, the right and left bits have the same channel length and channel width, that is, gm, by design for the transistor connecting the left bit line and the cell and the transistor connecting the right bit line and the cell. The level of the lines is divided by the resistive components through the combination of transistors 19 and 21. That is, the level of the node 45 of the memory cell 17 includes the gm ratio of the transistors 19 and 21 and the bit line ( Level and bit line of the power supply voltage V _CC -threshold voltage Vth of the load transistor It is equal to the level obtained by dividing by) level (about several hundred mV).

Here, since the transfer gate transistors are typically designed with the same channel length and channel width, the floating of the level is further accelerated and the level of the node 45 is increased to about 1.5 to 2.5 [V]. At this level, the n-channel MOS transistor 13 cross-coupled with the n-channel MOS transistor 14 cannot be turned off, so the write operation becomes unstable, so that the L data is written instead of the H data.

This problem is not localized in a two-port memory, but there are a plurality of ports and each port is provided with bit lines and word lines, but each bit line and word lines are connected to cells through select transistors. -Also occurs in Port Melory.

4-port memory

An example of the four-port memory will be described. 5 is a schematic diagram showing one row of a memory cell array of a four-port memory and its peripheral circuits. In FIG. 5, four word lines are extended from the first word line WL1 to the fourth word line WL4 corresponding to four ports in the horizontal direction of the drawing. Meanwhile, in the vertical direction, the first bit line pair BL1, ) To fourth bit line pair BL4, The four bit line pairs of the Cs are serially corresponding to the four ports. Each static memory cell is provided in an area surrounded by a bit line pair and a word line. In addition, the four data bus pairs (DB1, ,… … DB4, ) Extends horizontally corresponding to each port.

A column select transistor is provided at an end portion of each bit line extending in the vertical direction. When this column is selected for read or write operations, this column select transistor is turned on to connect the data bus lines and bit lines that are normally separated.

Here, assume that the H level is written from the third port by selecting the static memory cells (J in FIG. 5) contained in the second row of the four-port memory. In this case, the input terminals IN3 of the third gate, H level is applied to IN3, while L level is applied to IN3. Therefore, among the transistors Tr1 to Tr4, Tr1 and Tr4 are turned off while Tr2 and Tr3 are on. The bit line BL3 rises to the H level, and the bit line BL3 ) Drops to L level. The column select signal Y3 becomes H level to turn on the two column select transistors provided for the third bit line pair. When the third word line WL3 is at the H level, the transistor is turned on so that the third bit line pair BL3, ) And the static memory cell J are electrically connected.

In this case, another static memory cell which executes a read operation through the first port is present in the same row of the static memory cell J (right side not shown) from J and another that executes the read operation through the second port. The static memory cells are also present in the same row of the same static memory cells. Since the first and second word lines are on in the second row, the two transistors connected to these word lines through the gates are also on.

As a result, the static memory cells are connected to the first bit line pair, the second bit line pair, and the third bit line pair so that a current is connected to the input terminal through a load transistor connected to each bit line pair. To the L bit so that it must be at the L level ) Level is floated to a higher value.

The selection of the same row from multiple ports is a matter of course, so the chance of this selection increases as the number of ports increases. This problem is also aggravated as the capacity of the two-port memory increases. Therefore, as the capacity of the two-photo memory increases, it becomes more serious. Therefore, it is necessary to miniaturize the transfer transistors connected between the memory cell and the bit line because the capacity of the 2-port memory must be increased but the chip size must be reduced. However, if the transport transistors are made very small in size, the characteristics of each transport transistor of a plurality of ports are changed by process variation.

Therefore, it is an object of the present invention to further improve the reliability of the write operation of the multiport memory by eliminating the problem of writing into and out of cells while selecting the same row from a plurality of ports commonly occurring in the multiport memory as described above. It is. The structure of the multiport memory of the present invention can be summarized as follows. That is, a bit may be shorted by shorting bit lines corresponding to ports used for data writing and reading operations only when a write operation is performed from another port to another memory cell arranged in the same row as a memory cell during a read operation from one port. It is possible to prevent the level floating of the lines.

The multi-port memory of the present invention specifically includes a plurality of ports for read and write operations corresponding to one memory cell, and detects that a plurality of memory cells included in the same column are selected for read or write operations. And a switch for shorting the bit lines corresponding to the ports used for the read or write operation with the address match detection circuit, wherein the switch is turned on when the row address match detection circuit detects such a selection. have.

More specifically, the multi-port memory of the present invention, a plurality of ports provided in the static memory cell for read and write operations, a plurality of bit lines and word lines provided corresponding to the plurality of ports, A switch for electrically connecting bit lines and other bit lines corresponding to the word lines to the static memory cell according to the level of word lines, and a plurality of read or write operations for a plurality of word lines included in the same row. And a short circuit that short-circuits the bit lines corresponding to the ports selected for the write operation among the bit lines corresponding to the plurality of selected ports and any other bit lines when selected from the ports. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, a two-port memory having a pair of ports will be described, followed by a four-port memory.

2-port memory

An embodiment of the present invention will be described with reference to Figs. The same parts in the drawings are given the same reference numerals and redundant descriptions are omitted.

6 is a structural opening diagram of the two-port memory of the present invention. Referring to this figure, since there is no technical difference from the conventional two-port four memory, the same number is given. The only difference from the prior art is to input the output of the address buffers to the row address match detection circuit.

Also, although not shown in the figure, the newly added structure is that the output of this row address match detection circuit is input to the gate of the short circuit transistor provided at the end of the bit line columns of the memory cell array.

The row address matching detection circuit is inputted to the left address signal corresponding to the left and the right port address signal that is input corresponding to the right port _{(A OR ~A IR) (A} OL ~A IL) is input In addition, these address signals Have a structure in which a match is detected.

In this embodiment, part of the memory cell array is formed as shown in FIG. The difference from the prior art shown in FIG. 3 is that short-circuit transistors (n-channel MOSs) 46 and 47 are provided on the upper side to short-circuit the right and left bit lines of each column. Here, the bit line short-circuit transistor 46 through the drain is connected to bit lines (BL _L) of the left port also connected to a bit line (BL _R) for the right port through the source. In addition, the bit short circuit transistor 47 passes through the bit line of the left port ( ) And through the source to the bit line ( ) Is also connected. The output of the low address coincidence detection circuit 48 shown in FIG. 6 is connected to the gates of these short circuit transistors 46,47. If the low addresses input from the right and left shafts are considered to be matched as a result of the comparison, the output is set to H level and the gate is turned on, whereby the right and left bit lines are shorted to each other.

In addition, in the low address matching detection circuit 48, the left low address signals A _{OL to} A _IL shown in FIG. 6 and the right address signals A _OR to output from the right row address buffer 8 are shown for each bit. A _IR ) is divided and input to the exclusive OR circuits 52 _O to 52 _I. Exclusive OR paths 52 _O to 52 _I provided for each row address bit output an L level when the row address bits match or output an H level when the row address bits do not match.

The outputs of the exclusive OR circuits are input to the NOR circuit 53 at a time and their outputs are input to the gates of the short circuit transistors 46 and 47 to control on and off.

If the outputs of the exclusive OR circuits match in all the address bits, the NOR circuit 53 outputs the H level as the row address matching detection circuit AM, and the L level as the mismatch signal AM. The other structure is the same as that of the conventional two-port memory of FIG.

8 is a time chart for explaining the operation of an embodiment of the present invention. At time T1, the left row address A _L fluctuates and this left row address A _L coincides with the right row address A _R. At time T2, the left row address A _L fluctuates and this left row address A _L does not coincide with the right row address A _R.

First, since the left row address A _L and the right row address A _R do not coincide until the time T1, the row address coincidence detection signal AM is at the L level. As a result, the bit line short circuit transistors 46 and 47 are turned off, so that the bit lines BL _L , of the right and left ports are turned off. And BL _R , ) Performs the operation of each port, so there is no mutual interference of signals.

However, if the left row address A _L and the right row address A _R coincide at time T2, the address coincidence signal AM becomes H level. As a result, the bit line transistors 46 and 47 are turned on so that the bit lines BL _L ,. And BL _R , ) Is short circuited.

Thereafter, the left row address A _L and the right row address A _R do not coincide at time T2. As a result, the low address coincidence detection signal AM becomes L level, and the bit line short circuit transistors 46 and 47 are turned off.

As discussed in the case of FIG. 3, when the row select line WL _L of the left port and the row select line WL _R of the right port are set at the H level, for example, from the right port to the memory cell. For example, H data is written.

In this case, in this embodiment, the bit line of the left port ( Current from the load transistor 28 through the bit line short circuit transistor 47 ) And is absorbed by the write transistor 42 through the column select transistor 36 in the right port. Here, when the mutual conductance Gm of the bit line short circuit transistor 47 is set to a high value, the bit line ( L level is the bit line ( Can be lowered to almost the same level as L level.

Here, the L level of the node 45 of the memory cell 17 corresponds to the bit lines ( , It becomes the low level same as L level of (). Therefore, the MOS transistor 13 in the memory cell 17 shown in FIG. 4 (refer to FIG. 4 used to describe the related art because the memory cell 17 itself is not different from the conventional one) can be turned off. Can achieve a stable writing operation.

When the read operation is performed from the right and left ports, the bit line short circuit transistors 46 and 47 are not disturbed.

This is because the bit lines of the two ports of each column realize the same operation. Further, due to the limitation of the chip area, the transfer gate transistors 18 to 21 of the memory cell 17 cannot set their channel widths wide. However, according to the present invention, it is possible to set the channel width W wider because only a pair of bit line short circuit transistors 46 and 47 are disposed in each column.

Therefore, in the present invention, it is possible to set the mutual conductance gm to a higher value.

4-port memory

Next, an example of 4-port memory will be described.

9 is a partial schematic diagram of one column of a memory cell array of a 4-port memory and its peripheral circuits. FIG. 9 shows bit line pairs as compared to FIG. , ), ( , ), (, ), ( , A short circuit transistor is provided to short-circuit two bit lines and to short-circuit the corresponding two lines BL ₁ , BL ₂ , BL ₃ , and BL ₄ .

The gates of the short circuit transistors provided on the bit lines BL ₁ , BL ₂ , BL ₃ , BL ₄ (upper part of FIG. 9) are connected to the bit lines ( , , , Is connected to the gate of the short-circuit transistor provided on the () side, and the output of the low address matching circuit is connected to this gate.

Referring to Fig. 10, the relationship between the low address coincidence detection circuit 48 and the short circuit transistor will be described next.

FIG. 10 shows only one column by enlarging a pair of bit lines located at the top of FIG. The short circuit transistors 712, 723, 734, 713, 714, 724 are provided between the bit lines BL ₁ to BL ₄ , and the short circuit transistors 812, 823, 834, 813, 814, 824 are also provided with the bit lines ( To Is provided between). The gate of each short circuit transistor is connected to the low address coincidence detection circuit, but the gates of the short circuit transistors 712 and 812 are connected to the output of the row address matching detection circuit 912. The row address coincidence detection circuit 912 receives address signals A _{O1, ...} A _I1 corresponding to the first port and address signals A _{O2, ...} A _I2 corresponding to the second port. Inconsistency is determined. That is, when access is made to the same row from the first and second ports, the row address matching detection circuit 912 outputs the H level so that the bit lines BL ₁ , BL ₂ and the bit lines ( , ) Are respectively shorted, so that the write-in operation is suppressed as in the case of the two-port memory described above. If other bits are also shorted and a plurality of bit lines are accessed, the desired bit lines are all shorted.

In FIG. 9, the word lines of the first through fourth word lines WL1 through WL4 corresponding to the four ports are extended in the horizontal direction and the first fourth bit line pair corresponding to the four ports in the vertical direction. (BL ₁ , Four bit line pairs of BL4 and BL4 are extended. Each static memory cell is provided in an area surrounded by pairs of bit lines and word lines. In addition, four pairs of data bus line pairs DB1, ,… DB4, ) Are horizontally extended corresponding to the four ports.

A column select transistor is provided at an end portion of each bit line extending in the vertical direction. When this column is selected for read or write operations, the column select transistor is turned on to electrically close the data bus lines and bit lines that are normally electrically isolated.

Here, by selecting the static memory cells belonging to the second row (J in FIG. 9), the H level writing is performed from the third port in the above four-port memory.

In this case, the H level is the input terminal IN3 of the third gate. Is input to the input terminal IN3, while the L level is ) Is entered. The transistors (Tr ₁ ~Tr ₄₎ from Tr ₁ and Tr ₄ are turned off Tr ₂ and Tr ₃ are turned on. The bit line BL3 rises to H level while the bit line BL3 falls to L level. The column select signal Y3 goes to the H level so that the two column select transistors provided for the third bit line pair are turned on at the same time.

When the third word line WL3 becomes H level, the transistor is turned on, whereby the third bit line pair BL3, ) And the static memory cell J are electrically connected to each other.

In this case, another static memory cell to execute the read operation from the first port is in the same row (not shown in the right-extending direction of J) to which the static memory cell J belongs and another to execute the read operation from the second port. It is assumed that the static memory cell also exists therein. That is, it is assumed that the read operation is performed from the first and second ports among the four ports, and the write operation is performed from the third port to other memory cells in the same row.

Since the first and second word lines are turned on in the second row, the two transistors connecting the gates to these word lines are turned on at the same time. The static memory cell is thereby connected to the first, second and third bit line pairs. However, the write-in operation does not occur for the reason described later.

The row address input from the third port for the write operation and the row address input from the first and second ports for the read operation are respectively input to the low address match detection circuit, and if they match, the H level is output. The output H level signal is input to the gates of the short circuit transistors provided between the third bit line and the first and second bit lines, so that the bit line in the second row to which the static memory cell J for the write operation belongs is included. Are short-circuited.

In the second row to which the static memory cell J belongs, the problem of the L level in which the first, second and third bits are connected to each other and float in the first bit line may be solved.

Therefore, the so-called write-in where the information to be written is reversed can be eliminated.

In summary, it is important to have a means for shorting the bit lines corresponding to the write port and the read port when a plurality of ports selects static memory cells in the same row to ensure the effect of the present invention. Next, modifications belonging to this structure will be described. For example, when the read operation from the static memory cells in the target rows of the four ports is executed from the plurality of ports as described above, the third bit line participating in the write operation and the first and second participating in the read operation are performed. It is no longer necessary to short the bit lines and also connect one of the third bit line and the second bit lines participating in the write operation to obtain the effect of the present invention. However, in order to solve the problem of the L level floating of the bit lines, the write bit line should be shorted with the two read bit lines.

In this case, when there are a plurality of bit lines participating in a read operation, a selection circuit for a read bit line is needed to select only one of those bit lines and short it with the bit lines participating in the write operation. Therefore, even though it has significant advantages, it is not an ideal method because it unnecessarily complicates the circuit.

As a preferred embodiment of the multiport memory of the present invention, the two-port and four-port memories have been described so far, but various modifications and changes are possible. For example, those skilled in the art will understand that the number of ports is not limited to two or five and can be arbitrarily chosen.

In order to change the number of ports, a circuit change is necessary to enable the inputs as many as the number of ports for the low address matching circuit. For example, the low address coincidence detection circuits are provided by the number of combinations of all the pods.

That is, if the port number is 4, the inputs of the first and second ports, the first and third ports, the first and fourth ports, the second and third ports, the second and fourth ports, and the third and fourth ports As much as ₄ C ₂ (= 6) low address match detection circuit is required. In the case of a short-circuit transistor connecting bit lines of each column, according to the above description, between the first and second bit lines, between the first and third bit lines, between the first and fourth bit lines, and between the second and second bits. As many as ₄ C ₂ (= 6) short-circuit transistors are provided between the three bit lines, between the second and fourth bit lines, and between the third and fourth bit lines, whereby the outputs can be connected to the gates. In general, if n is a freely chosen integer, then n pairs of bit lines and n word lines are arranged corresponding to individual static memory cells in the n-port memory and also between two bit lines within each pair of n bit line pairs. A short circuit transistor is connected between the n bit lines of the pair. Therefore, a total of nC ₂ short circuit transistors are needed. It is also sufficient to input the outputs of the nC ₂ low address match detection circuit to the gates of the nC ₂ short circuit transistors one-to-one.

In addition, the short-circuit switch used for shorting the bit lines does not always need to be formed of a MOS transistor, and the gate insulating film of the transistor may be formed of an insulating film other than an oxide film, for example, a nitride film or another MIS transistor formed of an oxynitride film. have.

If necessary, the MOS transistor can also be replaced with a bipolar transistor. In addition, each port need not always have a structure to allow write and read operations.

Some ports may have the ability to operate only as read-only ports without input gates. However, at least one port must be a write port because the effect of the present invention is apparent to eliminate the write-in operation.

According to the present invention, when the same row is selected from a plurality of ports, one bit line of the bit line pair of the port in the same column and one bit line of the bit line pair of the other port are shorted and also a bit line pair of any port. The level of one bit line and the other bit lines of the opposite port from the port on which the write operation is performed is set at the same level as the level for the write operation because of the structure in which the other bit lines of the bit line pairs of the other port and the other port are also shorted. Since a write operation can be executed from one port and a stable write operation can be ensured even when the same row is selected from a plurality of accessing ports.

Claims (33)

Static memory cells, a plurality of ports provided for writing or reading data to or from the static memory cells, a plurality of bit lines and a plurality of word lines corresponding to the plurality of ports; Switches for electrically connecting the bit lines corresponding to the word lines of the same port to the static memory cells according to the levels of the word lines, and when the same row is selected by the corresponding ports. And short circuits for shorting between bit lines of each column of corresponding ports. The multiport memory according to claim 1, wherein the short circuits are switches formed of MIS transistors. The multiport memory of claim 2, wherein the switches connected to the same cell are formed in substantially the same size. 2. The multiport memory of claim 1 wherein the short circuits short between the bit lines of each column of corresponding ports. Static memory cells, a plurality of ports provided for writing or reading data to or from the static memory cells, a plurality of bit lines and a plurality of word lines corresponding to the plurality of ports; Switches that electrically connect the bit lines corresponding to the word lines of the same port to the static memory cells according to the levels of the word lines, and the same row from a plurality of ports for a write or read operation. Bit lines corresponding to a port selected for a write operation, other arbitrary bit lines selected, and other arbitrary bit lines selected from among bit lines corresponding to the plurality of selected ports when a plurality of word lines belonging to Short circuits for shorting the circuit boards, wherein the short circuits include row addresses to be input to respective ports. A low address matching circuit for outputting a signal when the low addresses of a plurality of ports match with each other, a bit line of each column of the corresponding ports connected to the low detection circuit and the low bit line and received in the output signal And a short circuit switch for shorting them out. 6. The multiport memory according to claim 5, wherein the short circuit switch is formed of a MIS transistor. 7. The multiport memory according to claim 6, wherein said short circuits connected to the same cell among said cells are formed in substantially the same size. 6. The multiport memory of claim 5, wherein the short circuits short circuit between bit lines corresponding to the ports selected for the write operation and all other bit lines among the bit lines corresponding to the plurality of selected ports. . 6. The multiport memory of claim 5, wherein the short circuit switch is provided at an end portion of each bit line positioned outside the cell region including the plurality of static memories. 6. The multiport memory according to claim 5, wherein the short circuit switch is formed of a MIS transistor. 11. The multiport memory of claim 10 wherein the interconductance Gm of the MIS transistors forming the short circuit switch is about the same as that of the MIS transistors forming the switches. Static memory cells, first and second ports provided for writing or reading data to or from the static memory cells, first and second ports corresponding to the first and second ports, and having levels. The static lines corresponding to the second bit lines and the first and second word lines, and the bit lines corresponding to the first and second word lines of the same port according to the levels of the first and second word lines. Switches electrically connected to memory cells, and a short circuit shorting between bit lines of each column of the first and second corresponding ports when the same row is selected by the first and second ports. Multiport memory characterized by including the. 13. The multiport memory of claim 12, wherein the short circuit is formed of a MIS transistor. 14. The multiport memory of claim 13 wherein the switches in the cells that are connected to the same cell are formed about the same size. The multiport memory of claim 12, wherein the short circuits are provided at an end portion of each bit line positioned outside a cell region including the plurality of static memories. 13. The multiport memory according to claim 12, wherein the short circuit switch is formed of the short circuit MIS transistor. 17. The multiport memory according to claim 16, wherein the interconductance Gm of the MIS type transistors forming the short circuit switch is larger than that of the MIS type transistors forming the switches. Static memory cells, first and second ports provided for writing or reading data to or from the static memory cells, first and second ports corresponding to the first and second ports, and having levels. And the bit lines corresponding to the first and second word lines of the same port according to the second lines, the first and second word lines, and the cells of the first and second word lines. Electrical connection to the field. Short circuits for shorting between bit lines of respective columns of corresponding ports when the same row is selected by the complementary shifts, wherein the short circuits compare a plurality of row addresses to be input to the respective ports. A row address matching detection circuit that outputs a signal when the low addresses of the ports of the port match with each other; and an output signal from the low address matching detection circuit connected to the detection circuit and the low bit lines to receive a signal from each column of the corresponding ports. And a short circuit switch for shorting corresponding bit lines of the multiport memory. 19. The multiport memory of claim 18, wherein the short circuit switch is formed of a MIS transistor. 10. The multiport memory of claim 8 wherein the switches in the cells that are connected to the same cell are formed about the same size. 21. The multiport memory of claim 20, wherein the short circuit switch is provided at an end portion of each bit line positioned outside of a cell region including the plurality of static memories. 22. The multiport memory of claim 21, wherein the short circuit switch is formed of a MIS transistor. 23. The multiport memory of claim 22 wherein the interconductance Gm of the MIS transistors forming the short circuit switch is greater than that of the MIS transistors forming the switches. First and second ports provided for writing or reading data to or from static memory cells, the static memocells, and first and second levels corresponding to the first and second ports. The static lines corresponding to the second bit lines, the first and second word lines, and the bit lines corresponding to the first and second word lines of the same port according to the levels of the first and second word lines. Bit lines corresponding to the ports selected for the write operation and the first and second switches when the switches electrically connected to the memory cells and the first and second word lie belonging to the same row are selected for the write or read operation. A short circuit for shorting other selected bit lines among the second bit lines, and a row of a plurality of ports including those selected for writing by comparing the low addresses input to the respective ports with each other; A low address matching circuit for outputting a signal when the addresses match, first and second cell regions formed by dividing the word lines in the cell region into almost two regions, and the first and second regions; A right row decoder provided corresponding to the right port between cell areas, and a left row decoder provided corresponding to the left port between the first and second cell areas, and the short circuit corresponds to the row address matching. And shorting other bit lines among bit lines corresponding to ports selected for a write operation and bit lines corresponding to related ports by receiving an output of the detection circuit. 25. The multiport memory of claim 24, wherein the switch is formed of a MIS transistor. 25. The multiport memory of claim 24 wherein said switches corresponding to the same port of said switches are formed approximately the same size. 27. The method of claim 26, further comprising: a data bus line provided corresponding to each port, a column select transistor for forming an electrical connection of bit lines corresponding to the same port, and maintaining the bit line at a predetermined voltage. And a second load circuit for maintaining the data bus line at a predetermined voltage. 27. The multiport memory of claim 26, wherein the short circuit is provided at an end portion of each bit line positioned outside of a cell region including the plurality of static memories. 27. The multiport memory of claim 26, wherein the short circuit switch is formed of a MIS transistor. 30. The multiport memory of claim 29 wherein the interconductance Gm of the MIS transistors forming the short circuit switch is greater than the MIS transistors forming the switches. 2. The method of claim 1, further comprising: a data bus line provided corresponding to each port, a column select transistor for forming electrical connections between bit lines corresponding to the same port, and the bit line at a predetermined voltage. And a second load circuit for maintaining the data bus line at a predetermined voltage. Static memory cells arranged in an array of rows and columns and having at least two separate bit lines corresponding to at least two ports providing cell addresses, the cell addresses being matched by being coupled to the individual bit lines to receive the cell addresses. And a short circuit for shorting between bit lines of corresponding columns. 32. The circuit of claim 31, wherein the short circuit comprises a low address matching circuit adapted to receive the cell addresses, and a short circuit transistor coupled to the row address matching circuit between one of the two bit lines and the other. Multi-port memory characterized by.