KR960000163B1 - Multiplexing method of input group module - Google Patents

Abstract

The method is for multiplexing the input group module to connect with a mixed interconnection network. The method comprises steps; (A)multiplexing input cell by the specific bit units and completing input cell multiplexing; and (B)multiplexing the next input cell with the same method of the step (A).

Description

Multiplexing Method of Input Group Modules for Hybrid Interconnection Networks

1 is a conceptual diagram of interconnection of a hybrid interconnection network to which the present invention is applied.

2 is a schematic diagram showing a configuration of a hybrid interconnection network to which the present invention is applied.

3 is a schematic diagram showing a configuration of an interconnect input device to which the present invention is applied.

4 is a schematic diagram of an input / output group connection network of a hybrid interconnection network to which the present invention is applied.

5 is a schematic diagram showing a configuration of an interconnection input device of a hybrid interconnection network to which the present invention is applied.

6 is a configuration diagram of an embodiment of an input group multiplexing module of an interconnection input device in which time division and space division are applied according to the present invention.

FIG. 7 is a flowchart illustrating an embodiment multiplexing method of an input input multiplexing module of a time zone and a space division according to the present invention.

8 is a flowchart for explaining another embodiment of a multiplexing method of an input input multiplexing module according to the present invention in which time division and space division are mixed.

9 is a diagram showing the outputs of the schemes of FIGS. 7 and 8 of an interconnection input device input group multiplexing module incorporating time division and space division according to the present invention.

* Explanation of symbols for main parts of the drawings

1: HIF complete nonblocking interconnection network 200: interconnection input device

300: I / O group network 400: interconnection output device

51 to 5G: input group multiplexing module 61 to 6G: input group connection medium

71 to 7K: Output group distribution module 81 to 8r: Input buffer

90: group multiplexer

The present invention relates to a nonblocking interconnection used for switching between a plurality of inputs and outputs. In particular, the present invention relates to a multiplexing method of an input group module for a hybrid interconnection network in which time division and space division are mixed. It is about.

Although there are a number of methods conventionally used to provide nonblocking interconnection between multiple inputs and multiple outputs, the complexity of the connection for interconnection between input and output, high hardware requirements, Or the complexity of control algorithms for interconnection or the like.

Now, looking more closely at the general technical field of the present invention, the means for providing an interconnect or connection between the inputs and outputs switch, the interconnection network, the interconnect fabric Or simply network. In addition, the structure, operation and actual implementation means of the means is various. However, their objectives together provide a connection between inputs and outputs, collectively referred to herein as interconnect networks.

Conflicts between inputs that occur when multiple (or more) inputs are simultaneously connected to one output are called output contentions. In addition, despite the assumption that there is no output contention between the inputs, a path conflict between inputs generated in the network due to lack of connection capacity of the interconnection network is referred to as internal conflict or internal blocking. In general, a nonblocking interconnection network is defined as an interconnection network in which there is no internal contention in the network under the assumption that there is no output contention. The non-blocking interconnection network again has sufficient paths between input and output to avoid blocking due to the change of the consensus Strict-Sense Nonblocking network and the input which does not block in any case unless there is an output contention. It is divided into a wide-sense nonblocking network (or called a rearranging network) for which the connection of devices in the network needs to be rearranged.

As described above, this nonblocking excludes the case of an output contention in which a plurality of inputs are simultaneously connected to one output. In contrast, when there is an output contention, an interconnection network capable of connecting the plurality of inputs to an output without internal collision is defined as a completely nonblocking interconnection network. The full nonblocking interconnection network can provide all connections even if multiple inputs are desired to be simultaneously connected to one output at the input side by various methods such as time division or space division.

The method of providing nonblocking or full nonblocking interconnection between inputs and outputs is largely time-division (TD) and multiplexed into shared medium. On the other hand, each output side accepts the input corresponding to the output among the inputs in the public media by the appropriate method. Public media used for such time-division access include memory devices, buses, and the like.

However, time division and interconnection by means of a common medium have a practical implementation limitation as the number of input lines and output lines increases, i.e., as the network size increases. In other words, in order for a large number of inputs to use one joint medium by time division, the speed of time-division multiplexing should be increased by that much, and in practice, the maximum speed of time division multiplexing or access to the joint medium is required. This is because there is an implementation limitation in the maximum speed of.

Thus, interconnects that rely solely on pure time division multiplexing have limitations on the number of inputs and outputs, making them unsuitable for large nonblocking interconnects.

On the other hand, the spatial division interconnection has a separate connection path between each input and output by a connection medium such as a connection line or a bus, and is limited by the operating speed limitation and the common media access speed as in time division multiplexing. There is no implementation limitation. However, a large number of connection media are required to provide a separate connection media for every possible pair of input and output. In other words, when the number of inputs and the number of outputs are N, respectively, the number of connecting lines is represented as a function of N ^2. As N increases, the number of connecting lines increases rapidly, making it difficult to implement.

A multi-stage interconnection network, which is a relocation network by small switch elements, can be considered as an approach using space division to solve the disadvantages and limitations of the existing interconnection methods. The relocation network can provide various connection states by rearranging the connection state of the switch elements in the network, thereby increasing the utilization efficiency of the hardware of the network compared to the non-blocking network. Therefore, the hardware requirement for establishing an interconnection network having the same connection capability is low. However, as the size of the network increases, the time required to perform an algorithm for relocating the connection state of the devices is long, and the number of connection lines for delivering the result to each of the numerous devices explodes. As a result, the advantage of reducing hardware requirements is overshadowed by the following reasons. That is, the time is limited by the time limit of the algorithm execution time as the network grows and the space limit by the number of connection lines required to transfer the control.

In addition, to solve this problem, each element of the network may be designed by self-routing. However, the increase in the amount of hardware required and the complexity of the design cannot be overlooked. Moreover, the above-mentioned problems become more serious in order to obtain a complete nonblocking network rather than a simple nonblocking network.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and the like, and has a simple structure and is an input for a hybrid interconnection network, which is a complete non-blocking interconnection network which is a simple non-blocking interconnection network that provides easy interconnection and provides effective interconnection. Its purpose is to provide a multiplexing method for group modules.

In order to achieve the above object, the present invention is directed to a multiplexing method of an input group module for a hybrid interconnection network mixed with time division and space division for a nonblocking interconnect utilized for switching between a plurality of inputs and outputs. The method may include: performing a first cycle of multiplexing bits of a predetermined size for each cell of each input to complete cell multiplexing of an initial input; And performing at least one next cycle for performing cell multiplexing on a next input in the same process as the first cycle, and performing one cell (c bit) of each input. Performing a first cycle by multiplexing sequentially by one minicell (p bits) to perform a cyclic process in units of minicells; And at least one subsequent cycle performing the same cycle as the first cycle until the multiplexing of one cell at each input is completed. By providing a multiplexing method of an input group module for an access network, a simple structure allows easy implementation and effective interconnection.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 is a conceptual diagram of interconnection of a hybrid interconnection network to which the present invention is applied, and illustrates the basic interconnection concept of the present invention. In the figure, the total number of inputs is _denoted by N _i , and the total number of outputs is denoted by N _o .

As shown in FIG. 1, in an interconnection network to which the present invention is applied, inputs are divided into a plurality of input groups. That is, by dividing the inputs into G input groups each having r inputs, the total number of inputs is represented by the following equation.

[Equation 1]

N _i = r * G

The outputs are also divided into k output groups, each with s outputs. Therefore, the total number of outputs is represented by the following equation.

[Equation 2]

N _o = s * K

Its main concept is to group multiple inputs and outputs into input groups and output groups, and then provide connections between input groups and output groups without providing separate connections between each input and output. This greatly reduces the complexity of the connection required for the interconnection between the input and output, and facilitates the actual implementation thereof.

In the interconnection network to which the present invention is applied, since each input group drawer provides connection between all inputs and all outputs with only connections between output groups, each input group has only one output and the output is connected to the next interconnection network. Connected. Therefore, in each input group, all inputs in the input group are output to one output medium by multiplexing. The interconnection between input groups and output groups uses spatial partitioning. That is, each input group has one output and its output is connected to one connection medium, and each output group has one connection for each connection medium from all the input groups, so that all input groups and output groups The connection is made. Within an output group, only those inputs from the connection medium of each input group that are desired to be connected to the corresponding output group are filtered out and then interconnected to the final incoming output in the output group. Thus, the interconnection method of the present invention achieves effective interconnection by mixing time division and space division.

2 is a schematic diagram of a HIF full nonblocking interconnection network according to the present invention, where 1 is a HIF full nonblocking interconnection network, 200 is an interconnect input device, 300 is an input / output group network, and 400 is an interconnect output device. Respectively.

The interconnection input device 200 divides the inputs into a plurality of input groups, and within each input group, one input group connection medium (4) for each group in the input / output group connection network 300, which is the next stage, by time division multiplexing. 61, 62, ... 6G of FIG. 6), and the input / output group connection network 300 interconnects each of the input groups and the output groups by space division, and each of the interconnection output devices 400 Selective filtration to the output group and interconnection to each incoming output in the output group are performed.

3 schematically shows the configuration of an interconnect input device to which the present invention is applied and is a detailed view of the interconnect input device 200. In the figure, 51 to 5G respectively show input group multiplexing modules.

As shown in FIG. 6, the input group multiplexing modules 51 to 5G are composed of r input buffers 81 to 8r and one group multiplexer (MUX) 90 to multiplex r inputs.

The inputs are divided into G input groups with r inputs for each group, and the inputs of each input group are input to the corresponding input group multiplexing module. In each input group multiplexing module 51 to 5G, the inputs within the group are output to one output line ci-1 to ci-G by time division multiplexing, and are connected to the next input / output group connection network 300. The number r of inputs per group and the number G of groups are values determined by any suitable value.

FIG. 4 schematically illustrates the configuration of an input / output group connection network 300 of a hybrid interconnection network to which the present invention is applied. In the drawings, 61 to 6G respectively represent input group connection media.

As shown in the figure, one input group connecting medium 61 to 6G connected to each input group multiplexing module 51 to 5G of the interconnection input device 200 has one connection to all output groups, respectively. Has a structure. As the input group connection medium 61 to 6G, a simple bus type connection line or an optical fiber may be used. Outputs from each of the input group multiplexing modules 51 to 5G are broadcasted to the corresponding input group connecting media 61 to 6G to be connected to all output groups.

5 is a schematic diagram showing the configuration of the interconnection output device 400 of the hybrid interconnection network to which the present invention is applied. In the drawings, 71 to 7K show output group distribution modules, respectively.

Here, the outputs are grouped into a plurality of output groups, and there are one output group distribution module 71 to 7K per output group. Each output group distribution module 71 to 7K has one connection from each of the input group connection media 61 to 6G connected one to each of the input groups, and consists of a destination address filter and an interconnection network.

The destination address filter corresponding to the input unit of the output group distribution module 71 to 7K is composed of destination address filters connected to each input group connection medium 61 to 6g, and the destination output is the output group among the inputs broadcasted. Select and filter only those belonging to. The destination address filter consists of a buffer (or register) for temporarily storing the destination address of the input and a logic gate such as a comparator to compare the destination address with the unique destination address of the output group distribution module. If the destination address of the comparison result matches the unique address of the output group, it is passed. For example, if the destination addresses of the outputs are arranged in size order and the number of outputs in each output group is 32 (2 ⁵ ), then the input is compared to the upper bits except the least significant 5 bits in the binary notation of the destination address. You can check whether the destination address belongs to the group. That is, the upper bits except the lower 5 bits become the unique address of the output group.

The inputs passing through the destination address filter are interconnected to the destination output by the interconnection network in the output group distribution modules 71 to 7K. Since the destination addresses of the inputs input through the destination address filtering unit belong to the output group, interconnection to the final destination is possible only if there is an interconnection network of the input / output size of the output group distribution module (71 to 7K). The interconnection network in the distribution modules 71 to 7K may be used in the present invention with any kind of interconnection network, such as a switch, an interconnection network, an interconnect fabric, or simply a network.

FIG. 6 is a diagram illustrating an embodiment of an interconnection input device input group multiplexing module 51 to 5G mixed with time division and space division to which the present invention is applied. In the drawing, 81 to 8r are input buffers, and 90 is a group multiplexer. Respectively.

This is for explaining the structure of an embodiment of the input group multiplexing module in detail, and shows an example of the input group multiplexing module 51 of the input group 1 when one input group includes r inputs. The configuration of the group multiplexing modules 51 to 5G is the same. The inputs 1, 2,... Let's call it input r.

Each of the above inputs has one input buffer 81 to 8r, as shown in the drawing, so that the input data (called packets or cells, hereinafter simply referred to as "cells") is serial. Alternatively, it is input in a parallel bit flow and is temporarily stored in the input buffers 81 to 8r. In this case, when the lengths of the input buffers 81 to 8r are larger than 1, the temporarily stored cells are sequentially output by FIFO (First In First Out) method, and group multiplexers are paralleled by p bits. Multiplexed by < RTI ID = 0.0 > 90, < / RTI > and its p bit units are referred to as minicells. That is, when the length of one cell is c bits, in order to complete the multiplexing of one cell, multiplexing of c / p minicells should be performed. Herein, the length of the minicell, that is, the value of p may be determined as an arbitrary value from the minimum 1 bit to the maximum cell length.

Now, the multiplexing method of the present invention applied to the interconnection input device input group multiplexing modules 51 to 5G in which the time division and the space division are mixed will be described in detail.

FIG. 7 is a flowchart illustrating an embodiment of a multiplexing method of an input input multiplexing module 51 to 5G in which time division and space division are mixed according to the present invention, and FIG. 8 is a time division scheme according to the present invention. Another embodiment of the interconnection input device input group multiplexing modules 51 to 5G in which spatial division is mixed is a flowchart for explaining the multiplexing method. 9 is a view for explaining the operation of the method of FIG. 7 and FIG. 8 of the input input multiplexing module 51 to 5G mixed with time division and space division according to the present invention. Shows the output of the input group multiplexing modules 51 to 5G. In the figure, c denotes the length of the cell, p denotes the length of the minicell, r denotes the number of inputs in the group, and i-j denotes the j-th minicell of the input i cell.

As a multiplexing method in the input group multiplexing modules 51 to 5G, various methods can be considered. When two representative methods are described, first, the method shown in FIG. FIG. 7 illustrates an embodiment of performing multiplexing in the input group multiplexing modules 51 to 5G of FIG. 6, which is a p-bit multiplexing operation for an output cell of a FIFO buffer of one input at a time. After one cell of the input is all multiplexed, the multiplexing of the cell of the next input is started.

As shown in the figure, input 1, input 2,... In the order of input r, the cells are multiplexed one by one (71, 72, 73). The multiplexing of one cell at each input is completed by the multiplexing of c / p minicells by p bits. In this approach, the delay caused by multiplexing of cells is approximated when we think that all inputs are serialized, that is, when one bit of input is completed when c bits are in series. It becomes about 1 cell (c bits).

On the other hand, as shown in FIG. 8, one minicell (p bit) of each input is input 1, input 2,... In this case, there is a method of multiplexing in order of input r, and performing this rotation (cycle or cycle) of c / p / times until the multiplexing of one cell (c bit) is completed on each input. In this method, multiplexing can be started whenever the input of the p bits of each input cell is completed. Therefore, the delay caused by the multiplexing is approximately p bits, which can reduce the delay compared to the former method. As such, although the complexity is required in the cell reception at the interconnection output terminal 400, the multiplexed delay can be reduced to about p / c of the multiplexed delay by the former method.

Thus, a hybrid interconnection network that combines time division and space division does not provide separate connections between inputs and outputs, but groups inputs and outputs individually to provide connections between input groups and output 7 groups. The complexity of the interconnections and the amount of hardware required can be greatly reduced. In addition, when the operation speed of the network becomes too high due to time division multiplexing of the interconnection input device 200, the operation speed of the network can be reduced by parallelizing the bit flow between the inputs and the outputs. Even in this case, the implementation of one large network is difficult, but it is easy to implement a small size of the network in parallel has an implementation advantage, especially in the implementation of a large capacity interconnection network. In addition, since each output group distribution module in the interconnect output device 400 can be composed of modules of a small interconnection network again in the output group interconnection, consequently a large interconnection network by small interconnection network modules. There is an advantage that can be configured.

In addition, the present invention provides a multiplexing method of an input group module for a hybrid interconnection network performed as described above, thereby performing a function of an input unit of a hybrid interconnection network in which time division and space division having the above advantages are performed. An interconnect network module has the effect of enabling a large capacity access network to be implemented.

Claims (2)

A multiplexing method of an input group module for a hybrid interconnection network in which time and space division is mixed, for nonblocking interconnects utilized for switching between multiple inputs and outputs, the method of multiplexing the cells of each input at a time. Performing a first cycle of performing multiplexing by bits P of a predetermined size to complete cell multiplexing of an initial input; And performing at least one next cycle (Cycle) for performing cell multiplexing on a next input in the same process as the first cycle (Cycle). Multiplexing method of input group module. A multiplexing method of an input group module for a hybrid interconnection network in which time division and space division are mixed for a nonblocking interconnect utilized for switching between a plurality of inputs and outputs, one cell of each input (c) Performing a first cycle of performing multiplexing on a minicell basis by sequentially multiplexing by one minicell (pbit) of each bit; And performing at least one next cycle (Cycle) performing the same process as the first cycle until the multiplexing of one cell at each input is completed. Multiplexing method of input group module for hybrid interconnection network.