KR950011289B1 - Muftipont d ram - Google Patents

Abstract

The device improves the signal transmission efficiency in the color video printer. The device includes ; the column SAM(A) which has the serial data selector(15), the column serial input/output signal buffer(14), the column data register(16) which selects the column serial input/output signals(CSI/00-CSI/03) and row address pointer(13a) output signal, the serial data selector(15), and ; the row SAM(B) which has the row serial input/output buffer(17), the row data register(19), the memory array(6), and the serial data selector(18), ; row address pointer(13a), column address pointer(13b), and the control timing unit(12).

Description

Multiport D Ram with Matrix Direction Data Processing

1 is a block diagram of a conventional multi-port dynamic RAM.

2 is a flow chart for explaining the operation of the conventional multi-port dynamic RAM.

3 is a block diagram of a multi-port dynamic RAM according to the present invention.

4 is a flow chart for explaining the operation of the multi-port dynamic RAM according to the present invention.

* Explanation of symbols for main parts of the drawings

A: column SAM i: row SAM

1: Predecoder 2: Column Decoder

3: row decoder 5: column input / output port

6: Memory Array 9: I / O Buffer

12: control timing section 13a: row address pointer

13b: Column Earth Pointer 14: Column Serial I / O Buffer

15 serial data selector 16 column data register

17: column data register 18: serial data selector

19: low data register

The present invention relates to a multiport dynamic RAM, and in particular, to store stored data in two directions, a column and a row.

In the conventional multi-port dynamic RAM configuration, as shown in FIG. 1, the predecoder 1 decodes the address signals A0-A7 into a desired signal, and the decoded signal from the predecoder 1 is input to the column. The memory array 6 inputs and outputs a column decoder 2 for decoding into a signal, a row decoder 3 for decoding into a low signal, an address pointer 4 for storing an address signal, and an output of the column decoder 2. Serial data selector for selecting serial input / output port 5 to be output to buffer 9 and output of address pointer 4 of memory array 6 forming an array of 256 rows and 256 * 4 bits as serial data. (7), a data register (8) for transmitting and receiving 256 rows of 4-bit data, an input / output buffer (9) for transferring the output of the column input / output port (5), and the operation of the memory array (6). Control timing section 10, address pointer 4, and data for controlling the Has been selected by the output of the register (8) configured as a serial input, an output buffer 11 for input to the serial input and output buffer 11.

The operation of the conventional multi-port dynamic RAM configured as described above can be classified into three types.

First, the operation of the RAM is to read and write by specifying a row address and a column address for each memory cell.

Second, the fast page mode operation recognizes the row address at the falling edge of the control signal RAS and decodes one row of data at high speed while changing the column address while the control signal RAS is in the low state. And recording, in which case no other operation is performed.

Third, the serial access memory (hereinafter referred to as Sam) operation is a transfer operation and memory array 6 transfers data of one row of data (256 * 4 bits) to data register 8 as shown in FIG. Or the data of the data register 8 is transmitted in the column of the designated address, and the serial transfer operation is performed by serially inputting and outputting the data of the data register 8 through the serial input / output buffer 11. The data is outputted to or outputted from the SE and the clock signal SC sequentially in the data register 8. In this case, high-speed data input and output are possible regardless of other control signals. .

However, in the conventional multi-port dynamic RAM, the transmission and serial input / output operations are performed only for 256 * 4 bit data, which is one row of data, so the operation of storing and decoding data in the memory array 6 is performed in the row direction. It is possible to process at high speed, but it is impossible to process at high speed in the column direction. Especially, in order to process pre-stored data in the column direction, the right angle memory cell has to be decoded by the RAM operation method. There was a problem.

The present invention has been made to solve the problems of the prior art, which includes a low SAM, a column serial input, a low serial input, an output buffer, a serial data selector, and a 256 * 4 bit low data register in a reference multi-port dynamic RAM. Its purpose is to complement the functions of the column SAM, which consists of an output buffer, a serial data selector, and a 256 * 4 bit column data register, a row, a color address pointer, and a control timing section to enable high-speed data processing in the matrix direction.

Hereinafter, the present invention will be described in detail by the accompanying drawings.

3 is a block diagram of a multi-port dynamic RAM according to the present invention, which includes a predecoder 1 for decoding an address signal A0-A7 into a desired signal, and a signal decoded by the predecoder 1. A column decoder 2 that receives and decodes by a column depth, a row decoder 3 that decodes a low signal, and a column input that outputs the output of the column decoder 2 to the memory array 6 and the input / output buffer 9. An output port 5, a memory array 6 forming an array of 256 rows and 256 * 4 bits, an input / output buffer 9 for transferring the output of the column input and output ports 5, and a memory In a multi-port dynamic RAM provided with a control timing section for controlling the operation of the array 6, a column serial for buffering column serial input and output signals (CSI / OΦ-CSI03) to perform data transfer with the serial data selector 15. I / O buffer 14, column serial I / O signal (CSI / OΦ-CSI / 03) Selects the output signal of the right address pointer 13a, the column data register 16, the serial data register 16 for performing data transfer, the serial data selector 15 for performing data transfer, and 256 columns of 4-bit data. A column SAM composed of the color data registers 16 to transmit and receive to and from (6) is provided, and buffers the row serial input and output signals (RSI / OΦ-RSI / 03) to transfer data to the serial data selector 18. Selects the row serial input and output buffer 17, the row serial input and output signal (RSI / OΦ-RSI / 03) and the column address pointer 13b output signal to perform the data transfer with the row data register 19. A row SAM (I) composed of a serial data selector 18 to execute and a row data register 19 for transmitting and receiving 256 rows * 4 bits of data to and from the memory array 6, and an address output from the predecoder 1; Each signal (AΦ-A7) Determine whether the row address pointer 13a, column address pointer 13b, which are stored as row and column data and output to the serial data selectors 15 and 18, and whether the data transfer operation is performed by one column or one row. And a control timing unit 12 for controlling the timing so as to control the timing.

Thus described with reference to Figure 4 the effect of the present invention left as follows.

First, in the present invention, the operation of the multi-port dynamic RAM (RAM, FAST PAGE MODE, SAM) is operated by dividing the SAM operation into rows and columns, while maintaining the operation of the existing multi-port dynamic RAM.

The SAM transmission operation during the SAM operation is to transmit data of one row or one column according to the row enable / column enable signal RE / CE from the control timing unit 12. Determining whether or not to transfer data, each of the row data registers 19 and the column data registers 16 has a row serial enable signal RSE from the control timing unit 12 and a column serial enable signal CSE. The high speed serial input and output signals can be transmitted by the timing of the low serial clock signal RSC and the column serial clock signal CSC.

That is, as shown in FIG. 4, only the signal transmission operation is performed by independent timing, and data (256 * 4 bits) is input and output at the same time at high speed by one column or one row.

As described above, in the configuration of the multi-port dynamic RAM, the present invention can transmit one row of data and one row of data at a high speed simultaneously, so that the storage and reproduction using the memory can be transmitted at high speed in image signal processing such as a color video printer. Because of the number, the storage and reproduction using the memory can be performed at high speed in the image signal processing such as a color video printer, so that the efficiency in signal transmission can be improved.

Claims (1)

Column serial input and output buffer 14, which buffers the column serial input and output signals (CSI / OΦ-CSI03) and transmits data with the serial data selector 15, and column serial input and output signals (CSI / OΦ-CSI). / 03) and a serial data selector 15 for selecting the output signal of the row address pointer 13a to perform data transfer with the column data register 16, and a color for transmitting and receiving 256 columns of 4-bit data to and from the memory array 6; A row SAM comprising a data register 16 and a row serial input and output for buffering a row serial input and output signal (RSI / OΦ-RSI / 03) to perform data transfer with the serial data selector 18. Serial data selector 18 which selects a buffer 17, a row serial input and output signal (RSI / OΦ-RSI / 03) and a column address pointer 13b output signal to perform data transfer with the row data register 19 And transmit and receive 256 rows * 4 bits of data to and from the memory array 6 A row SAM (I) composed of row data registers 19, and storing the address signals AΦ-A7 output from the predecoder 1 as row and column data, respectively. Row address pointer 13a, column address pointer 13b, and control timing section 12 for controlling timing to determine whether the data transfer operation is performed by one column or one row. Multi-port dynamic RAM capable of processing matrix direction data.