KR950010928B1 - Differential biphase-shift keying demodulator and method thereof - Google Patents

Abstract

The multipliers are eliminated in the DBPSS decoder so that it provides simple logic structure and high operating speed. The decoder includes a phase detector for detecting phases of input signals through I and Q channels, a delayer for delaying phase by one sampling time, a subtracter for calculating phase difference between two consecutive signals, an absolute value detector for calculating absolute value of the phase difference, and a decoder for decoding input data in reference of the phase difference.

Description

Differential two-phase shift keying demodulator and demodulation method

1 is a block diagram of a typical transmitter for performing DBPSK modulation in a spread spectrum communication system.

2 is a block diagram of an asynchronous receiver using a general DMF performing DBPSK demodulation in a spread spectrum communication system.

3 is a block diagram of a general digital matching filter.

4 is a block diagram of a conventional DBPSK demodulator.

5 is a block diagram of a DBPSK demodulator according to the present invention.

6 is a state diagram of phase? (K) corresponding to I (K) and Q (K).

7 is a detailed configuration diagram of the phase detector 503 in the configuration of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver of differential bi phase-shift keying (hereinafter referred to as "DBPSK") in a digital communication system, and more particularly, to a DBPSK demodulator.

In general, a carrier band digital transmission is used to convert a digital signal into a signal having a given frequency band by modulation. Representative examples of the carrier-band digital transmission include ASK (Amplitude-Shift Keying) for converting the amplitude of the carrier to a digital signal, Fsk (Frequency-Shift Keying) for converting the frequency of the carrier to a digital signal, and digital phase to the carrier phase. PSK (Phase-Shift Keying) method to change by. In general, the present invention relates to a differential two-phase shift keying (DBPSK) method using many PSK methods among the three methods.

1 is a block diagram of a general transmitter for performing DBPSK modulation in a spread spectrum communication system.

The serial / parallel converter 102 receives data generated from the data source 101 and converts the data into parallel data. The DBPSK encoder 103 outputs the parallel-converted data to the inputs of the I and Q channels, respectively, of the differential encoding terms. The spreaders 107 and 108 receive the differentially encoded data and spread the spectrum by PN codes generated from the PN generator 106 to output the spread signals.

The spread spectrum data is filtered through the first and second LPEs 109 and 110, respectively, and the first mixer 112 is an I-channel mixer, and receives the spread spectrum data from the first LPE 109 and a carrier generator. In-Phase component generated from 111 is mixed with the carrier to output QPSK modulation. In addition, the second mixer 113 is a Q-channel mixer, which receives filtered spread data from the second LPE 110 and mixes with the carrier of the 90 degree phase shifted component generated from the carrier generator 111 to modulate the QPSK. Output

The combiner 115 receives the I, Q channel QPSK modulated outputs from the first and second mixers 112 and 113, respectively, and combines and outputs them. The BPF 120 performs band filtering on the DBPSK modulated signal input from the combiner 115, and the amplifier 130 amplifies the band filtered signal and outputs it through the antenna 140.

2 is a block diagram of an asynchronous receiver using a general DMF performing DBPSK demodulation in a spread spectrum communication system.

First, a low noise amplifier 202 (hereinafter referred to as LNA) amplifies and outputs a signal input through the reception antenna 201. The BPF 203 then filters and outputs the low noise amplified signal. The first mixer 205 receives an RF signal output from the RF frequency generator 204 and mixes the filtered signal and outputs the mixed signal. Thereafter, the second BPF 206 filters the mixed signal and outputs the mixed signal at an intermediate frequency.

2 is a block diagram of an asynchronous receiver using a general DMF performing DBPSK demodulation in a spread spectrum communication system.

First, a low noise amplifier 202 (hereinafter referred to as LIA) amplifies and outputs a signal input through the reception antenna 201. The BPF 203 then filters and outputs the low noise amplified signal. The first mixer 205 receives an RF signal output from the RF frequency generator 204 and mixes the filtered signal and outputs the mixed signal. Thereafter, the second BPF 206 filters the mixed signal and outputs the mixed signal at an intermediate frequency.

Here, if the carrier frequency is fc, the RF frequency is f _RF , and the intermediate frequency is f _IF , the carrier frequency generally constitutes a relationship of fc = f _RF + f _IF .

Each of the second mixer 209 and the third mixer 210 receives the output signal of the second BPF 206 and receives the intermediate frequency shifted from the intermediate frequency generator 211 by 90 degrees from the intermediate frequency generator 211, respectively. It is mixed with the signal and output as a band-spread signal with the intermediate frequency removed. In this case, the second mixer 209, which is an I-channel mixer, mixes in-phase components from the intermediate frequency generator 211, and the third mixer 210, which is a Q-channel mixer, mixes orthogonal components that have shifted the intermediate frequency by 90 degrees. do.

The output signals of the second and third mixers 209 and 210 are input to the first and second LPEs 213 and 214, respectively, and filtered. The first and second A / D converters 215 and 216 are respectively filtered. Receives and converts it into digital data and outputs it. At this time, the sampling frequency at the time of digital conversion is generally more than twice the spread signal band.

The first and second digital matching filters 217 and 218 receive the digitally converted signal, receive the PN code generated from the PN code generator 219 and correlate with the digitally converted signal to despread it. Output In this case, the despreading output has a very large correlation value observed when the digitally converted signal coincides with the PN code, and a very small correlation value is observed when it does not match.

3 is a block diagram of a general digital matching filter. Referring to FIG. 3, the operation of the digital matching filters 217 and 218 will be described in detail. First, the received input signal is transmitted through a shift register array 302. Referring to FIG. It is shifted every clock. In addition, the PN code input from the PN code generator 219 is stored in the reference PN code register 304. Thus, the output of the shift register array 302 and the output of the reference PN code register 304 are simultaneously multiplied by the first-n-th multipliers 305, 306, ..., 307 for each clock, and the result is an adder 308, respectively. ) And the added output is output to the outputs of the first and second digital match filters 217 and 218.

The first and second squarers 220 and 221 receive squares of output signals of the first and second digital matched filters 217 and 218, respectively. Thereafter, the adder 222 receives the squared outputs of the first and second squarers 220 and 221 at the same time, adds them, and outputs them. A square root circuit 223 receives the output of the adder 222 to calculate the square root. The output is then sent to the timing controller 224. At this time, the control unit 224 is mainly to detect the peak value and restore the data clock corresponding to the square root operation input. That is, the highest peak value of the output of the square root circuit 223 is detected during the baseband symbol duration and output to the DBPSK demodulator 229. Therefore, the DBPSK demodulator 229 receives the output signal of the timing controller 224 to sense and store the highest value among the outputs of the first and second digital match filters 217 and 218. In addition, the timing controller 224 reproduces and outputs a clock for the baseband data after symbol duration is completed, and controls the baseband data demodulation operation of the DBPSK demodulator 229.

When the output signal of the DMF 217 of the I channel selected for the Kth baseband data in the DBPSK demodulator 29 is I (K), and the output signal of the DMF 218 of the Q channel is Q (K), The I (K) and Q (K) are outputs of the first and second DMFs 217 and 218 when the highest peak value is detected by the controller 224 during the Kth symbol duration, respectively.

In addition, if the input to the DBPSK demodulator 229 is sin (K), I (K), Q (K) and sin (K) is represented by the following equation.

I (K) = A (K) cos (ø (K)) ... ..............(One)

Q (K) = A (K) sin (øK)) ... ............(2)

sin (K) = I (K) + jQ (K) ..................... ............... (3)

= A (K) e ^{iø: Kj} ... ...................(4)

ø (K) ø _mod (K) + ø _offset (K) + θ ... 6)

= arctan (Q (K) / I (K)) ..................... ............. (7)

In the above formula

Q _mod (K): Phase component by DBPSK modulation

Q _offset (K): Phase component by frequency offset of received signal and local generator

θ: Component due to initial phase difference between local signal generator and receiver

Therefore, the DBPSK demodulator 229 output Sout (K) is expressed as a phase difference between successive adjacent samples as shown in the following equation.

Sout (K) = sin (K) * sin (K-1) ........................ .......(8)

X (K) + jY (K) ..................... .......... (9)

X (K) = reall [Sout (K)] ... ......... (10)

Y (K) = Image [Sout (K)] ..................... ....... (11)

In addition, said 8, 10, 11 are represented as a following formula.

Sout (K) = A (K) A (K-1) e ^jøiKj e ^{-jø (K-1)} ......................... .... (12)

X (K) = A (K-1) cos (△ ø _mod (K)-△ ø _offset (K)) ................. (13)

Y (K) = A (K-1) sin (△ ø _mod (K)-△ ø _offset (K)) ..... (14)

△ ø _mod (K) = ø _mod (K) -ø _mod (K-1) ......................... (15)

Øø _offset (K) = ø _offset (K) -ø _offset (K-1) ........................ (16)

In the case of DBPSK modulation, phase shift Δø _mod (K) due to modulation is 0 ° or 180 °, and Δø _offset (K) is a nearly negligible factor, and the above equation (13) can be represented as follows.

X (K) = ± A (K) A (K-1) ... .............. (17)

Therefore, the final output of the DBPSK demodulator 229 is data demodulated in correspondence with the code of equation 17 above.

That is, X (K) If 0, DBPSK demodulator 229 demodulates data " 0 ".

Further, if X (K) <0, the DBPSK demodulator 229 demodulates data "1".

Hereinafter, the DBPSK demodulator 229 will be described in detail with reference to the configuration and operation of the DBPSK transceiver of the digital communication system.

4 is a block diagram of a conventional DBPSK demodulator, comprising: a first delayer (Delay: 403) for receiving an input I (K) of an I channel and outputting I (K-1) by delaying one sampling period; A first multiplier 405 that receives input I (K) of the I channel and an output I (K-1) of the first delayer 403 and multiplies and outputs the input, and inputs Q (K) of the Q channel. A second delay (Delay 404) for receiving Q (K-1) and delaying for one sampling period, and the input Q (K) of the Q channel and the output Q (K−) of the second delayer 404 A second multiplier 406 that receives 1) and multiplies and outputs the multiplier, an adder 409 that receives and outputs the outputs of the first and second multipliers 405 and 406, and the adder 409 And a data determiner 410 that receives the output and determines demodulation data.

The operation of the conventional DBPSK demodulator will be described below based on the configuration of FIG. 4 described above.

First, the first and second delayers 403 and 404 receive the input I (K) of the I channel and the input Q (K) of the Q channel, respectively, I (K-1) which is the input of the previous sampling period delayed by one sampling period. And Q (K-1).

The first multiplier 405 receives the delay output I (K-1) of the first delayer 403 and the input I (K) of the current sampling period, and multiplies and outputs the two input signals.

The second multiplier 406 receives the delay output Q (K-1) of the second delayer 404 and the input Q (K) of the current sampling period, and multiplies and outputs the two input signals.

The adder 409 receives the outputs of the first and second multipliers 405 and 406 and adds and outputs the two input signals. Thereafter, the data determiner 410 receives the addition output of the adder 409. If the sign of the add output is positive, the data determiner 410 determines and demodulates the data " 0 ", and if the sign of the add output is negative, the data " 1 " Determine and output the demodulation.

However, the above-described conventional DBPSK demodulator requires two multipliers 405 and 406 and two delayers 403 and 404 inside, which makes the configuration complicated. In particular, the multiplier is complicated by a large amount of logic gates. In addition, there is a problem in that the cost increases because the high speed multiplier required for performing the fast operation is required. In addition, since the input I (K) of the I channel and the input Q (K) of the Q channel are each represented by 8 bits or more, it is difficult to process the signals as a multiplier and a delay, and has a disadvantage in that power consumption is large. .

Accordingly, an object of the present invention is to provide a simple and easy to implement DBPSK demodulator by eliminating the logic implementation of the multiplier.

Another object of the present invention is to provide a DBPSK demodulation method with a simple logic implementation.

According to another object of the present invention described above, the present invention provides a phase detection step of detecting a phase of a DBPSK modulated signal by receiving an input I (K) and an input Q (K) of a Q channel, and the detected phase. And a phase difference calculation step of calculating a phase difference between two consecutive sampling periods from a detection phase before one sampling, an absolute value step of obtaining an absolute value of the phase difference, and demodulating data corresponding to a predetermined reference value from the absolute value. It consists of a data determination step.

5 is a block diagram of a DBPSK demodulator according to an embodiment of the present invention, comprising: a phase detector 503 for detecting a phase of a DBPSK modulated signal by receiving an input I (K) of an I channel and an input Q (K) of a Q channel; A delayer 504 that receives the detected phase from the phase detector 503 and outputs it after one sampling delay; and a phase of detection of the current sampling period from the phase detector 503 and previous sampling from the delayer 504 A subtractor (507) for receiving a phase detected between two sampling phases by subtracting the two detected phases and outputting a phase difference between two consecutive sampling periods, and receiving the phase difference value from the subtractor 507 An absolute value circuit (Absolutor) 508 for outputting the absolute value is output, and a data determiner 509 for receiving the output of the absolute value circuit 508, and determines and demodulates and outputs data in response to the input signal.

6 is a state diagram of phase K corresponding to I (K) and Q (K).

FIG. 7 is a detailed configuration diagram of the phase detector 503 in FIG. 5, which includes a second absolute value circuit 703 which receives an input I (K) of an I channel, and outputs the absolute value by outputting the absolute value. A comparator that receives the first absolute value circuit 704 that receives K) and outputs the absolute value, and outputs the first and second absolute value circuits 703 and 704, and compares the two input signals to output the comparison result. 705, a first code detector 708 that receives an input I (K) of an I channel, detects and outputs a code, and a second code that receives a Q Q input of a Q channel, and outputs a detected code. Binary data receiving a detector 709, a comparison output of the comparator 705, and code detection outputs of the first and second code detectors 708 and 709, and representing a representative phase band corresponding to the input signals. It consists of a binary code generator 707 that outputs.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the state of FIG. 6 based on the above-described configuration of FIGS. 5 and 7.

First, the phase detector 503 receives an input I (K) of an I channel and an input Q (K) of a Q channel, and detects and outputs a DBPSK modulated phase (0 ° -360 °) from the two signals.

That is, referring to FIG. 7, the first and second absolute value circuits 703 and 704 receive the input I (K) of the I channel and the input Q (K) of the Q channel, respectively, and output an absolute value. In addition, the first and second code detectors 708 and 709 receive the input I (K) of the I channel and the input Q (K) of the Q channel, respectively, and detect and output the sign of the input signal.

The binary code generator 707 receives the comparison output of the comparator 705 and the code detection outputs of the first and second code detectors 708 and 709, and represents a representative phase band corresponding to the input signals. Print binary data.

That is, in FIG. 6, the X axis represents the phase? (K), and the Y axis represents the magnitudes of I (K) and Q (K). Therefore, since I (K) and Q (K) can be known, phase? (K) can be obtained from the sampling paths of I (K) and Q (K).

Further, if the decision bit is increased to represent the phase? (K) from the sampling values of I (K) and Q (K), a more accurate phase? (K) can be obtained. As you can see, good performance can be achieved without using many decision bits.

In one embodiment according to the present invention, for example, as shown in FIG. 6, the phase? (K) is represented as a 3-bit decision bit. Thus, 0 ° -360 ° is represented by eight representative phase bands 605-612, and each representative phase band 605-612 occupies a phase by 45 °. That is, when the phase? (K) is determined from inputs I (K) and Q (K) of the K-th sampling period,? (K) is represented by a representative phase band from P (605) to 7 (612). .

Thereafter, in FIG. 5, the delay unit 504 receives the detected phase from the phase detector 503 and outputs the signal after one sampling delay. A subtractor 507 receives the detection phase of the current sampling period from the phase detector 503 and the detection phase of the previous sampling period from the delayer 504, and subtracts the two detection phases consecutively. Outputs the phase difference between two sampling periods. That is, the subtractor 507 subtracts and outputs the phase? (K-1) in the K-1 th sampling period from the current phase? (K) in the current K th sampling period.

In this case, the phase difference is referred to as Δø (K), and Δø (K) is given by Equation 18 by the sum of Equation 15 and Equation 16, and Δø _offset (K) is given by Equation 19 Appears together.

△ ø (K) = △ ø _mod (K) + △ ø _offset (K) ......................... (18)

△ ø (K) △ _mod (K) ............ ........ (19)

In the equations 18 and 19, Δø _mod (K) is 0 ° or 180 °. Therefore, the output of the subtractor 507 passes through an absolute value circuit (Absolutor) 508 and is then input to the data determiner 509 so that the phase difference? (K) is close to 0 ° or close to 180 ° according to Equation 18. And close to 0 ° demodulate to data " 0 &quot;, and close to 180 ° demodulate to data " 1 &quot;.

That is, the data determination and demodulation output operation of the above-described data determiner can be expressed as follows.

-90 ° <△ ø (K) ≤90 °: Demodulation of data "0" ... (20)

90 ° <Δø (K) ≤-90 °: Data "1" Demodulation ..... (20)

Therefore, as described above, the present invention does not require the configuration of the multiplier, and the configuration of the delay is reduced, thereby simplifying the configuration of the circuit. In addition, since the circuit configuration is simplified, the operation speed is increased and power consumption is reduced.

Claims (7)

A differential two-phase shift keying receiver comprising: a phase detector configured to receive an input I (K) of an I channel and an input Q (K) of a Q channel, and detect a phase of a DBPSK modulated signal; and a phase detected from the phase detector. Receives a delay and outputs after a one-sampling delay, a phase of the current sampling period from the phase detector and a detection phase of the previous sampling period from the delay is received, and the two detection phases are subtracted to successive two A subtractor for outputting a phase difference between sampling periods, an absolute value circuit for receiving the phase difference value from the subtractor and outputting the absolute value, and an output of the absolute value circuit, and determining and demodulating data in response to an input signal A differential two-phase shift keying demodulator comprising an output data determiner. The absolute value circuit of claim 1, wherein the phase detector receives an input I (K) of an I channel and an input Q (K) of a Q channel and outputs an absolute value circuit and an output of the absolute value circuit. A comparator for comparing signals and outputting a comparison result, a code detector for receiving inputs I (K) and Q (K) of an I channel, detecting and outputting respective codes, a comparison output of the comparator, and the code And a binary code generator for receiving a code detection output of a detector and outputting a detection phase of a binary code represented by a representative phase band in response to the input signals. The second absolute value circuit according to claim 2, wherein the absolute value circuit receives the input I (K) of the I channel and outputs the absolute value and outputs the absolute value of the input channel I (K) of the Q channel. Differential two-phase shift keying demodulator, characterized in that the configuration. 3. The apparatus of claim 2, wherein the code detector receives an input I (K) of an I channel and detects and outputs a code. The code detector detects and outputs a code by receiving an input Q (K) of a Q channel. A differential two-phase shift keying demodulator comprising a second code detector. 4. The apparatus of claim 3, wherein the code detector receives the input I (K) of the I-channel and detects and outputs the code, and detects and outputs the code by receiving the input I (K) of the Q-channel. A differential two-phase shift keying demodulator comprising a second code detector. A differential two-phase shift keying demodulation method, comprising: a phase detection step of receiving input I (K) of an I channel and input I (K) of a Q channel, and detecting a phase of a DBPSK modulated signal; A phase difference calculation step of calculating a phase difference between two consecutive sampling periods from a previous detection phase, an absolute value step of obtaining an absolute value of the phase difference, and a data determination step of demodulating data corresponding to a predetermined reference value from the absolute value Differential two-phase shift keying demodulation method characterized in that the configuration. 7. The data determining method of claim 6, wherein the data determining step determines whether the absolute value is close to '0' or close to 180 °, demodulates to data "0" if close to 0 °, and data "1 to close to 180 °. Differential two-phase shift keying demodulation method characterized in that it is a data determination step of demodulating.