KR950005050B1 - Code generator - Google Patents

Abstract

This generator converts a variable length code generated due to a variable length coding to a constant length unit. It comprises: (a) a memories (30),(31) having a first and a second nonvolatile momory; (b) a control (100) generating a multiplexing selection signal and an output clock to transform and control the variable length code to a constant length unit; (c) a multiplexer (40) that responds to a selection signal of the control part and outputs a constant bit of data; (d) a first delay (50) outputting an output data of the multiplexer with delay; (e) a second delay (51) outputting an output data of a first nonvolatile memory; and (f) an output latch (60) that responds to an output clock and finally outputs the delay-outputted data of constant bit. This generator is suitable for a high speed processing of data and has stability of data at high speed operation too.

Description

Code generator

1 is a block diagram of a code generator in accordance with the present invention.

2 is a detailed circuit diagram of the control unit 100 in the first diagram.

3 is an operation timing diagram according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code generator for converting a variable length code generated by variable length coding into a predetermined length unit, and more particularly, to a code generator suitable for high-speed processing of data.

Typically disclosed video signal processing devices (e.g., digital TV and VTR systems, CD-ROMs, HDTVs, etc.) Huffman coding to compress or transmit still video or moving pictures ).

Such Hoffman coding is a type of variable length coding, and is usually coded after discrete cosine transform (DCT) and quantization.

The image data on the transform region generated by the Hoffman coding is a variable length code having a variable length according to the complexity of the original image.

In order to record such variable length codes on a recording medium (e.g., IC card, magnetic tape or magnetic disk), it is necessary to convert them into codes having a certain length and then record them.

Conventionally, a code generator composed of a shift register or the like has been employed to convert a variable-length code generated after Huffman coding into a code having a fixed length unit.

The code generator composed of the shift register was not suited for the high-speed processing, and the larger the amount of processed data, the greater the probability of data loss. This phenomenon is remarkable when a certain length unit (eg, 8 bits) needs to be processed at a high clock frequency of several tens of megabytes or more in an image encoder of 60 k bps (bit per second) or higher, because of the characteristics of the shift register. This includes not being able to expect enough operation for the clock frequency.

It is therefore an object of the present invention to provide a code generator suitable for high speed processing of data.

It is still another object of the present invention to provide a code generator for converting a predetermined length unit to ensure stability of data even at high speed.

According to an aspect of the present invention for achieving the above object, a variable long code is received as an upper input address among the input addresses, and the code value of the number of combination bits of the lower addresses applied to one upper input address is stored in advance. A memory unit having a first nonvolatile memory and a second non-anisotropic memory for storing code length data of the code values of the first nonvolatile memory and outputting the code length data corresponding to the input address; ; The code length data coupled to the memory unit, the code length data output from the second nonvolatile memory, an applied main clock, and a reset signal are logically combined to provide the lower address to the memory unit, and the variable length code is a predetermined length unit. A controller configured to generate a multiplexing selection signal and an output clock for controlling conversion into a subfield; A first input terminal is connected to an output terminal of the first nonvolatile memory, and a second and third input terminals are respectively connected to first and second delayed output lines to output a predetermined bit of data in response to the selection signal of the controller. Wealth; A first delay unit connected to the multiplexer unit and delaying output data of the multiplexer in response to the applied main clock; A second delay unit connected to an output terminal of the first nonvolatile memory and delaying output data of the first nonvolatile memory in response to the applied main clock; An output latch unit is connected to an output terminal of the first delay unit and finally outputs a predetermined bit data output in response to the output clock of the controller.

Hereinafter, the configuration of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram of a code generator according to an embodiment of the present invention, in which data input to an input terminal IN is variable length data according to Huffman coded results, and the variable length data is an input latch unit responsive to a main clock MCLK. The latch is output by 20.

The variable length data output from the input latch unit 20 has the same meaning as the input address.

The first memory 30 and the second memory 31 for inputting the input address are included in the memory unit when each of the nonvolatile ROM is configured.

In addition, the control unit 100 corresponds to the control unit, the multiplexer 40, the first-second delay units 50 and 51, and the output latch unit 60 correspond to each of the above-described units to perform the corresponding flag.

FIG. 2 is a detailed circuit diagram of the controller 100 of the first diagram, and is reset by the reset signal and includes first to fourth flip flops F1 and F2 for latching the code length data in response to the main clock. F3 and F4 and a plurality of logic gates AND1-AND19, OR1-OR4, and INV1-INV2, which are connected to the facets 1-4 flip-flops F1-F4 to generate the selection signal and the output clock. It is.

FIG. 3 is an operation timing diagram according to an embodiment of the present invention, and shows an operation timing relationship with respect to the input and output according to the embodiment by attaching the same reference numerals to those of FIG. 1.

Hereinafter, an embodiment of the operation based on the above-described configuration of the present invention will be described in detail.

Referring to FIG. 1, an input address that is an output of the input latch unit 20 is the variable length code. In order to obtain an output code of a predetermined length unit (for example, 8 bits) from the output latch unit 60, the first input address may be used. 2 memory (30,31), control unit 100, multiplexer unit 40, 1-2 delay unit (50, 51) is required.

First, the first memory 30 previously stores eight values (in the case of an 8-bit length unit) with respect to one input address, wherein the input address corresponds to the upper address 8 bits (3: A). The lower address is divided into 3 bits (0: 2) and input respectively.

The upper address is an address output from the input latch unit 20, and the lower address is an address output from the control unit 100.

Accordingly, an example of code values and code lengths stored in the first memory 30 and the second memory 31 is shown in Table-1.

TABLE 1

.

As shown in Table 1, eight code values are stored in the first memory 30 corresponding to the upper address, and the second memory 31 stores the pure data number of the code values corresponding to the corresponding addresses. In reading, the code length data of Table-1 is provided to the input terminal LEN of the controller 100 as an output terminal RN.

That is, the second memory 31 contains the number of pure bit data of each code value of the first memory 30.

The controller 100 transmits the lower address to the address input terminal A2 of the first-memory memories 30 and 31 in response to the code length data Len (0: 3) applied from the second memory 31. ADDR (0: 2) is applied, and select signals S1 and S2 and output WCLK for generating codes having a predetermined length unit are applied to output terminals S14 and WCLK.

A detailed configuration of the controller 100 is shown in FIG. 2, which will be described.

The first to fourth flip-flops F1 to F4 are configured as D-flip flops, and the code length data (for example, 4 bits) lines are connected to each input terminal D, respectively. In addition, each clock stage is provided with the main clock MCLK, and a reset stage RESET is connected to each other.

Accordingly, data logic and gates OR1-OR3, AND2-AND4, and5 in all cases appearing in the respective output lines E, D, C, and B of the first to fourth flip-flops F1 to F4. The data logic appearing on the output lines (fh, ik, s4, S11-S27) of -AND18 is summarized as shown in Table-2 below.

TABLE 2

The selection signal S14 generated according to Table 2 is applied to the selection terminal S of the multiplexer 40 through the lines S1 and S2 of FIG.

Here, the multiplexer 40 may be configured by combining eight commercially available 4: 1 multiplexers. In this case, one input terminal of each multiplexer 40 is not connected. Of course, two signals of the selection signal S14 are input to the selection terminal of each of the halt multiplexers.

And it is desirable to ground the selection terminal of the last multiplexer. The multiplexer unit 40 may output data in units of 8 bits by a selection signal applied to the selection terminal S, which will be described below. For example, initially, if the number of valid bits (length) of data provided to the input line Val (0: 7) of the multiplexer section 40 is less than eight, for example, the first delay section 50 is less than eight. The data having a small number of bits is delayed by the main clock, and the delayed data is provided to the input terminal D2 of the multiplexer unit 40 again. Therefore, after that, the data applied to the input terminal Val (0: 7) and the delayed data can be combined by the multiplexer unit 40 operated by the selection signal and output as 8-bit data.

In addition, when larger than 8 bits, the remaining data is delayed by the second delay unit 51 and then applied to the input terminal D3 of the multiplexer unit 40. Therefore, the data to be applied thereafter and the delayed data are output as 8 bits.

Therefore, the control unit 100 sets the output clock WCLK only when the input lines Val, D2, and D3 of the multiplexer 40 are input in predetermined bit units (8 bits). ), So that the output latch unit 60 outputs an 8-bit unit code to the output (out).

To explain this, reference is made to FIG. 3 with respect to FIG.

At the time of standing (rising edge point) of the main clock MCLK applied to each part of FIG. 1, the 8-bit upper address ADDR and the 3-bit lower address ADDR are stored in the 1-2 memory 30-31. When applied to, the read code values are output to the output terminal CV of the first memory 30 as Val (0: 7) and Val (8: F) of FIG.

In this case, if the code length data inputted to the controller 100 appears as Len (0: 3) of FIG. 3, the lower address outputted from the controller 100 is the ADDR (0: 2) of FIG. 3. The same as S1 (1: 7) and S2 (1: 7) are applied to the selection stage S of the multiplexer 40, respectively.

Accordingly, it is understood that D2 (0: 7) and (0: 7) of FIG. 3 are displayed on the input lines D2 and D3 of the multiplexer 40 and D1 (0: 7) is output to the output line D1. Can be.

At this time, the light clock W of FIG. 3 is generated in the line W of FIG. 2 and the output clock WCLK is generated by the AND gate AND19 as the latch clock of the output latch unit 60 of FIG. Is approved.

Accordingly, an 8-bit length code such as 0 (0: 7) of FIG. 3 is output to the output door 0 of the output latch unit 60.

For example, when there is an input corresponding to 5 bits as described in the above description, the controller 100 waits for 3 more bits to enter 8 bits to apply an output clock to the output latch unit 60. You will know.

Therefore, since the present invention operates at a higher speed than outputting a constant code length unit due to the delay of the shift register as before, the probability of data loss is remarkably improved.

As described above, the present invention has the advantage of preventing the loss of data by achieving stability of the data at the time of high-speed data processing.

Claims (3)

A code generator for receiving a variable length code generated by variable phase coding and converting the same into a predetermined length unit, the variable length code being received as an upper input address among input addresses and applied to one upper input address. A code length data corresponding to the first nonvolatile memory and the code values of the first nonvolatile memory, which store as many code values as the number of combination bits of a lower address in advance, and store the code length data corresponding to the input address. A memory unit having a second nonvolatile memory for outputting the memory; The code length data coupled to the memory unit, the code length data output from the second nonvolatile memory, an applied main clock, and a reset signal are logically combined to provide the lower address to the memory unit, and the variable length code is a predetermined length unit. A controller configured to generate a multiplexing selection signal and an output clock for controlling conversion into a signal; A first input terminal is connected to an output terminal of the first nonvolatile memory, and a second and third input terminals are respectively connected to first and second delayed output lines to output a predetermined bit of data in response to the selection signal of the controller. Wealth; A first delay unit connected to the multiplexer unit and delaying output data of the multiplexer in response to the applied main clock; A second delay unit connected to an output terminal of the first nonvolatile memory and delaying and outputting output data of the first nonvolatile memory in response to the applied main clock; And an output latch unit connected to an output terminal of the first delay unit to finally output the first delayed constant bit data in response to the output clock of the controller. The code generator as set forth in claim 1, wherein said memory means comprises a read-only memory, wherein said upper address is 8 bits and said lower address is 3 bits. 3. The control unit as set forth in claim 2, wherein the control unit is reset by the reset signal and includes first to fourth flip flops F1 to F4 for latching the code length data in response to the make clock, and the first to fourth flips. A logic gate (AND1-AND19, OR1-OR4, INV1-INV2) consisting of a plurality of AND gates, an OR gate, and an inverter connected to the flop (F1-F4) to generate the selection signal and the output clock. Code generator.