KR940012823A - Clock signal generation circuit - Google Patents

Clock signal generation circuit Download PDF

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Publication number
KR940012823A
KR940012823A KR1019930024042A KR930024042A KR940012823A KR 940012823 A KR940012823 A KR 940012823A KR 1019930024042 A KR1019930024042 A KR 1019930024042A KR 930024042 A KR930024042 A KR 930024042A KR 940012823 A KR940012823 A KR 940012823A
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KR
South Korea
Prior art keywords
clock signal
output
signal
main clock
timing
Prior art date
Application number
KR1019930024042A
Other languages
Korean (ko)
Inventor
기미요시 우사미
Original Assignee
사토 후미오
가부시키가이샤 도시바
오카모토 세이시
도시바 마이크로 일렉트로닉스 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 사토 후미오, 가부시키가이샤 도시바, 오카모토 세이시, 도시바 마이크로 일렉트로닉스 가부시키가이샤 filed Critical 사토 후미오
Publication of KR940012823A publication Critical patent/KR940012823A/en
Priority to KR2019980019617U priority Critical patent/KR200152703Y1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Abstract

본 발명은, 선충전식 회로의 어드레스신호 또는 입력데이터가 확정되는 타이밍에 따라 선충전기간을 설정하는 클록시호를 생성하는 클록신호 생성회로 및 이 회로를 갖춘 선충전식 집적회로를 제공하고자 함에 그 목적이 있다.It is an object of the present invention to provide a clock signal generation circuit for generating a clock signal for setting a precharge period in accordance with a timing at which an address signal or input data of a precharge circuit is determined, and a precharge integrated circuit having the circuit. have.

이를 위해 본 발명은, 주클록신호를 받아서 반전출력하는 제1인버터회로(4)와, 주클롤신호와, 어드레스신호 또는 입력데이터가 주클록신호에 대하여 확정되는 타이밍을 나타내는 타이밍신호를 받는 논리합게이트(6), 제1인버터회로(4)의 출력단자와 전원 사이에 접속되어서 논리합 게이트(6)의 출력에 따라 도통제어되는 FET(P2) 및, 제1인버터회로(4)의 출력을 받아서 반전출력하고, 타이밍신호에 따라 주클록신호의 듀티비가 가변되어 이루어진 클록신호를 생성하는 제2인버터회로(5)로 구성된다.To this end, the present invention provides a logic sum gate for receiving a first clock signal 4 that receives the main clock signal and inverting the main clock signal, a main clock signal, and a timing signal indicating a timing at which an address signal or input data is determined with respect to the main clock signal. (6) FET (P2) connected between the output terminal of the first inverter circuit (4) and the power supply and conductingly controlled in accordance with the output of the logic sum gate (6) and the output of the first inverter circuit (4) and inverted And a second inverter circuit 5 for generating a clock signal in which the duty ratio of the main clock signal is varied in accordance with the timing signal.

Description

클록신호 생성회로Clock signal generation circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 1실시예에 따른 선충전식 집적회로의 구성을 나타낸 도면.1 is a diagram showing the configuration of a pre-charged integrated circuit according to an embodiment of the present invention.

제2도는 제1도의 도시된 선충전식 집적회로에 구비된 본 발명의 1실시예에 따른 클록신호 생성회로의 구성을 나타낸 도면.2 is a diagram showing the configuration of a clock signal generation circuit according to an embodiment of the present invention provided in the precharge integrated circuit shown in FIG.

제4도는 본 발명의 1실시예에 따른 클록신호 생성회로의 다른 구성을 나타낸 도면.4 is a diagram showing another configuration of a clock signal generation circuit according to an embodiment of the present invention.

Claims (3)

주클록신호와, 클록신호에 따라 선충전동작이 이루어지는 회로의 출력을 선택 결정하는 신호가 주클록신호에 대하여 확정되는 타이밍을 나타내는 타이밍신호를 받아서 타이밍신호에 따라 주클록신호의 듀티비를 가변시켜 클록신호를 생성하도록 구성된 것을 특징으로 하는 클록신호 생성회로.The duty cycle of the main clock signal is varied according to the timing signal by receiving a timing signal indicating a timing at which the main clock signal and a signal for selecting the output of the circuit for which the precharge operation is performed according to the clock signal are determined with respect to the main clock signal. And a clock signal generation circuit configured to generate a clock signal. 주클록신호를 받아서 반전출력하는 제1인버터회로(4)와, 상기 주클록신호와, 클록신호에 따라 선충전동작이 이루어지는 회로의 출력을 선택결정하는 신호가 주클록신호에 대하여 확정되는 타이밍을 나타내는 타이밍신호를 받아 논리합게이트(6), 제1인버터회로의 출력단자와 전원 사이에 접속되어서 논리합게이트의 출력에 따라 도통제어되는 FET (P2) 및, 상기 제1인버터회로(4)의 출력을 받아서 반전출력하고, 타이밍신호에 따라 주클록신호의 듀티비가 가변되어 이루어진 클록신호를 생성하는 제2인버터회로 (5)를 갖춘 것을 특징으로 하는 클록신호 생성회로.The timing of determining the first inverter circuit 4 for receiving the main clock signal and inverting the output signal, and for determining the output of the main clock signal and the output of the circuit in which the precharge operation is performed according to the clock signal are determined with respect to the main clock signal. In response to the timing signal indicative, the logic sum gate 6 is connected between the output terminal of the first inverter circuit and the power supply, and the FET P2 is electrically controlled according to the output of the logic sum gate. The output of the first inverter circuit 4 And a second inverter circuit (5) for generating a clock signal obtained by inverting the output signal and varying the duty ratio of the main clock signal according to the timing signal. 주클록신호를 받아서 반전출력하는 제1인버터회로 (4)와, 상기 주클록신호와, 클록신호에 따라 선충전동작이 이루어지는 회로의 출력을 선택결정하는 신호가 주클록신호의 하이레벨기간에 있어서 확정되는 경우에 그타이밍을 나타내는 제1타이밍신호를 받는 논리합게이트 (6), 제1인버터회로 (4)의 출력단자와 고위전원 사이에 접속되어서 논리합게이트의 출력에 의해 도통제어되는 FET (P2), 클록신호에 따라 선충전동작이 이루어지는 회로의 출력을 선택결정하는 신호가 주클록신호이 로우레벨기간에 있어서 확정되는 경우에 그 타이밍을 나타내는 제2타이밍신호를 받아서 반전출력하는 제3인버터회로 (9), 주클록신호와 제3인버터회로의 출력을 받는 논리곱게이트 (8), 제1인버터회로의 출력단자와 저위전원 사이에 접속되어서 논리곱게이트의 출력에 의해 도통제어되는 FET (N2) 및, 제1인버터회로의 출력을 받아서 반전출력하고 제1또는 제2타이밍신호에 따라 주클록신호이 듀티비가 가변되어 이루어진 클록신호를 생성하는 제2인버터회로 (5)를 갖춘 것을 특징으로 하는 클록신호 생성회로.A first inverter circuit 4 for receiving the main clock signal and inverting the output signal, and a signal for selecting and determining the output of the main clock signal and the circuit in which the precharge operation is performed in accordance with the clock signal are performed in the high level period of the main clock signal. FET P2, which is connected between the output terminal of the first inverter circuit 4 and the high power supply, which is connected to the logic sum gate 6 which receives the first timing signal indicating the timing when it is determined, and is electrically controlled by the output of the logic sum gate. A third inverter circuit for inverting and outputting a second timing signal indicating a timing when the main clock signal is determined in the low level period, when the main clock signal is determined in the low level period (9) ), The logical multiplication gate (8) receiving the main clock signal and the output of the third inverter circuit, and connected between the output terminal of the first inverter circuit and the low power supply, A second inverter circuit (5) which receives the output of the FET (N2) controlled by the conduction control and inverts the output of the first inverter circuit, and generates a clock signal in which the main clock signal is varied in duty ratio according to the first or second timing signal. Clock signal generation circuit comprising: a. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930024042A 1992-11-18 1993-11-12 Clock signal generation circuit KR940012823A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019980019617U KR200152703Y1 (en) 1992-11-18 1998-10-14 Clock signal generator

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP30869392 1992-11-18
JP92-308693 1992-11-18

Publications (1)

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KR940012823A true KR940012823A (en) 1994-06-24

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Application Number Title Priority Date Filing Date
KR1019930024042A KR940012823A (en) 1992-11-18 1993-11-12 Clock signal generation circuit

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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5828612A (en) * 1997-10-27 1998-10-27 Motorola, Inc. Method and circuit for controlling a precharge cycle of a memory device
CA2250538A1 (en) 1998-10-30 2000-04-30 Mosaid Technologies Incorporated Duty cycle regulator
US6831493B2 (en) * 1998-10-30 2004-12-14 Mosaid Technologies Incorporated Duty cycle regulator
US6816932B2 (en) * 2000-10-06 2004-11-09 Broadcom Corporation Bus precharge during a phase of a clock signal to eliminate idle clock cycle
US6662136B2 (en) * 2001-04-10 2003-12-09 International Business Machines Corporation Digital temperature sensor (DTS) system to monitor temperature in a memory subsystem
US6788585B1 (en) 2002-11-27 2004-09-07 Cisco Technology, Inc. System and method for processing data in a memory array

Family Cites Families (8)

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Publication number Priority date Publication date Assignee Title
US5133064A (en) * 1987-04-27 1992-07-21 Hitachi, Ltd. Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices
JPH01256093A (en) * 1988-04-05 1989-10-12 Matsushita Electric Ind Co Ltd Register file
JPH0292012A (en) * 1988-09-29 1990-03-30 Toshiba Corp Pulse generating circuit
US5008563A (en) * 1989-09-05 1991-04-16 Eastman Kodak Company Adjustable clock generator circuit
JP2925600B2 (en) * 1989-11-07 1999-07-28 富士通株式会社 Semiconductor storage device
US5059818A (en) * 1990-06-01 1991-10-22 Advanced Micro Devices, Inc. Self-regulating clock generator
JP3018554B2 (en) * 1991-04-25 2000-03-13 株式会社日立製作所 Semiconductor module and method of manufacturing the same
US5315164A (en) * 1993-05-26 1994-05-24 Nec America, Inc. Adaptive clock duty cycle controller

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