KR940011495B1 - Method of checking a call processor performance of full electronics exchange system - Google Patents
Method of checking a call processor performance of full electronics exchange system Download PDFInfo
- Publication number
- KR940011495B1 KR940011495B1 KR1019910024041A KR910024041A KR940011495B1 KR 940011495 B1 KR940011495 B1 KR 940011495B1 KR 1019910024041 A KR1019910024041 A KR 1019910024041A KR 910024041 A KR910024041 A KR 910024041A KR 940011495 B1 KR940011495 B1 KR 940011495B1
- Authority
- KR
- South Korea
- Prior art keywords
- processor
- call
- timer
- performance
- processing
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54575—Software application
- H04Q3/54591—Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/16—Service observation; Fault circuit; Testing
Abstract
Description
제1도는 본 발명의 관련된 전전자 교환기의 구조도.1 is a structural diagram of a related electron exchanger of the present invention.
제2도는 입력 데이타를 처리하는 흐름도.2 is a flow chart of processing input data.
제3도는 사용중 상태에서 연결 통보나 불가 통보를 받은 후의 처리 흐름도.3 is a flow chart of processing after receiving a connection notification or a non notification when in use.
제4도는 타임 아웃되어 오는 신호에 대한 처리 흐름도.4 is a process flow diagram for a signal that is timed out.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 가입자 교환 서비시스템(ASS) 12 : 연결망 서브시스템(INS)11 Subscriber Switching Service (ASS) 12 Linked Network Subsystem (INS)
13 : 가입자 교환 프로세서(ASP) 14 : 연결망 프로세서(INP)13 Subscriber Switched Processor (ASP) 14: Connected Network Processor (INP)
15 : 공간 스위치 프로세서(SSP) 16 : 공간 스위치(SSW)15: Space Switch Processor (SSP) 16: Space Switch (SSW)
17 : 스위치 망 제어블럭(SNC)17: Switch Network Control Block (SNC)
본 발명은 전전자 교환기에서의 연결망 서브시스템의 연결망 프로세서(INP ; Interconnection Network Processor)에 대한 호 처리 성능을 측정하는 방법에 관한 것이다.The present invention relates to a method for measuring call processing performance for an INP (Interconnection Network Processor) of an interconnection network subsystem in an electronic switching center.
본 발명에서 연결망 서브시스템(INS ; Interconnection Network Subsystem)은 분산 수용된 가입자의 통화로 집중 관리 기능과 공간 스위치 제어 기능을 수행하며, 집중화된 호 처리 기능 부분을 수행하는 연결망 프로세서(INP ; Interconnection Network Processor)와 공간 스위치 제어 기능을 수행하는 공간 스위치 프로세서(SSP ; Space Switch Processor)를 구비한다. 본 발명에서는 상기 연결망 프로세서(INP)를 성능 측정 대상으로 한다.In the present invention, the Interconnection Network Subsystem (INS) is an INP (Interconnection Network Processor) that performs centralized management and spatial switch control functions for distributed calls of subscribers and performs centralized call processing functions. And a Space Switch Processor (SSP) that performs a space switch control function. In the present invention, the connection network processor INP is a performance measurement target.
교환기 시스템에서는 기능 실현뿐만 아니라 호 처리 성능도 대단히 큰 영향을 주는 인자이다. 기능 실현이 잘 되어 있어도 성능이 낮은 시스템이라면 전전자 교환기로서의 기능을 제대로 수행하지 못한다. 이러한 성능을 제대로 측정하고 평가를 하는 일은 중요하며 시뮬레이션 프로그램을 어떻게 실현하느냐에 따라 성능이 다르게 나올 수도 있다.In the exchange system, not only the function realization but also the call processing performance is a significant factor. Even if the function is well realized, a low-performance system may not function properly as an electronic switch. It is important to measure and evaluate this performance properly, and performance may vary depending on how the simulation program is implemented.
따라서, 본 발명은 성능을 측정하는 데 있어 실세계 환경과 유사하게 호를 발생시키고 해당 프로세서의 점유율을 계산하여 성능을 측정하는 방법을 제공하는데에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for measuring performance by generating a call and calculating a share of the processor in a similar way to real-world environments in measuring performance.
상기 목적을 달성하기 위하여 본 발명은, 호 연결 요구를 하는 모의 프로그램이 실장된 가입자 교환 프로세서(ASP)를 구비한 가입자 교환 서브시스템(ASS)과, 상기 가입자 교환 서브시스템에 연결되고 성능을 측정하고자 하는 프로세서(INP)와 공간 스위치 제어 기능을 수행하는 공간 스위치 프로세서(SSP)를 구비한 연결망 서브시스템(INS)를 포함하는 전전자 교환기에 적용되는 호 처리 성능 측정 방법에 있어서, 원하는 양만큼의 호를 발생시키는 제1단계, 일반 호 처리 판정을 거쳐 통보되어 온 갯수를 측정하는 제2단계, 측정하고자 하는 프로세서의 점유율을 계산하여 성능을 평가하는 제3단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a subscriber exchange subsystem (ASS) having a subscriber exchange processor (ASP) equipped with a simulated program for making a call connection request, and to measure the performance of the subscriber exchange subsystem. A method for measuring call processing performance applied to an electronic switching system including a network subsystem (INS) having a processor (INP) and a space switch processor (SSP) performing a space switch control function, the desired amount of calls The first step of generating a second step, the second step of measuring the number reported through the general call processing determination, and the third step of evaluating the performance by calculating the occupancy of the processor to be measured.
이하, 첨부된 도면을 사용하여 본 발명의 일실시예를 상세히 설명한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
제1도는 전전자 교환기의 연결망 서브시스템(INP)의 성능 측정과 관련된 구조도로서, 도면에서, 11은 가입자 교환 서브시스템(ASS), 12는 연결망 서브시스템(INS), 13은 가입자 교환 프로세서(ASP), 14는 연결망 프로세서((NP), 15는 공간 스위치 프로세서(SSP), 16은 공간 스위치(SSW), 17은 스위치 망 제어블럭(SNC)을 각각 나타낸다.FIG. 1 is a structural diagram related to performance measurement of an INP of an electronic switching center, in which 11 is a subscriber switching subsystem (ASS), 12 is a network subsystem (INS), and 13 is a subscriber switching processor (ASP). 14 denotes a network processor (NP), 15 denotes a spatial switch processor (SSP), 16 denotes a spatial switch (SSW), and 17 denotes a switch network control block (SNC).
ASS(Access Switching Subsystem)(11)은 ASP(Access Switching Processor(13)에는 호 연결 요구를 하는 모의 프로그램이 실장된다.In the ASS (Access Switching Subsystem) 11, the ASP (Access Switching Processor 13) is mounted a mock program for making a call connection request.
성능을 측정하고자 하는 프로세서는 INS(Interconnection Network Subsystem)(12))의 INP(14 ; Interconnection Network Processor)이며 실제 실행되는 블럭은 SNC(17 ; Switching Network Control)이다. 호연결 요구시 SNC(17)는 SSP(15 ; Space Switch Processor)에 있는 SSW(16 ; Space Switch)와 연계하여 스페이스 스위치를 제어한다.The processor for which the performance is to be measured is an INP 14 (Interconnection Network Processor) of the INS (Interconnection Network Subsystem) 12, and the actual execution block is an SNC 17 (Switching Network Control). When the call connection request is made, the SNC 17 controls the space switch in association with the SSW 16 (Space Switch) in the SSP 15 (Space Switch Processor).
제2도는 본 발명에 의한 입력 데이타를 처리하는 흐름도이다. 먼저, 사용자가 메뉴방식으로 원하는 양만큼의 호의 발생요구를 한다. 즉, 호 발생 주기를 입력(21, 이하, A라 함)하는데, 1시간은 3600초이므로 360ms의 배수로 발생 주기를 정하는 것이 좋다. 그리고, A주기동안 몇 호를 발생시킬 것인지 입력한다(22, 이하 B라 함). 가령 360ms동안 10호를 발생시키면 최번시 시도 호수 (BHCH ; Busy Hour Call Attempt)가 10만이 되는 것이다.2 is a flowchart of processing input data according to the present invention. First, the user requests the generation of the desired amount of calls by the menu method. That is, the call generation period is input (21, hereinafter referred to as A). Since one hour is 3600 seconds, it is preferable to set the generation period in multiples of 360 ms. Then, enter how many arcs to generate during A cycle (22, hereinafter referred to as B). For example, if you generate 10 calls for 360ms, you will have 100,000 Busy Hour Call Attempt (BHCH).
그런후, 얼마동안 측정할 것인지 입력한다(23, 이하, C라 함). 데이타 입력이 끝나면 A주기의 타이머를 작동시킨다(24). 이 타이머는 타임 아웃될 때 마다 호 연결 요구를 한다. 다음은 C주기의 타이머를 구동시킨다(25). 이 타이머는 전체 시뮬레이션 시간에 대한 타이머이다. 타이머를 구동시킨 후, 호 연결 요구를 B번 한다. 회선의 상태는 사용중으로 간다(27).Then enter how long you want to measure (23, hereinafter C). After the data input, the timer of A cycle is started (24). This timer makes a call connection request whenever it times out. Next, the timer of the C cycle is driven (25). This timer is a timer for the entire simulation time. After running the timer, make a call connection request B times. The state of the line goes to busy (27).
제3도는 사용중 상태에서 연결 통보나 불가 통보를 받은 후의 처리 단계이다.3 is a processing step after receiving a connection notification or a non notification when in use.
연결 통보를 받는 경우(31)에는 성공 횟수를 하나 증가시키고(32), 성공한 회선에 대해서는 채널 해제 요구를 한다(33). 불가 통보를 받는 경우는(34) 실패 횟수를 하나 증가하여(35) 통계데이타를 처리하며 회선의 상태는 휴지 상태로 한다(36).If the connection notification is received (31), the number of successes is increased by one (32), and a channel release request is made for the successful line (33). If notified (34), the number of failures is increased by one (35) to process statistical data, and the state of the line is set to idle (36).
제4도는 본 발명의 수행중에 타임 아웃되어 오는 시그날에 대한 처리이다.4 is a process for signals that time out during the implementation of the present invention.
A주기의 타이머가 타임 아웃되어 오는 경우에는(41) 다시 B번의 호 연결 요구를 한다(42). 이때, 측정하고자 하는 프로세서의 점유율을 계산한다(43). 프로세서의 점유율이 100%가 되는 경우에는 처리 능력이 한계에 도달한 것으로 그 때의 BHCA를 호 처리 성능으로 한다(44). C주기 타이머에 의해 A주기 타이머가 동작이 멈출때까지 B번씩 연결 요구를 한다.When the timer of the A cycle has timed out (41), a call connection request of B is made again (42). At this time, the share of the processor to be measured is calculated (43). If the processor occupies 100%, the processing capacity has reached its limit, and the BHCA at that time is used as the call processing performance (44). The C cycle timer makes a connection request B times until the A cycle timer stops operating.
C주기 타이머가 타임 아웃되어 오는 경우는(45) 구동중이던 A주기 타이머의 동작을 멈추게 하고(46) 통계 데이타(성공율, 실패율)를 수집하고(47), 모든 수행을 종료한다(48).When the C cycle timer has timed out (45), the operation of the A cycle timer that has been driven is stopped (46), statistical data (success rate, failure rate) is collected (47), and all executions are finished (48).
상기와 같이 구성하여 작동하는 본 발명은, 전전자 교환기의 연결망 서브시스템(INP)의 성능 평가에 적용되어 호 발생을 실상황과 같게 구현함으로서 정확한 성능 평가가 되도록 하였으며 호의 발생 횟수나 시간을 사용자가 정할 수 있어 다양한 평가를 수행할 수 있는 효과가 있다.The present invention, which is configured and operated as described above, is applied to performance evaluation of the INP of an electronic switchboard so that call generation can be performed in the same manner as the actual situation, so that accurate performance evaluation can be performed. As a result, various evaluations can be performed.
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910024041A KR940011495B1 (en) | 1991-12-23 | 1991-12-23 | Method of checking a call processor performance of full electronics exchange system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910024041A KR940011495B1 (en) | 1991-12-23 | 1991-12-23 | Method of checking a call processor performance of full electronics exchange system |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930015906A KR930015906A (en) | 1993-07-24 |
KR940011495B1 true KR940011495B1 (en) | 1994-12-19 |
Family
ID=19325718
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910024041A KR940011495B1 (en) | 1991-12-23 | 1991-12-23 | Method of checking a call processor performance of full electronics exchange system |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR940011495B1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100332202B1 (en) * | 1997-12-26 | 2002-08-17 | 주식회사 하이닉스반도체 | Method for measuring load of bcp in mobile communication system |
KR100788139B1 (en) * | 2001-05-31 | 2007-12-21 | 주식회사 케이티 | Method and Apparatus for Measurementing of A Space Switch Performance in Time Division Exchange |
-
1991
- 1991-12-23 KR KR1019910024041A patent/KR940011495B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR930015906A (en) | 1993-07-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS61140263A (en) | Traffic simulation apparatus for testing exchange equipment | |
US5892818A (en) | Method of controlling message overload on a program in a plural processor controlled switching system | |
KR940011495B1 (en) | Method of checking a call processor performance of full electronics exchange system | |
US20070116188A1 (en) | Simulate usercalling's test system and method which built-in digital spc-exchange | |
JPH02271763A (en) | Digital subscriber line quality monitor system | |
KR100198447B1 (en) | Call generating method in atm | |
KR100571250B1 (en) | Subscriber Location Determination using Traffic Demand Distribution Modeling | |
KR950008111B1 (en) | The method measuring call traffic for an electronic exchanger | |
FI104594B (en) | Storing events in a service database system | |
KR100341390B1 (en) | Performance test system and test control method for Intelligent Peripheral | |
KR960013971B1 (en) | Attend consol interface device & its operation method for pbx | |
KR0136502B1 (en) | Basic Call Processing Simulation Method for Intelligent Network Service Application Process Function Test in Service Switch | |
KR950012584B1 (en) | Electronics exchanger | |
KR0138595B1 (en) | Apparatus for simulating personal mobile application protocol | |
KR100258499B1 (en) | Method for processing statistics by outgoing prefix of full-electronic telephone exchange system | |
KR100266260B1 (en) | Method of measuring primitive operating time of full electronic telephone exchange | |
KR900003624B1 (en) | Method improving reliability in communicating data between processors | |
CN116321287A (en) | Neighbor optimization method, neighbor optimization device and computer-readable storage medium | |
KR100264492B1 (en) | Method for output processing statistics by route of full-electronic exchange system | |
KR100290622B1 (en) | Method for formating input frame of telephony network simulator | |
KR0143046B1 (en) | Exchange-tone transmission & receiving card simulation method | |
RU2127896C1 (en) | Process of generation of signal in electronic commutation system | |
KR100600948B1 (en) | Digital subscriber's test method using analog subscriber's test equipment and switching resource | |
KR940011496B1 (en) | Method of making a task in real time system | |
KR100295459B1 (en) | Signal Delay Analysis Method for Arrangement of Physical Entities of Functional Entities |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 19980929 Year of fee payment: 5 |
|
LAPS | Lapse due to unpaid annual fee |