KR940009474B1 - Variable dynamic divider circuit - Google Patents

Abstract

The adjustable dynamic divider circuit includes first through fifth output means in parallel structured as a string NAND cell type to maintain a regular high-frequency clock signal and dividing control signal in a constant logic level by receiving them as a common signal of each gate terminal to repeatedly perform a turn On/Off operation, thus temporarily storing data in the capacitors; and a divider control signal which receives a plurality of control signals as a common control signal of each gate terminal according to a frequency dividing ratio determined by the peripheral circuit in accordance with the signals output from the first through fifth outputted means and then operates by dividing the first through fifth output means into divider 5 through divider 2 circuits.

Description

Variable Dynamic Divider Circuit

1 is a circuit diagram showing an embodiment of a conventional static divider two circuits.

2 is a circuit diagram showing an embodiment of a conventional static divider three circuits.

3 is a circuit diagram showing an embodiment of a conventional static divider five circuits.

4 is a circuit diagram showing an embodiment of the flip-flop portion of the second and third degrees.

5 is an operational waveform diagram of each part of FIG.

6 is an operational waveform diagram of each part of FIG.

7 is a circuit diagram showing an embodiment of a variable dynamic divider circuit according to the present invention.

8 is an operational waveform diagram of each part of FIG. 7 in the case where the variable dynamic divider circuit according to the present invention operates with 5 dividers.

9 is an operational waveform diagram of each part of FIG. 7 when the variable dynamic divider circuit of the present invention operates with four divider circuits.

Fig. 10 is an operational waveform diagram of each part of Fig. 7 when the variable dynamic divider circuit of the present invention operates with three divider circuits.

Fig. 11 is an operational waveform diagram of each part of Fig. 7 when the variable dynamic divider circuit of the present invention operates with two divider circuits.

12 is an exemplary circuit diagram for dividing a high frequency frequency using a variable dynamic divider circuit according to the present invention.

The present invention relates to a divider circuit, and more particularly, to a variable dynamic divider circuit capable of varying the frequency division of a high frequency signal.

The divider circuit used in the conventional MOS integrated circuit is a static divider circuit and generates one signal in one divider hero. Examples of such divider circuits include two static dividers, three static dividers, and five static dividers.

The two static divider circuits shown in FIG. After the reset signal RB changes from the "low" state to the "high" state, the input signal is divided according to the clock signal CK to generate a divided signal.

The static divider three circuit shown in FIG. 2 is composed of two stages of flip-flop portions 1 and 2 and a NAND gate, each of which has the configuration shown in FIG. The reset signal RB is provided to one end of the NAND gate ND1, the input signal D is provided to the other end of the NAND gate ND11 through the transmission gate TM11, and the NAND gate ND11 provides its output. It is provided to the other end of the NAND gate ND12 through the inverter IN12 and simultaneously fed back to the NAND gate ND11 through the inverter IN13. The signal passing through the inverter IN12 is provided at the other end of the NAND gate ND12 and then outputted through the output terminal Q through the inverter IN14 and simultaneously fed back to the NAND gate ND12 through the inverter IN13. do.

The flip-flop of such a configuration is connected in two stages, and the output signals Q1 and Q2 of the two flip-flop portions are logically multiplied through the NAND gate to feed back to the terminal D of the flip-flop 1. Each of the three static divider circuits operates as shown in FIG. 5 according to the reset signal RB and the clock signal CK. When the reset signal RB is in the "low" state, even when the clock signal CK is generated, the output signals Q1 and Q2 of the flip-flop portion remain in the "low" state, and the output signals Q1, Each of the Q2) passes through the NAND gate ND10, becomes "high", and is fed back to the terminal D of the flip-flop 1 and input. When the reset signal RB is in the "low" state, the above state is maintained. When the reset signal RB changes from the "low" state to the "high" state and the reset signal RB becomes the "high" state, the respective flip-flops operate according to the clock signal CK. At the rising edge of the signal CK, the flip-flop 1 delays the "high" status signal, which is a feedback signal input to the terminal D, and represents the output signal Q1. (Q1) is provided to the flip-flop (2).

At this time, the output signal Q2 of the flip-flop 2 maintains the "low" state, and the flip-flop ND10 outputs the output signal Q1 of the "high" state and the output signal Q2 of the "low" state. Logically multiply " high " state signals by feeding back to the flip-flop 1.

In the flip-flop 2, the "high" state output signal Q1 of the flip-flop 1 is input, and then the output signal Q1 from the rising edge of the clock signal CK to the output signal Q2. Is delayed, and the output signals Q1 and Q2 in the " high " state are changed to the " low " state through the NAND gate ND10 and fed back to the flip-flop 1. The flip-flop 1 receives the signal of the "low" state as the delayed signal of the input signal from the previous "high" state signal at the rising edge of the clock signal CK when the signal of the "low" state is input. The output signal Q1 is provided. At this time, since the output signal Q2 of the flip-flop 2 maintains the "high" state, the flip-flop ND10 provides the "high" state signal to the flip-flop 1. The "high" state is provided to the flip-flop 1 so that the output signal Q1 exhibits a "high" state by the clock signal CK, and the flip-flop 2 is "low" of the previous flip-flop 1. The NAND gate ND10 maintains the "high" state by delaying and outputting the output signal Q1 of the "state".

The static divider 5 circuit shown in FIG. 3 is constructed by connecting flip-flops having the configuration as shown in FIG. 4 in three stages, and flips the output signals Q12 and Q13 of the respective flip-flops 12 and 13. It is configured to logically multiply through the flop ND20 to feed back to the flip-flop 11 to provide it to the terminal D. An operation waveform diagram of each component is shown in FIG.

When the reset signal RB changes from the "low" state to the "high" state, the flip-flop 11 inputs the feedback signal D by the clock signal CK to the output signal Q11. The signal D is delayed and output in a "high" state. At this time, the output signals Q12 and Q13 of the flip-flops 12 and 13 maintain the previous state "low", and the NAND gate ND20 logically multiplies the output signals Q12 and Q13 by the "high" state. Provides a signal (D).

When the output signal Q11 of the "high" state of the flip-flop 11 is input to the terminal D of the flip-flop 12, the output signal Q11 is delayed by the clock signal CK and the flip-flop 12 Is indicated by the output signal Q12. The output signal Q12 in the "high" state is provided to the flip-flop 13 as the terminal D, and at this time, the signal in the "low" state is output to the output terminal Q of the flip-flop 13. The output signal Q12 in the "high" state and the output signal Q13 in the "low" state are logically multiplied by the NAND gate ND20 to provide the flip-flop 11 with the signal "D" in the high state. . The output signal Q12 in the "high" state of the flip-flop 12 input to the flip-flop 13 is delayed according to the clock signal CK and output as the output signal Q13. The output signals Q12 and Q13 of the flip-flops 12 and 13 are changed to the "low" state through the NAND gate ND20 and are provided to the flip-flop 11.

When the signal of the "low" state is input to the flip-flop 11, the input signal of the "low" state is delayed and output to the output signal Q11 by the clock signal CK, and at this time, the flip-flops 12 and 13 are It retains its previous state. When the output signal Q11 of the flip-flop 11 in the "low" state is input to the flip-flop 12, the output signal Q11 is delayed by the clock signal CK, and the output signal Q12 of the flip-flop 12 is output. ), The output signal Q13 of the flip-flop 13 maintains the previous state, and the signal D fed back to the flip-flop 11 through the NAND gate ND20 is in a "high" state. Is provided. The output signal Q12 of the flip-flop 12 in the "low" state input to the flip-flop 13 is delayed by the clock signal CK and represented as the output signal Q13 of the flip-flop 13. ND20 logically multiplies the output signals Q12 and Q13 of the flip-flops 12 and 13 and provides them to the terminal D of the flip-flop 11 in a "high" state. In this manner, the input signal is divided to output a predetermined signal.

Since the conventional divider circuit has a static structure, only one signal is generated in one divider circuit, and the division ratio, phase, and duter are fixed, and the operation speed is slow.

In addition, when the division ratio is larger than 5 divisions, a number of static divider circuits are required, and the circuit configuration is complicated, resulting in a large chip area during integration and a high manufacturing cost.

The present invention has been invented to solve the above problems, and an object thereof is to provide a variable dynamic divider circuit capable of achieving high integration of a MOS integrated circuit due to a fast operation speed and a simple circuit configuration.

Another object of the present invention is to provide a variable dynamic divider circuit capable of generating signals having different division ratios, phases, and tutuities in one divider circuit.

In order to achieve the above object, the variable dynamic divider circuit according to the present invention is characterized in that the high frequency clock signal and the divided control signal periodically periodically taken from the outside are applied as the common signal at the gate stage to perform the on / off operation repeatedly. First to fifth output means configured in parallel in a string NAND cell type to temporarily store data in capacitors to maintain a constant logic level; Divider 5, Divider 4 receives the first to fifth output means by receiving a plurality of control signals according to the division ratio determined from the peripheral circuit according to the signal output from the first to fifth output means as a common control signal of the gate stage, respectively And divider control means for dividing and operating the divider 3 and divider 2 circuits.

Hereinafter, a variable dynamic divider circuit according to the present invention will be described in detail with reference to the accompanying drawings.

7 is a detailed circuit diagram showing an embodiment of a variable dynamic divider circuit according to the present invention. First, the output means includes a first conductivity-type MOS transistor P2 for inputting a high frequency clock signal CK to a gate. A first output of connecting the second conductivity-type MOS transistor N1 to the node Q21, and connecting the first conductivity-type MOS transistor P1 and the second conductivity-type MOS transistor N2 in series to each transistor thereof. The means 21, the first conductivity-type MOS transistor P4 and the second conductivity-type MOS transistor N3 for inputting the high frequency clock signal CK to the gate are connected to the node Q2, and to each transistor thereof. Second output means 22 having the first conductive MOS transistor P3 and the second conductive MOS transistor N4 connected in series, and the first conductive MOS transistor for inputting a high frequency clock signal CK to the gate. P6 and the second challenge Third output means 23 connecting the MOS transistor N5 to the node Q23 and connecting the first conductive MOS transistor P5 and the second conductive MOS transistor N6 in series to each transistor thereof. And a first conductivity-type MOS transistor P8 having a high frequency clock signal CK connected to its gate, and a second conductivity-type MOS transistor N7 connected to a node Q24, and to each transistor thereof. The fourth output means 24 having the MOS transistor P7 and the second conductive MOS transistor N8 connected in series, the first conductive MOS transistor P10 having the high frequency clock signal CK connected to the gate, A fifth output in which the second conductivity-type MOS transistor N9 is connected to the node Q25, and the first conductivity-type MOS transistor P9 and the second conductivity-type MOS transistor N10 are connected in series to each transistor thereof. It consists of the means 25.

Next, the variable dynamic divider means is connected to the node Q21 of the first output means 21 and has a second conductivity type NMOS transistor N13 to which a signal is input and a control signal DS2 as inputs. A third divider control means 33 in which a type MOS transistor N14 is connected in series and a drain of the second conductivity type MOS transistor N13 is connected in parallel with a node Q22 of the second output means 22, The first conductivity-type MOS transistor P12 connected to the node Q22 of the second output means 22 and the first conductivity-type MOS transistor P12 for inverting the control signal DS1 are connected in series. Of the first divider control means 31 and the fifth output means 25 having a drain of the first conductivity-type MOS transistor P13 connected in parallel to the node Q23 of the third output means 23. The second conductivity-type MOS transistor N11 connected to the node Q25 is connected with the node. The second conductivity-type MOS transistor N12 having the troll signal DS1 as an input is connected in series so that the drain of the second conductivity-type MOS transistor N11 is connected in parallel to the node Q21 of the first output means 21. The second divider control means 32 connected, the second conductivity-type MOS transistor N19 and the control signal DS2 connected to the node Q24 of the fourth output means 24 are input, and the source is connected to ground. A second conductive MOS transistor N20 is connected in series between the second conductive MOS transistor N19 and N21 by using the connected second conductive MOS transistor N21 and the control signal DS1 as an input. The drain of the conductive MOS transistor N19 is constituted by fourth divider control means 34 connected in parallel to the node Q25 of the fifth output means 25.

The variable dynamic divider circuit of the present invention configured as described above is divided into divider 2, divider 3, divider 4, and divider 5 circuits by control signals DS1 and DS2, respectively.

This circuit always starts from the state in which the preset signal PS is input in the "high" state.

Hereinafter, the variable dynamic divider circuit of the present invention will be described in detail with reference to the waveform diagrams of FIGS. 8, 9, 10, and 11.

Preset signal PS is "high", control signal DS1 is "low", control signal DS2 is "low", and the clock signal CK is input to the variable dynamic divider circuit of the present invention. ) Is input to the "high" state, the first conductivity-type MOS transistors P1 and P2 of the first output means 21 are turned on and off, respectively, and the second conductivity-type MOS transistor N1 is on, Since the transistor N2 is turned off and the first conductivity-type MOS transistor P11 is turned on, the node Q21 is initially charged to the capacitor C1 in a "high" state, and the second output means 22 is turned on. Since the first conductive MOS transistor P3 is turned off and the transistor P4 is also turned off, and the second conductive MOS transistors N3 and N4 are turned on, respectively, the node Q22 is initialized to the capacitor C2. Is charged to a "low" state. The first conductivity-type MOS transistors P5 and P6 of the third output means 23 are turned on and off, respectively, and the second conductivity-type MOS transistors N5 and N6 are turned on and off, respectively. Since P14 is turned on, the node Q23 is initially charged to the capacitor C3 in a "high" state, and the first conductivity-type MOS transistors P7 and P8 of the fourth output means 24 are turned off. Since the second conductivity-type MOS transistors N7 and N8 are turned on, the node Q24 is initially charged to the capacitor C4 in a "low" state. The transistors P9 and P10 of the fifth output means 25 are turned on and off, respectively, and the transistors N9 and N10 are turned on and off, and the transistor N18 is turned on. Is initially charged to the capacitor C5 in the "low" state.

On the other hand, since the control signals DS1 and DS2 are in the "low" state, they do not affect the divider control units 31 to 34 at all. In this initial state, when the preset signal PS changes from the "high" state to the "low" state and the clock signal CK is periodically input at this point, each MOS transistor is in the next state at the point a of FIG. Will work.

Since transistors P1 and N1 are on and transistors P2 and N2 are off, node Q21 maintains the previous state charged to capacitor C1, and transistors P3 and P4 are off and transistors. Since node (N3, N4) is in an on state, node Q22 maintains the previous state charged in capacitor C2, and transistors P5 and N5 are on, and transistors P6 and N6 are off. Q23 maintains the previous state charged to capacitor C3, and transistors P7 and P8 are off and transistors N7 and N8 are on, so node Q24 is charged to capacitor C4. The previous state is maintained, and the transistors P9 and N9 are turned on and the transistors P10 and N10 are turned off, so that the node Q25 maintains the previous state charged in the capacitor C5.

Referring to the state of each MOS transistor at point b where the clock signal CK is "low" in FIG. 8, the transistors P1 and N1 are turned off and the transistors P2 and N2 are turned on. Q21 keeps the previous state charged to capacitor C1, and transistors P3 and N3 are turned off and transistors P4 and N4 are turned on, so node Q22 is capacitor C2. It maintains the state it was previously charged to. At this time, since the transistors P5 and P6 are on and the transistors N5 and N6 are off, the node Q23 maintains the previous state charged in the capacitor C3, and the transistors P7 and N7 are off and transistors. (P8, N8) is on, so node Q24 maintains the previous state charged to capacitor C4, transistors P9, P10 are on, and transistors N9, N10 are off. Node Q25 is charged to capacitor C5 in a " high " state.

Again, at the point C of FIG. 8 in which the click signal CK is in the "high" state, the state of the MOS transistor is as follows.

Transistors P1 and P2 are off, transistors N1 and N2 are on, so node Q21 is charged to capacitor C1 "low", transistors P3 and P4 are off and transistors N3, N4) is on, so node Q22 continues to maintain the previous state charged in capacitor C2, transistors P5 and P6 are on and off, and transistors N5 and N6 are on and off, respectively. Node Q23 maintains the previous state charged to capacitor C3, transistors P7 and P8 are off and transistors N7 and N8 are on, so node Q24 is capacitor C4. ), And the transistors P9 and N9 are turned on and the transistors P10 and N10 are turned off, so that the node Q25 maintains the previous state charged to the capacitor C5. do.

The MOS transistor at the time when the clock signal CK at the point d in FIG. 8 is in the "low" state operates as follows.

The transistors P1 and P2 are turned off and on, respectively, and the transistors N1 and N2 are turned off and on, respectively, so that the node Q21 maintains the previous state charged in the capacitor C1. Since P3 and P4 are on and transistors N3 and N4 are off, node Q22 is charged to capacitor C2 in a "high" state, and transistors P5 and P6 are off and on, respectively. Since the transistors N5 and N6 are also turned off and on, respectively, the node Q23 maintains the previous state charged to the capacitor C3. The transistors P7 and P8 are turned off and on, respectively, and the transistors N7 and N8 are turned off and on, respectively, so that the node Q24 maintains the previous state charged to the capacitor C4 and the transistor P9. , P10 is on, and transistors N9 and N10 are off so that node Q25 remains in the previous state charged to capacitor C5.

As seen from the point e of FIG. 8, the clock signal CK is in the "high" state, and each MOS transistor operates as follows.

Since transistors P1 and P2 are off and transistors N1 and N2 are on, node Q21 maintains the previous state charged to capacitor C1, and transistors P3 and P4 are on, The node Q22 maintains the previous state charged in the capacitor C2, and the transistors P5 and P6 are turned off and the transistors N5 and N6 are turned off and the transistors N3 and N4 are turned on and off, respectively. Node Q23 is charged low to capacitor C3, transistors P7 and N7 are turned on and transistors P8 and N8 are turned off, so node Q24 is connected to a capacitor (Q24). Since the transistors P9 and N9 are turned on and the transistors P10 and N10 are turned off, the node Q25 remains at the previous state charged in C4. Keep it.

When the clock signal CK at the point f of FIG. 8 is in the "low" state, the transistors P1 and N1 are turned off and the transistors P2 and N2 are turned on, so that the node Q21 is connected to the capacitor C1. Since the transistors P3 and P4 are turned on and the transistors N3 and N4 are turned off, the node Q22 maintains the previous state charged in the capacitor C2, and the transistor P5 is maintained. N5 is in an off state and transistors P6 and N6 are in an on state, so node Q23 maintains the previous state charged in capacitor C3. Since transistors P7 and P8 are on, transistors N7 and N8 are off, so node Q24 is charged to capacitor C4 "high", and transistors P9 and N9 are off and transistor ( Since P10 and N10 are turned on, the node Q25 maintains the previous state charged to the capacitor C5.

Referring to the point g of FIG. 8, when the clock signal CK is in the "high" state, the transistors P1 and P2 are turned on and off, and the transistors N1 and N2 are turned on and off. Q21 maintains the previous state charged in capacitor C1, and transistors P3 and N3 are on and transistors P4 and N4 are off, so node Q22 is charged to capacitor C2. And the transistors P5 and P6 are turned off and the transistors N5 and N6 are turned on so that the node Q23 continues to maintain the previous state charged to the capacitor C3. Since the transistors P7 and P8 are turned on and off, and the transistors N7 and N8 are turned on and off, the node Q24 maintains the previous state charged to the capacitor C4. Since P9 and P10 are off and transistors N9 and N10 are on, node Q25 is charged to capacitor C5 "low".

Referring to the point h of FIG. 8, the clock signal CK is in the "low" state, and the state of the MOS transistor is as follows.

Transistors P1 and P2 are on, transistors N1 and N2 are off, so node Q21 is charged high to capacitor C1, transistors P3 and N3 are off, and transistor P4. Node Q22 remains in the previous state charged to capacitor C2, and transistors P5 and N5 are off and transistors P6 and N6 are on, so that node Q23 is on. ) Maintains the previous state charged to capacitor C3, and transistors P7 and P8 are on and transistors N7 and N8 are off, so node Q24 is the previous state charged to capacitor C4. Since the transistors P9 and P10 are turned off and on, and the transistors N9 and N10 are turned off and on, the node Q25 maintains the previous state charged in the capacitor C5.

Referring to the point i of FIG. 8, the clock signal CK is in the "high" state, and the state of the MOS transistor is as follows.

The transistors P1 and P2 are turned on and off, respectively, and the transistors N1 and N2 are turned on and off, respectively, so that the node Q21 maintains the previous state charged in the capacitor C1, and the transistor ( Since P3 and P4 are turned off, and transistors N3 and N4 are turned on, node Q22 is charged "low" to capacitor C2, and transistors P5 and P6 are turned on and off, respectively. Since the transistors N5 and N6 are turned on and off, respectively, the node Q23 maintains the previous state charged in the capacitor C3, and the transistors P7 and N7 are on and the transistors P8 and N8. Node Q24 remains in the previous state charged to capacitor C4, transistors P9 and P10 are off, and transistors N9 and N10 are on, so node Q25 is the capacitor. The previous state charged in (C5) is maintained.

Referring to point j of FIG. 8, the clock signal CK is in the "low" state, and the state of the MOS transistor is as follows.

Since transistors P1 and P2 are on and transistors N1 and N2 are off, node Q21 retains the previous state charged to capacitor C1, and transistors P3 and P4 are off, respectively. And the transistors N3 and N4 are turned off and on, respectively, so that the node Q22 maintains the previous state charged in the capacitor C2, and the transistors P5 and P6 are on and the transistors N5 and N6. Node Q23 is charged high to capacitor C3, transistors P7 and P8 are turned off and on, and transistors N7 and N8 are turned off and on, respectively. Node Q24 maintains the previous state charged to capacitor C4, and transistors P9 and N9 are off and transistors P10 and N10 are on, so node Q25 is charged to capacitor C5. The old state is maintained.

Referring to point k of FIG. 8, the clock signal CK is in the "high" state, and the state of the MOS transistor is as follows.

Since transistors P1 and N1 are on and transistors P2 and N2 are off, node Q21 remains the previous state charged in capacitor C1, and transistors P3 and P4 are off and transistor N3. N4 is turned on so that node Q22 maintains the previous state charged to capacitor C2, and transistors P5 and P6 are on and off, respectively, and transistors N5 and N6 are on, respectively. , The node Q23 maintains the previous state charged to the capacitor C3, the transistors P7 and P8 are turned off, and the transistors N7 and N8 are turned on, so that the node Q24 is turned off. The capacitor C4 is charged "low", and the transistors P9 and N9 are turned on and the transistors P10 and N10 are turned off, so that the node Q25 maintains the previous state charged to the capacitor C5. .

Referring to the point l of FIG. 8, the clock signal CK is in the "low" state, and the state of the MOS transistor is as follows.

Since transistors P1, P2, N1, and N2 are turned off, on, off, and on, respectively, node Q21 maintains the previous state charged to capacitor C1, and transistors P3, P4, N3, and N4. Nodes are turned off, on, off, and on, respectively, so that node Q22 maintains the previous state charged in capacitor C2, and transistors P5, P6, N5, and N6 are on, on, off, and off states, respectively. Node Q23 maintains the previous state charged to capacitor C3, and transistors P7, P8, N7, and N8 are turned off, on, off, and on, respectively, so that node Q24 The previous state charged in C4 is maintained, and the transistors P9, P10, N9, and N10 are in the on, on, off, and off states, respectively, so that the node Q25 is charged to the capacitor C5 "high".

Referring to the point m of FIG. 8, the clock signal CK is in the "high" state, and the state of the MOS transistor is as follows.

The transistors P1, P2, N1, and N2 are turned off, off, on, and on, respectively, so that the node Q21 is charged low to the capacitor C1, and the transistors P3, P4, N3, and N4 are charged. Since the respective states are on, off, on, and off, the note Q22 maintains the previous state charged in the capacitor C2, and the transistors P5, P6, N5, and N6 are on, off, on, and off, respectively. Therefore, the node Q23 maintains the previous state charged to the capacitor C3, and the transistors P7, P8, N7, and N8 are in the off, off, on, and on states, respectively, and the node Q24 is connected to the capacitor C4. Since the transistors P9, P10, N9, and N10 are in the on, off, on, and off states, respectively, the node Q25 maintains the previous state charged in the capacitor C5.

8, the clock signal CK is in the "low" state, and the state of the MOS transistor is as follows.

Since transistors P1, P2, N1, and N2 are turned off, on, off, and on, respectively, node Q21 maintains the previous state charged to capacitor C1, and transistors P3, P4, N3, and N4. Are turned on, on, off, and off, respectively, so that node Q22 is charged "high" to capacitor C2, and transistors P5, P6, N5, and N6 are off, on, off, and on, respectively. Therefore, the node Q23 maintains the previous state charged in the capacitor C3, and the transistors P7, P8, N7, and N8 are turned off, on, off, and on, respectively, so that the node Q24 is the capacitor C4. ), And transistors P9, P10, N9, and N10 are turned on, on, off, and off, respectively, so that node Q25 has capacitor C5 charged to capacitor C5. Maintain state.

Referring to the point o of FIG. 8, the clock signal CK is in the "high" state, and the state of the MOS transistor is as follows.

Since transistors P1, P2, N1, and N2 are turned off, off, on, and on, respectively, node Q21 maintains the previous state charged in capacitor C1, and transistors P3, P4, N3, and N4. Are in the on, off, on, and off states, respectively, so that the node C22 maintains the previous state charged in the capacitor C2, and the transistors P5, P6, N5, and 6 are in the off, off, on, and on states, respectively. Node Q23 is charged low to capacitor C3, and transistors P7, P8, N7, and N8 are on, off, on, and off, respectively, so node Q24 is capacitor C4. Since the transistors P9, P10, N9, and N10 are turned on, off, on, and off, respectively, the node Q25 maintains the previous state charged to the capacitor C5.

Referring to the point p of FIG. 8, the clock signal CK is in the "low" state, and the state of the MOS transistor is as follows.

Since transistors P1, P2, N1, and N2 are turned off, on, off, and on, respectively, node Q21 maintains the previous state charged to capacitor C1, and transistors P3, P4, N3, and N4. Are turned on, on, off, and off, respectively, so that node Q22 maintains the previous state charged to capacitor C2, and transistors P5, P6, N5, and N6 are off, on, off, and on, respectively. Node Q23 maintains the previous state charged to capacitor C3, and transistors P7, P8, N7, and N8 are on, on, off, and off, respectively, so that node Q24 is capacitor C4. ), And transistors P9, P10, N9, and N10 are turned off, on, off, and on, respectively, so that node Q25 maintains the previous state charged to capacitor C5.

When the variable dynamic divider of the present invention operates as the divider 4 in which the control signals DS1 and DS2 are in the "low" and "high" states, the variable dynamic divider will be described with reference to the waveform diagram of FIG.

Transistors P1, P2, and N1 in the state where the preset signal PS is input as "high", the control signals DS1 and DS2 are input as "low" and "high", and the clock signal CK is input as "high". , N2, P11, N11, and N12 are turned on, off, on, off, on, off, and off, respectively, so that the node Q21 is initially charged to the capacitor C1 in a "high" state, and the transistor ( Since P3, P4, N3, N4, N13, and N14 are turned off, off, on, on, on, on, respectively, node Q22 is initially charged to capacitor C2 in a low state, and the transistor (P5, P6, N5, N6, N12, N13, N14) are turned on, off, on, off, off, on, and on, respectively, so that node Q23 is initially in the "high" state of capacitor C3. And the transistors P7, P8, N7, and N8 are turned off, off, on, and on, respectively, so that the node Q24 is initially charged to the capacitor c4 in a "low" state, and the transistor P9 , P10, N9, N10, N18, N19, N20, N21) are on and five respectively Nodes Q25 are initially charged to capacitor C5 in a low state because they are turned on, off, on, off, off, and on.

In this initial state, if the preset signal PS is in the "low" state and the clock signal CK is periodically input at this time, the state of each MOS transistor at point a of FIG. 9 is as follows.

Since transistors P1, P2, N1, and N2 are turned on, on, off, and off, respectively, node Q maintains the previous state charged in capacitor C1, and transistors P3, P4, N3, N4, N13 is off, on, off, on, on and on, respectively, so node Q22 maintains the previous state charged to capacitor C2, and transistors P5, P6, N5, and N6 are on and on, respectively. , Off, and off, so that the node Q23 maintains the previous state charged in the capacitor C3, and the transistors P7, P8, N7, and N8 are turned off, on, off, and on, respectively. Q24 maintains the previous state charged to capacitor C4, and transistors P9, P10, N9, and N10 are turned on, on, off, and off, respectively, so that node Q25 is charged to capacitor C5. Keep the previous state.

Referring to point b of FIG. 9, the clock signal CK is in the "low" state, and the state of the MOS transistor is as follows.

Since transistors P1, P2, N1, and N2 are turned off, on, off, and on, respectively, node Q21 maintains the previous state charged in capacitor C1, and transistors P3, P4, N3, N4, N13 is turned off, on, off, on and on, respectively, so node Q22 maintains the previous state charged in capacitor C2, and transistors P5, P6, N5, and N6 are on, on, The node Q23 maintains the previous state charged to the capacitor C3 because the states are turned off and off, and the transistors Q24 are turned off, on, off, and on, respectively, because the transistors P7, P8, N7, and N8 are turned off. ) Maintains the previous state charged in capacitor C4, and transistors P9, P10, N9, and N10 are in the on, on, off, and off states, respectively, so that node Q25 is " high " Is charged.

Referring to point c of FIG. 9, the clock signal CK is in a high state, and the state of the MOS transistor is as follows.

Since transistors P1, P2, N1, and N2 are turned off, off, on, and on, respectively, node Q21 is charged to capacitor C1 "low", and transistors P3, P4, N3, N4, and N13. ) Are turned on, off, on, off, and off, respectively, so that node Q22 maintains the previous state charged to capacitor C2, and transistors P5, P6, N5, and N6 are on, off, The node Q23 maintains the previous state output to the capacitor C3 because the states are turned on and off, and the transistors Q24 are turned off, on, on, and on, because the transistors P7, P8, N7, and N8 are turned off, on, and on, respectively. Maintains the previous state charged in the capacitor C4, and the transistors P9, P10, N9, and N10 are turned on, off, on, and off, respectively, so that the node Q25 returns the previous state to the capacitor C5. Keep it.

Referring to point d of FIG. 9, the clock signal CK is in the "low" state, and the MOS transistor is as follows.

Since the transistors P1, P2, N1, and N2 are turned off, on, off, and on, respectively, the transistors P1, P2, N1, and N2 remain in the previous state charged in the node Q21 SMS capacitor C1, and the transistors P3, P4, N3, N4, N13 turns on, on, off, off, and off, respectively, so node Q22 charges capacitor C2 "high", and transistors P5, P6, N5, and N6 are off, on, off, respectively. , The node Q23 maintains the previous state charged to the capacitor C3, and the transistors P7, P8, N7, and N8 are turned off, on, off, and on, respectively. Maintains the previous state charged in the capacitor C4, and the transistors P9, P10, N9, and N10 are turned on, on, off, and off, respectively, and thus maintain the previous state charged in the node Q25.

Referring to the point e of FIG. 9, the clock signal CK is in the "high" state, and the state of the MOS transistor is as follows.

Since the transistors P1, P2, N1, and N2 are turned off, off, on, and on, respectively, the node Q21 maintains the previous state charged to the capacitor C1, and the transistors P3, P4, N3, N4, N13 is turned on, off, on, off and off, respectively, so that node Q22 maintains the previous state charged to capacitor C2, and transistors P5, P6, N5, and N6 are off, off, The node Q23 is charged "low" in the capacitor C3 because the states are turned on and on, and the nodes Q24 are turned on, off, on, and off, respectively, because the transistors P7, P8, N7, and N8 are turned on. The previous state charged in the capacitor C4 is maintained, and the transistors P9, P10, N9, and N10 are in the on, off, on, and off states, respectively, so that the node Q25 is charged in the capacitor C5. Keep it.

Referring to the point f of FIG. 9, the clock signal CK is in the "low" state, and the state of the MOS transistor is as follows.

Since transistors P1, P2, N1, and N2 are turned off, on, off, and on, respectively, node Q21 maintains the previous state charged to capacitor C1, and transistors P3, P4, N3, N4, N13 is turned on, on, off, off, and off, respectively, so that node Q22 maintains the previous state charged in capacitor C2, and transistors P5, P6, N5, and N6 are off, on, and off, respectively. The node Q23 maintains the previous state charged to the capacitor C3 because the state is turned off and on, and the transistors Q7, P8, N7, and N8 are turned on, on, off, and off, respectively. Is charged high to capacitor C4, and transistors P9, P10, N9, and N10 are turned off, on, off, and on, respectively, so node Q25 is charged to capacitor C5. Will be maintained.

Looking at the point g of FIG. 9, the clock signal CK is in the "high" state, and the state of the MOS transistor is as follows.

Since the transistors P1, P2, N1, and N2 are turned off, off, on, and on, respectively, the node Q21 maintains the previous state charged to the capacitor C1, and the transistors P3, P4, N3, N4, N13 is turned on, off, on, off and off, respectively, so that node Q22 maintains the previous state charged to capacitor C2, and transistors P5, P6, N5, and N6 are off, off, The node Q23 is kept in the previous state charged to the capacitor C3 because the state is turned on and on, and the transistors Q24 are turned on, off, on, and off, respectively, because the transistors P7, P8, N7, and N8 are turned on, respectively. ) Maintains the previous state charged to capacitor C4, and transistors P9, P10, N9, and N10 are turned off, off, on, and on, respectively, so that node Q25 is " low " To charge.

Referring to the point h of FIG. 9, the clock signal CK is in the "low" state, and the state of the MOS transistor is as follows.

Since transistors P1, P2, N1, and N2 are turned on, on, off, and off, respectively, node Q21 charges capacitor C1 "high", and transistors P3, P4, N3, N4, and N13. ) Are turned off, on, off, on, and on, respectively, so that node Q22 charges low on capacitor C2, and transistors P5, P6, N5, and N6 are on, on, off, and off, respectively. Node Q23 charges capacitor C3 "high", and transistors P7, P8, N7, and N8 are turned off, on, off, and on, respectively. The previous state charged in C4 is maintained, and the transistors P9, P10, N9, and N10 are turned off, on, off, and on, respectively, so that the node Q25 maintains the previous state charged in the capacitor C5. .

Referring to point i of FIG. 9, the clock signal CK is in a "high" state, and the state of the MOS transistor is as follows.

Since transistors P1, P2, N1, and N2 are turned on, off, on, and off, respectively, node Q21 maintains the previous state charged to capacitor C1, and transistors P3, P4, N3, N4, N13 is turned off, off, on, on, and on, respectively, so that node Q22 maintains the previous state charged in capacitor C2, and transistors P5, P6, N5, and N6 are on, off, and respectively. The node Q23 maintains the previous state where the node Q23 is charged to the capacitor C3, and the transistors P7, P8, N7, and N8 are in the off, off, on, and on states, respectively. The capacitor C4 is charged " low ", and the transistors P9, P10, N9, and N10 are turned on, off, on, and off, respectively, so that the node Q25 maintains the previous state charged to the capacitor C5. do.

Referring to point j of FIG. 9, the clock signal CK is in the "low" state, and the state of the MOS transistor is as follows.

Since transistors P1, P2, N1, and N2 are turned off, on, off, and on, respectively, node Q21 maintains the previous state charged to capacitor C1, and transistors P3, P4, N3, and N4. , N13 is in the off, on, off, on, and on states, respectively, so that node Q22 maintains the previous state charged in capacitor C2, and transistors P5, P6, N5, and N6 are on and on, respectively. Node Q23 maintains the previous state charged to capacitor C3, and transistors P7, P8, N7, and N8 are in the off, on, off, and on states, respectively. ) Maintains the previous state charged in capacitor C4, and transistors P9, P10, N9, and N10 are in the on, on, off, and off states, respectively, so that node Q25 is " high " Is charged.

Referring to point k of FIG. 9, the clock signal CK is in a "high" state, and the state of the MOS transistor is as follows.

Since transistors P1, P2, N1, and N2 are turned off, off, on, and on, respectively, node Q21 is charged to capacitor C1 "low", and transistors P3, P4, N3, N4, and N13. ) Are turned on, off, on, off, and off, respectively, so that node Q22 maintains the previous state charged to capacitor C2, and transistors P5, P6, N5, and N6 are on, off, and on, respectively. , The node Q23 maintains the previous state charged to the capacitor C3, and the transistors P7, P8, N7, and N8 are turned off, off, on, on, and in the state, respectively. Maintains the previous state charged in the capacitor C4, and the transistors P9, P10, N9, and N10 are in the on, off, on, and off states, respectively, so that the node Q25 is in the previous state charged in the capacitor C5. Keep it.

Referring to the point l of FIG. 9, the clock signal CK is in the "low" state, and the state of the MOS transistor is as follows.

Since transistors P1, P2, N1, and N2 are turned off, on, off, and on, respectively, node Q21 maintains the previous state charged to capacitor C1, and transistors P3, P4, N3, N4, N13 turns on, on, off, off, and off, respectively, so node Q22 charges capacitor C2 "high", and transistors P5, P6, N5, and N6 are off, on, off, respectively. , The node Q23 maintains the previous state charged to the capacitor C3, and the transistors P7, P8, N7, and N8 are turned off, on, off, and on, respectively, so that the node Q24 is turned on. The previous state charged in the capacitor C4 is maintained, and the transistors P9, P10, N9, and N10 are in the on, on, off, and off states, respectively, so that the node Q25 receives the previous state charged in the capacitor C5. Keep it.

Referring to the point m of FIG. 9, the clock signal CK is in a "high" state, and the state of the MOS transistor is as follows.

Since transistors P1, P2, N1, and N2 are turned off, on, off, and on, respectively, node Q21 maintains the previous state charged to capacitor C1, and transistors P3, P4, N3, N4, N13 is turned on, off, on, off and off, respectively, so that node Q22 maintains the previous state charged to capacitor C2, and transistors P5, P6, N5, and N6 are off, off, Node Q23 charges capacitor C3 "low" because it is on and on, and transistors Q7, P8, N7, and N8 are on, off, on, and off, respectively, so that node Q24 Since the previous state charged in the capacitor C4 is maintained, and the transistors P9, P10, N9, and N10 are turned on, off, on, and off, respectively, the node Q25 receives the previous state charged in the capacitor C5. Keep it.

Referring to point n of FIG. 9, the clock signal CK is in the "low" state, and the state of the MOS transistor is as follows.

Since transistors P1, P2, N1, and N2 are turned off, on, off, and on, node Q21 maintains the previous state charged in capacitor C1, and transistors P3, P4, N3, N4, and N13. ) Are on, on, off, off, and off, respectively, so that node Q22 maintains the previous state charged in capacitor C2, and transistors P5, P6, N5, and N6 are off, on, and off, respectively. , The node Q23 maintains the previous state charged to the capacitor C3, and the transistors P7, P8, N7, and N8 are turned on, on, off, and off, respectively. The capacitor C4 is charged " high " and the transistors P9, P10, N9 and N10 are turned off, on, off and on, respectively, so that the node Q25 maintains the previous state charged to the capacitor C5. do.

When the variable dynamic divider of the present invention operates as the divider 3, the variable dynamic divider will be described in detail with reference to the signal of FIG.

Morse transistors P1, P2, N1, N2, P11 with PS signal " high ", DSI signal " high ", DS2 signal " low " and clock signal CK " high " N11 and N12 are turned on, off, on, off, on, off and on, respectively, so that the node Q21 is initially charged to the capacitor C1 in a "high" state, and the transistors P3, P4, N3, N4, N13, and N15 are turned off, off, on, on, and on, respectively, so that node Q22 is initially charged to capacitor C2 in a "low" state, and transistors P5, P6, N6, N13, N13, and N14 are turned on, off, on, off, on, on, and on, respectively, so that the node Q23 is initially charged to the capacitor C3 in a "high" state, and the transistor P7 , P8, N7, N8 are turned off, off, on, and on, respectively, so that the node Q24 is initially charged to the capacitor C4 in a low state, and the transistors P9, P10, N9, N10, N18, N19, N20, N21) is on, off, on, off, on Node Q25 is initially charged to capacitor C5 in a low state.

In this initial state, if the preset signal PS is in the "low" state, and the clock signal CK is periodically input at this time, the state of the MOS transistor at point a of FIG. 10 is as follows.

Since transistors P1, P2, N1, N2, and N11 are in the on, off, on, and off states, respectively, node Q21 maintains the previous state charged in capacitor C1, and transistors P3, P4, N3, N4) is turned off, off, on, and on, respectively, so that node Q22 maintains the previous state charged in capacitor C2, and transistors P5, P6, N5, N6, and N13 are on, off, and respectively. The nodes Q23 maintain the previous state charged in the capacitor C3 because they are turned on, off, and on, and the transistors P7, P8, N7, and N8 are turned off, off, on, and on, respectively. Q24 maintains the previous state charged to capacitor C4, and transistors P9, P10, N9, and N10 are turned on, off, on, and off, respectively, so that node Q25 is charged to capacitor C5. Keep the previous state.

Referring to point b of FIG. 10, the clock signal CK is in the "low" state, and the state of the MOS transistor is as follows.

The transistors P1, P2, N1, N2, and N11 are turned off, on, off, on, and on, respectively, so that the node Q21 is charged "low" to the capacitor C1, and the transistors P3, P4, N3. , N4 is turned on, on, off, and off, respectively, so that node Q22 is charged high to capacitor C2, and transistors P5, P6, N5, N6, and P13 are off, on, The node Q23 maintains the previous state charged to the capacitor C3 because the states are turned off, on, and off, and the transistors P7, P8, N7, and N8 are off, on, off, and on, respectively. Q24 maintains the previous state charged to capacitor C4, and transistors P9, P10, N9, and N10 are turned on, off, off, and off, respectively, so that node Q25 is " high " "Is charged.

Referring to the point c of FIG. 10, the clock signal CK is in the "high" state, and the state of the MOS transistor is as follows.

Since transistors P1, P2, N1, N2, and N11 are turned off, off, on, on, and off, respectively, node Q21 maintains the previous state charged to capacitor C1, and transistors P3, P4, N3 and N4 are turned on, off, on and off, respectively, so that node Q22 maintains the previous state charged in capacitor C2, and transistors P5, P6, N5, N6, and P13 are off, respectively. Node Q23 charges capacitor C3 "low" because it is in the off, on, on, off state, and transistors P7, P8, N7, and N8 are in off, off, on, and on states, respectively. Q24 maintains the previous state charged in capacitor C4, and transistors P9, P10, N9, and N10 are turned on, off, on, and off, respectively, so that node Q25 charges capacitor C5. Maintain the previous state.

Referring to point d of FIG. 10, the clock signal CK is in the "low" state, and the state of the MOS transistor is as follows.

Since the transistors P1, P2, N1, N2, and N11 are in the off, on, off, on, and on states, the node Q21 maintains the previous state filled with the capacitor C1, and the transistors P3, P4, N3 and N4 are turned on, on, off, and off, respectively, so that node Q22 maintains the previous state charged in capacitor C2, and transistors P5, P6, N5, N6, and P13 are off, respectively. Since the node Q23 is in the on, off, on, and off states, the node Q23 maintains the previous state charged in the capacitor C3, and the transistors P7, P8, N7, and N8 are in the on, on, off, and off states, respectively. Node Q24 charges capacitor C4 "high", and transistors P9, P10, N9, and N10 are turned off, on, off, and on, respectively, so node Q25 charges capacitor C5. Maintain the previous state.

Referring to the point e of FIG. 10, the clock signal CK is in the "high" state, and the state of the MOS transistor is as follows.

Since the transistors P1, P2, N1, N2, and N11 are turned on, off, on, off, and off, respectively, the node Q21 maintains the previous state charged in the capacitor C1, and the transistors P3, P4, N3 and N4 are turned on, off, on, and off, respectively, and thus maintain the previous state charged in node Q22 and node capacitor N2, and transistors P5, P6, N5, N6, and P13 are respectively The node Q23 maintains the previous state charged to the capacitor C3 because the states are off, off, on, on, and off, and the transistors P7, P8, N7, and N8 are on, off, on, and off, respectively. Node Q24 maintains the previous state charged to capacitor C4, and transistors P9, P10, N9, and N10 are turned off, off, on, and on, respectively, so that node Q25 is capacitor C5. ) To "low".

Referring to the point f of FIG. 10, the clock signal CK is in the "low" state, and the state of the MOS transistor is as follows.

Since transistors P1, P2, N1, N2, and N11 are turned on, on, off, off, and off, respectively, node Q21 is charged "high" in capacitor C1, and transistors P3, P4, N3. , N4 is turned off, on, off and on, respectively, so that node Q22 maintains the previous state charged to capacitor C2, and transistors P5, P6, N5, N6, and N13 are off and on, respectively. , Off, on, and off, so the node Q23 maintains the previous state charged in the capacitor C3, and the transistors P7, P8, N7, and N8 are on, on, off, and off, respectively. Node Q24 maintains the previous state charged in capacitor C4, and transistors P9, P10, N9, and N10 are turned off, on, off, and on, respectively, so node Q25 is connected to capacitor C5. Keep the previous state charged.

Referring to point g of FIG. 10, the clock signal CK is in a high state, and the state of the MOS transistor is as follows.

Since the transistors P1, P2, N1, N2, and N11 are turned on, off, on, off, and off, respectively, the node Q21 maintains the previous state charged in the capacitor C1, and the transistors P3, P4, N3 and N4 are turned off, off, on, and on, respectively, so that node Q22 is charged "low" to capacitor C2, and transistors P5, P6, N5, N6, and P13 are on and off, respectively. , On, off, and on, so that node Q23 charges capacitor C3 "high", and transistors P7, P8, N7, and N8 are off, off, on, and on, respectively. Q24 is charged "low" in capacitor C4, and transistors P9, P10, N9, N10 are on, off, on, off states, respectively, so node Q25 is charged to capacitor C5. Keep state.

Referring to the point h of FIG. 10, the clock signal CK is in the "low" state, and the state of the MOS transistor is as follows.

Since transistors P1, P2, N1, N2, and N11 are turned off, on, off, on, and on, respectively, node Q21 is charged to capacitor C1 "low", and transistors P3, P4, N3. N4 is turned on, on, off and off, respectively, so that node Q22 charges capacitor C2 "high", and transistors P5, P6, N5, N6, and N13 are off, on, The node Q23 maintains the previous state charged to the capacitor C3 because the states are turned off, on, and off, and the transistors P7, P8, N7, and N8 are off, on, off, and on, respectively. Q24 maintains the previous state charged to capacitor C4, and transistors P9, P10, N9, and N10 are in the on, on, off, and off states, respectively, so that node Q25 is " high " "Is charged.

Referring to point i of FIG. 10, the clock signal CK is in a high state, and the state of the MOS transistor is as follows.

Since the transistors P1, P2, N1, N2, and N11 are in the off, off, on, on, and on states, the node Q21 maintains the previous state charged in the capacitor C1, and the transistors P3, P4, N3 and N4 are turned on, off, on, and off, respectively, so that node Q22 maintains the previous state charged to capacitor C2, and transistors P5, P6, N5, N6, and P13 are off, respectively. Nodes Q23 are charged low to capacitor C3 because they are turned off, on, on, off, and transistors P7, P8, N7, and N8 are turned on, off, on, and off, respectively. Q24 maintains the previous state charged in capacitor C4, and transistors P9, P10, N9, and N10 are turned on, off, on, and off, respectively, so that node Q25 charges capacitor C5. Maintain the previous state.

Referring to point j of FIG. 10, the clock signal CK is in the "low" state, and the state of the MOS transistor is as follows.

Since transistors P1, P2, N1, N2, and N11 are turned off, on, off, on, and on, respectively, node Q21 maintains the previous state charged in capacitor C1, and transistors P3, P4, N3 and N4 are turned on, on, off, and off, respectively, so that node Q22 maintains the previous state charged to capacitor C2, and transistors P5, P6, N5, N6, and P13 are off and on. , Off, on, and off, so that node Q23 maintains the previous state charged in capacitor C3, and transistors P7, P8, N7, and N8 are on, on, off, and off, respectively. Node Q24 charges capacitor C4 "high", and transistors P9, P10, N9, and N10 are turned off, on, off, and on, respectively, so node Q25 charges capacitor C5. Maintain the previous state.

When the variable dynamic divider of the present invention operates at 2, it will be described in detail with reference to the waveform diagram of FIG.

Preset signal PS is inputted with "high", control signals DS1 and DS2 are input "high", and the MOS transistors P1, P2, N1, N2, when the clock signal CK is input "high". Since P11, N11, and N12 are on, off, on, off, on, off, and on, respectively, node Q21 is initially charged to capacitor C1 in a "high" state, and transistors P3, P4, N3, N4, N13, and N14 are turned off, off, on, on, on, and on, respectively, so that node Q22 is initially charged to capacitor C2 in a low state, and transistors P5 and P6. , N5, N6, P12, P13, and P14 are turned on, off, on, off, on, on, and on, so that the node Q23 is initially charged to the capacitor C3 in a "high" state, and the transistor Since the nodes P24, P8, N7, and N8 are turned off, off, on, and on, respectively, the node Q24 is initially charged to the capacitor C4 in a low state, and the transistors P9, P10, N9, N10, N18, N19, N20, N21) are on, off, on, and oh respectively , On, off, on, since the on-state node (Q25) is a capacitor (C5), initially charged to the "low" state.

In this initial state, if the preset signal PS is in the "low" state and the clock signal CK is periodically input at this time, the state of each MOS transistor at point a in FIG. 11 is as follows.

Since the transistors P1, P2, N1, N2, N11, N12, and P11 are on, off, on, off, off, on, and off, respectively, the node Q21 maintains the previous state charged to the capacitor C1. Since the transistors P3, P4, N3, N4, N13, and N14 are turned off, off, on, on, off, and on, respectively, the node Q22 maintains the previous state charged in the capacitor C2, The transistors P5, P6, N5, N6, P12, P13, and P14 are in the on, off, on, off, on, on, and off states, respectively, so that the node Q23 maintains the previous state charged in the capacitor C3. Since the transistors P7, P8, N7, and N8 are in the off, off, on, and on states, the node Q24 maintains the previous state charged in the capacitor C4, and the transistors P9, P10, N9, and N10. N18, N19, N20, and N21 are in an on, off, on, off, off, off, on, and on state, so that the node Q25 maintains the previous state charged in the capacitor C5.

Referring to point b of FIG. 11, the clock signal CK is in the "low" state, and the state of the MOS transistor is as follows.

The transistors P1, P2, N1, N2, N11, and N12 are turned off, on, off, on, on, and on, respectively, so that the node Q21 is charged "low" in the capacitor C1, and the transistor P3 , P4, N3, N4, N13, and N14 are turned on, on, off, off, off, and on, respectively, so that node Q22 is charged "high" to capacitor C2, and transistors P5, P6, N5, N6, P12, and P13 are on, on, off, off, on, and on, respectively, so that node Q23 maintains the previous state charged to capacitor C3, and transistors P7, P8, N7, N8) is turned off, on, off, and on, respectively, so that node Q24 maintains the previous state charged in capacitor C4, and transistors P9, P10, N9, N19, N20, and N21 are on, The node Q25 is charged "high" to the capacitor C5 because it is turned on, off, off, off, on, and on.

Referring to point c of FIG. 11, the clock signal CK is in a high state, and the state of the MOS transistor is as follows.

Since the transistors P1, P2, N1, N2, N11, and N12 are turned off, off, on, on, on, on, respectively, the node Q21 maintains the previous state charged in the capacitor C1, and the transistor ( Since P3, P4, N3, N4, N13, and N14 are on, on, off, on, off, and on, respectively, the node Q22 maintains the previous state charged to the capacitor C2, and the transistors P5, Since P6, N5, N6, P12, and P13 are turned off, off, on, on, on, and on, respectively, the node Q23 is charged "low" in the capacitor C3, and the transistors P7, P8, and N7. , N8 is on, off, on, off, and state, respectively, so that node Q24 maintains the previous state charged in capacitor C4, and transistors P9, P10, N9, N19, N20, and N21 are respectively The node Q25 maintains the previous state charged in the capacitor C5 since the state is on, off, on, off, off, on, and on.

Referring to point d of FIG. 11, the clock signal CK is in the "low" state, and the state of the MOS transistor is as follows.

The transistors P1, P2, N1, N2, N11, and N12 are turned on, on, off, off, off, and on, respectively, so that the node Q21 is charged "high" in the capacitor C1, and the transistor P3 , P4, N3, N4, N13, and N14 are turned off, on, off, on, on, and on, respectively, so that node Q22 is charged "low" in capacitor C2, and transistors P5, P6, N5, N6, P12, and P13 are turned on, on, off, off, on, and on, respectively, so that node Q23 is charged high to capacitor C3, and transistors P7, P8, N7, and N8. ) Are on, on, off, and off, respectively, so that node Q24 is charged "high" to capacitor C4, and transistors P9, P10, N9, N19, N20, and N21 are off, on, The node Q25 is charged "low" to the capacitor C5 because it is turned off, on, on, and on.

Looking at the point e of FIG. 11, the clock signal CK is in the "high" state, and the state of the MOS transistor is as follows.

Since the transistors P1, P2, N1, N2, N11, and N12 are turned on, off, on, off, off, and on, respectively, the node Q21 maintains the previous state charged in the capacitor C1. Since P3, P4, N3, N4, N13, and N14 are turned off, off, on, on, on, and on, respectively, the node Q22 maintains the previous state charged to the capacitor C2, and the transistors P5, Since P6, N5, N6, P12, and P13 are turned on, off, on, off, on, and on, respectively, the node Q23 maintains the previous state charged to the capacitor C3, and the transistors P7, P8. , N7, N8 are turned off, off, on, and on, respectively, so that node Q24 is charged "low" to capacitor C4, and transistors P9, P10, N9, N19, N20, and N21 are respectively The node Q25 maintains the previous state charged in the capacitor C5 since the state is on, off, on, off, off, on, and on.

Referring to the point f of FIG. 11, the clock signal CK is in the "low" state, and the state of the MOS transistor is as follows.

Since transistors P1, P2, N1, N2, N11, and N12 are turned off, on, off, on, on, on, respectively, node Q21 is charged to capacitor C1 "low", and transistors P3, Since P4, N3, N4, N13, and N14 are turned on, on, off, off, off, and on, respectively, node Q22 charges capacitor C2 "high", and transistors P5, P6, and N5. , N6, N12, and N13 are turned off, on, off, on, on, and off, respectively, so that node Q23 maintains the previous state charged to capacitor C3, and transistors P7, P8, N7, and N8. ) Are turned off, on, off and on, respectively, so that node Q24 maintains the previous state charged in capacitor C4, and transistors P9, P10, N9, N10, N19, N20, and N21 are on, respectively. Node Q25 is charged to capacitor C5 "high" because it is in the on, off, off, off, on, on state.

Looking at the point g of FIG. 11, the clock signal CK is in the "high" state, and the state of the MOS transistor is as follows.

Since the transistors P1, P2, N1, N2, N11, and N12 are turned off, off, on, on, on, on, respectively, the node Q21 maintains the previous state charged in the capacitor C1, and the transistor ( Since P3, P4, N3, N4, N13, and N14 are on, off, on, off, off, and on, respectively, node Q22 maintains the previous state charged to capacitor C2, and transistors P5, Since P6, N5, N6, N12, and N13 are turned off, off, on, on, on, and off, respectively, node Q23 is charged to capacitor C3 "low", and transistors P7, P8, and N7. , N8 is turned off, off, on, and on, respectively, so that node Q24 maintains the previous state charged in capacitor C4, and transistors P9, P10, N9, N10, N19, N20, and N21 The nodes Q25 maintain the previous state charged in the capacitor C5 because they become on, off, on, off, off, on, and on states, respectively.

Looking at the point h of FIG. 11, the clock signal CK is in the "low" state, and the state of the MOS transistor is as follows.

The transistors P1, P2, N1, N2, N11, and N12 are turned on, on, off, off, off, and on, respectively, so that the node Q21 is charged "high" in the capacitor C1, and the transistor P3 , P4, N3, N4, N13, and N14 are turned off, on, off, on, on, and on, respectively, so that node Q22 is " low " charged to capacitor C2, and transistors P5, P6, and N5. , N6, N12, N13 are turned on, on, off, off, off, and on, respectively, so that node Q23 is charged to capacitor C3 "high" and transistors P7, P8, N7, and N8. Nodes are turned on, on, off, and off, respectively, so that node Q24 is charged "high" in capacitor C4, and transistors P9, P10, N9, N10, N19, N20, and N21 are off and on, respectively. Nodes are turned off, on, on, and on, and thus the node Q25 is charged low to the capacitor C5.

An example in which the variable dynamic divider circuit of the present invention operating as described above is used as a clock divider circuit of a high frequency input terminal in a mode of a MOS integrated circuit such as a microcomputer or the like is shown in FIG.

The clock divider circuit of the oscillator to which a high frequency is input is comprised of the high frequency input terminal 100, the amplifier 200, and the variable dynamic divider circuit 300 of this invention. This circuit starts from the state in which the preset signal PS1 is input in the "high" state in the initial state.

Hereinafter, with reference to Figure 12 of the accompanying drawings, the operation, the effect will be described.

The clock signal CK is output in a "high" state when the preset PS1 signal is input "high", and then a peak to peak voltage (Vpp) is about 500 mV at the high frequency input terminal 100. When a high frequency of 100 MHz is input, and the preset signal PS1 is brought to a "low" state, the voltage Vpp is amplified by the amplifier 200 and a signal of a complete waveform is input to the clock signal CK. Lose. When the clock signal CK is input to the variable dynamic divider 300 of the present invention, the clock signal CK divides a high frequency signal to provide a clock signal to each part of the MOS integrated circuit.

As described above, the variable dynamic divider circuit of the present invention can generate a plurality of signals having different division ratios, phases, and dutys in one divider circuit, and can divide a high frequency signal (100 MHz or more). In addition, due to the characteristics of the dynamic circuit, the operation speed is faster than that of the conventional static divider circuit, and the circuit configuration is simpler, thereby achieving high integration of the MOS integrated circuit.

This feature is shown in Table 1 in more detail compared to the conventional static divider.

TABLE 1

Claims (3)

Receives a high frequency clock signal and a split control signal that are periodically applied from the outside as a common signal at the gate stage, and repeatedly performs the on / off operation to temporarily store data in the capacitors to maintain a constant logic level. First to fifth output means configured in parallel in a cell type; Divider 5, divider by receiving a plurality of control signals according to the division ratio determined from the peripheral circuit in accordance with the signal output from the first to fifth output means as a common control signal of the gate stage, respectively A variable dynamic divider circuit, comprising: divider control means for dividing and operating into four, divider 3, and divider 2 circuits. The method of claim 1, wherein the output means connects the first conductivity-type MOS transistor P2 and the second conductivity-type MOS transistor N1 for inputting a high frequency clock signal CK to a gate, First output means for connecting a first conductivity type MOS transistor (P1) and a second conductivity type MOS transistor (N2) in series with each of the transistors; A first conductive MOS transistor P4 and a second conductive MOS transistor N3 for inputting the high frequency clock signal CK to a gate are connected to a node Q22, and a first conductive MOS transistor is connected to each transistor. Second output means connected to a transistor P3 and the second conductivity-type MOS transistor N4 in series, and having a gate end thereof connected to a node Q21 of the first output means; A first conductive MOS transistor P6 and a second conductive MOS transistor N5 for inputting the high frequency clock signal CK to a gate are connected to a node Q23, and a first conductive MOS transistor is connected to each transistor. Third output means connected with a transistor P5 in series with the second conductivity-type MOS transistor N6, and a gate end thereof connected to a node Q22 of the second output means; The first conductive MOS transistor P8 and the first conductive MOS transistor N7 having the high frequency clock signal CK input to the gate are connected to the node Q24, and the first conductive MOS transistor is connected to each transistor. Fourth output means connected to a transistor P7 and a second conductivity-type MOS transistor N8 in series, and having a gate end thereof connected to a node Q23 of the third output means; The first conductive MOS transistor P10 and the second conductive MOS transistor N9 having the high frequency clock signal CK input to a gate are connected to the node Q25, and the first conductive MOS transistor is connected to each transistor. After the transistor P9 and the second conductivity-type MOS transistor N10 are connected in series, a fifth output means having a gate terminal connected to the node Q24 of the fourth output means, respectively, is provided. Variable dynamic divider circuit. 3. The divider control means according to claim 1 or 2, wherein the divider control means inputs a second conductivity-type MOS transistor N13 and a control signal DS2 connected to a node Q21 of the first output means to receive a signal. Third divider control means having a second conductive MOS transistor N14 connected in series and having a drain connected to the node Q22 of the second output means in series; The first conductivity-type MOS transistor P13 connected to the node Q22 of the second output means and the first conductivity-type MOS transistor P12 for inputting the inverted signal of the control DS1 are connected in series to provide a first conductivity. First divider control means having a drain of the type MOS transistor P13 connected in parallel to a node Q23 of the third output means; The second conductive MOS transistor N12 connected to the node Q25 of the fifth output means, the transistor N11 and the second conductive MOS transistor N12 that receives the control signal DS1 in series, are connected in series to each other. Second divider control means having a drain of the MOS transistor N11 connected in parallel to a node Q21 of the first output means; The second conductivity-type MOS transistor N21 connected to the node Q24 of the fourth output means as a second conductive-type MOS transistor N19 to which a signal is input and the control signal DS2 is connected to the ground. And a drain of the second conductivity-type MOS transistor N19 and the second conductivity-type MOS transistor N19 connected in series between the second conductivity-type MOS transistors N19 and N21 as inputs. And a fourth divider control means connected in parallel to the node (Q25) of the fifth output means.