KR940007239B1 - Semiconductor integrated circuit device and method of testing the same - Google Patents

Abstract

No content.

Description

Semiconductor integrated circuit device and inspection method

1 is a block diagram of an embodiment of the present invention.

2 is a circuit diagram of an important part.

3A and 3B are schematic cross-sectional views showing the state of charge gain and charge loss of a memory cell.

4A to 4D are partial circuit diagrams of a memory cell for explaining each method of checking a charge gain and a charge loss.

5 is a cross-sectional view showing a configuration of an EPROM to which the present invention is applied.

6 is a cross-sectional view showing the sealing shape of the EPROM to which the present invention is applied.

7 and 8 are partial circuit diagrams for explaining another embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, in particular, as a PROM (Programmable Read Only Memory), to a semiconductor memory device and a test method thereof most suitable.

The following method is considered as a test method of the data retention defect of EPROM (Erasable and Programmable ROM). First, by storing data (injecting charge) in all bits of the memory, each bit is set to "0" (all "0"). For example, this is left at a high temperature of 150 degrees C. Thereafter, by calling all bits, it is detected that data "0" has been changed to data "1" (state in which no charge is injected or accumulated). This detects a bad bit. The principle of this method is as follows.

It is assumed that a defect occurs in each insulating film between the EPROM substrate and the floating gate or between the floating gate and the control gate. The charges (positive charges in the case of N-channel MOSFETs) implanted (accumulated) in the floating gate by storage are left at a high temperature, and are transferred to the control gate or other sites through the above defects. As a result, the charges are lost (disposed), so that the defective memory cell is changed into a state in which no memory is performed.

This method is effective for an EPROM capable of erasing stored information by irradiating ultraviolet rays or the like even after encapsulation. However, it is impossible to use this method as it is for the recently proposed OTP (One Time Programable) type EPROM. In the OTP type EPROM, the EPROM chip is packaged by plastic or the like to simplify the product structure and lower the price. For this reason, when the memory is stored for an EPROM element, which is normally sealed in a package, it cannot be erased. Therefore, it is not possible to adopt the above-described method on the premise of storing all the bits in the package.

For the above reasons, the OTP type EPROM requires another inspection method, for example, the above inspection in a wafer state, erasing with ultraviolet rays, and then sealing. However, since some of the data retention defects of the EPROM occur in the sealing step, it is preferable to perform the inspection after sealing.

Examples of OTP-type EPROMs include HN482764 p-3, which is published in Hitachi, Japan, May 1984, HITACHI IC MEMORY DATA BOOK, p263.

An object of the present invention is to provide a programmable semiconductor memory device represented by an OTP type EPROM that enables inspection of data retention failure.

Another object of the present invention is to provide a method for inspecting a semiconductor memory device which can easily inspect a data retention defect of a programmable semiconductor memory device, which is typical of OTP type EPROMs.

Another object of the present invention is to provide a method for inspecting a defect of a memory cell of a semiconductor memory device for storing information by injecting electric charges without injecting electric charges into a memory cell having no defects.

Another object of the present invention is to provide a semiconductor memory device suitable for performing the above inspection. Another object of the present invention is to provide a semiconductor memory device in which an address terminal is used for defect inspection of a memory cell.

The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.

In this application, when outlined briefly among the invention disclosed, it is as follows. The PROM is left standing while the data line is held at a low level potential and a voltage is applied to the word line. As a result, inspection of a defective memory cell due to the function of the insulating film between the substrate and the floating gate and between the floating gate and the control gate can be realized without storing information in each memory cell.

In addition, a stress applying step of aging while maintaining the data line at a low level potential and applying a storage voltage to the word line, and a memory cell having a high threshold voltage The inspection step includes a step of inspecting (charge and personal inspection) and a step of inspecting (charge and loss inspection) of a memory cell having a low threshold voltage. This makes it possible to check for defects in the memory cells without storing them in each memory cell. This enables inspection of the PROM, thereby improving the reliability of this kind of PROM.

FIG. 1 shows an embodiment in which the present invention is applied to an OTP type EPROM. Memory cells MC are arranged in a row and form a memory array. In the memory array, the memory cells MC are arranged in correspondence with the intersection of the word line WL extending in the row state and the data line DL extending in the column state. In the periphery of the memory array, an address control circuit AC and peripheral circuits provided according to the present invention, i.e., X-decoder X-DCR, Y-decoder Y-DCR, and X-address buffer X-ADB. , A Y-address buffer Y-ADB, a sense amplifier SA, a data input buffer DIB, a data output buffer DOB and a memory circuit, W are disposed.

The memory cell MC is an N channel MOSFET QM having a floating gate 4 and a control gate 6, as shown in FIG. The MOSFET QM is formed around the semiconductor substrate 1, which is made of P-type silicon single crystal. The floating gate electrode 4 and the control gate electrode 6 are, for example, a polycrystalline silicon film. The control electrode 6 is used as the word line WL. The first and second gate insulating films 3 and 5 become a silicon oxide film. The oxide films 3 and 5 are formed by thermal oxidation on the surfaces of the substrate 1 and the floating gate electrode 4, respectively. The insulating film 7 is a silicon oxide film formed by thermal oxidation of the control gate electrode 6. The N ⁺ type semiconductor region 8, which is a source or drain region, is formed on the gate electrodes 4 and 6 by self-alignment. In one N ⁺ type region, a data line DL which becomes aluminum wiring 10 through a contact hole formed in an insulating film, for example, a phosphosilicate glas film 9 Connected. The other N ⁺ type region extends in the same direction as the word line and is used as a wiring for supplying the ground potential GND to the memory cell MC. And 2 is a field oxide film.

The insulating film which covers the floating gate 4 which accumulates electric charge as information, especially the insulating film 3 between the board | substrate 1 and the floating gate 4, and the insulating film 5 between the floating gate 4 and the control gate 6 should not have a defect. Through the defect, the charge of the floating gate 4 is counted to the substrate 1 or the control gate 6.

The EPROM having the above structure is sealed in a plastic package as shown in FIG. In other words, the EPROM chip 11 mounted on the tab 12 by silver paste 13 is molded by plastic resin 16. 14 is lead And 15 are bonding wires. The tab 125, the lead 14, the bonding wire 15, and the resin 16 are known materials. Resin 16 is black and is opaque also to ultraviolet rays. Therefore, in this OTP type EPROM, the electric charge accumulated in the memory cell transistor QM cannot be released. That is, once information is stored, it cannot be erased and stored again.

Reuse of plastic packages is effective for reducing the manufacturing cost of devices. Most of EPROMs are used only once. Therefore, even the EPROM which cannot be erased and stored again has a wide range of use.

가 인가된다.워드선 w1에 높은 전압, 즉, 기억 전압 Vpp를 인가할때, 바꾸어 말하면, 기억할때와 스트레스 인가공정(다음에 기술함)에 있어서, 신호

는 로우·레벨로 된다. 호출할때와, 챠지·게인(charge gain)검사 공정 및 챠지 로스(charge lose)검사 공정시, 신호

는 하이레벨로 된다. 저항 R는, 예를들면, 다결정 실리콘막으로 되어, 비교적 높은 저항치를 갖는다. X어드레스 버퍼 X-ADB는, X 어드레스 단자XA0∼XAn를 통해서,IC의 외부에서, 외부 어드레스 신호를 받아, 여기에서, 내부 상보(相補)어드레스를 만든다. X데코우더 DCR에 X어드레스 버터 X-ADB에서 내부 상보 어드레스 신호가 송출된다. X데코우더 X-DCR는, 내부 상보 어드레스 신호에 대응하는 워드선 WL를 선택한다. X어드레스 버퍼 X-ADB와 기억회로 W은, 주지의 회로에 의해서 구성된다. X데코우더 X-DCR의 구성은 다음에 기술한다.One end of the word line WL serving as the control gate 6 of the memory cell MC is connected to an X decoder X-DCR as a word line selecting means via a deflation type N channel MOSFET QD1. The other end of the word line WL is connected via the resistor R to the memory circuit W for applying the storage voltage Vpp (e.g., 12, 5V) to the word line WL and the data line DL at the time of storage. A write enable signal, which is an internal memory control signal formed by a program signal from the outside (not shown), is provided at the gate electrode of the MOSFET QD1

When a high voltage is applied to the word line w1, i.e., the storage voltage Vpp, in other words, when the memory and in the stress application process (described below), the signal is applied.

Becomes the low level. Signals during calls and during charge gain check and charge lose check

Becomes high level. The resistor R becomes a polycrystalline silicon film, for example, and has a relatively high resistance value. The X address buffer X-ADB receives an external address signal from the outside of the IC via the X address terminals XA0 to XAn to form an internal complementary address. The internal complementary address signal is sent from the X address butter X-ADB to the X decoder DCR. The X decoder X-DCR selects the word line WL corresponding to the internal complementary address signal. The X address buffer X-ADB and the memory circuit W are constituted by known circuits. The configuration of the X decoder X-DCR is described next.

The data line DL is connected to the sense amplifier SA, the input buffer circuit DIB, and the output buffer circuit DOB through a switch element SW which is an N channel MOSFET. The input and output circuits DIB and COB are connected to data terminals I / O _{0 to} I / O ₇ . The input or output circuit DIB or DOB inputs or outputs data through the data terminals I / O _{0 to} I / O ₇ in accordance with a predetermined internal timing signal. In practice, the sense amplifier SA data input and output buffers DIB and DOB are provided in the number corresponding to each of the terminals I / O _{0 to} I / O ₇ . The gate electrode of the selection switch element SW is connected to the Y selection line YL. One of the Y select lines YL is connected to the Y decoder Y-DCR via the N-channel MOSFET QD2 of the deflectin type. The other end of the Y select line YL is connected to the memory circuit W through the resistor R. The address buffer Y-ADB as the data line selecting means receives an external address signal from the outside of the IC via the Y address terminals YA0 to YAn, and forms an internal complementary address signal here. The internal complementary address signal is sent from the Y address buffer A-ADB to the Y decoder Y-DCR. The Y decoder Y-DCR conducts the switch element SW corresponding to the internal complementary address signal. As a result, the selected data line DL is connected to the sense amplifier SA or the input circuit DIB. Since the configuration of the sense amplifier SA, the input circuit DIB, the output circuit DOB, the Y decoder Y-DCR and the Y address buffer Y-ADB may be a known circuit, the description thereof is omitted.

According to the present invention, the address control circuit AC is connected to two terminals of the X address terminals XA0 to XAn, for example, terminals XA0 and XA1. The output of the address control circuit AC is sent to the X decoder X-DCR. The address control circuit AC is for controlling the potential of the word line WL in the inspection process according to the present invention.

The details of the X address decoder X-DCR and the address control circuit AC are shown in FIG.

列) 접속된 P찬넬 MOSFET Q9∼Q13과 직열접속된 N찬넬 MOSFET Q14∼Q18으로 되는 NAND게이트 회로와, P찬넬 MOSFET Q7 및 N찬넬 MOSFET Q8으로 되는 인버어터(inverter)회로를 갖는다. MOSFET Q9∼Q18의 게이트 전극에는, X어드레스 버퍼 X-ADB에서 송출된 상보 어드레스 신호중 사전에 정해진 신호가 인가된다. MOSFETQ9∼Q13과 병열 접속된 P찬넬 MOSFET Q19가 마련된다. MOSFET Q14∼Q18과 직열 접속된 N찬넬 MOSFET Q22가 마련된다. 또, MOSFET Q9∼Q13과 전원전압 Vcc와의 사이에, P찬넬 MOSFET Q20이 마련된다. 또, NAND 게이트 회로의 출력단자와 접지전원 GND와의 사이에, N찬넬 MOSFET Q21이 마련된다. 어드레스 제어회로 AC의 제1의 회로 AC1(다음에 기술한다)의 출력이, EPROM Q20,Q21의 게이트 전극에 인가된다.The X decoder X-DCR has a plurality of unit circuits uDCR. Each unit circuit is provided corresponding to each word line WL. Each unit circuit, as shown in FIG.

I) a NAND gate circuit comprising N-channel MOSFETs Q14-Q18 connected in series with a connected P-channel MOSFET Q9-Q13, and an inverter circuit consisting of P-channel MOSFET Q7 and N-channel MOSFET Q8. Predetermined signals from the complementary address signals sent from the X address buffer X-ADB are applied to the gate electrodes of the MOSFETs Q9 to Q18. P-channel MOSFET Q19 connected in parallel with MOSFET Q9-Q13 is provided. An N-channel MOSFET Q22 connected in series with the MOSFETs Q14 to Q18 is provided. The P channel MOSFET Q20 is provided between the MOSFETs Q9 to Q13 and the power supply voltage Vcc. In addition, an N channel MOSFET Q21 is provided between the output terminal of the NAND gate circuit and the ground power supply GND. The output of the first circuit AC1 (to be described later) of the address control circuit AC is applied to the gate electrodes of EPROM Q20 and Q21.

On the other hand, the output of the second circuit AC2 (to be described later) of the address control circuit AC is applied to the gate electrodes of the MOSFETs Q19 and Q22. The MOSFETs Q19 to Q22 are regarded as a switch element controlled by the address control circuit AC or a NOR gate circuit. In the inspection process according to the present invention, the potential of the word line WL becomes a high voltage or a ground voltage by the control circuits AC1 and AC2. The address control circuit AC includes a first circuit AC1 and a second circuit AC2.

The first circuit AC1 has P channel MOSFETs Q1 and Q2, and N channel MOSFET Q3 and CMOS inverter circuits IV1 and IV2. MOSFET Q1 is a load of CMOS inverter circuit IV3 which becomes MOSFET Q2, Q3. An appropriate fixed potential, for example, a power supply potential Vcc (5V) is applied to the gate electrodes of the MOSFETs Q2 and Q3. The source of the P-channel MOSFET Q2 is connected to the X address terminal XA0 via the MOSFET Q1. The output of the inverter circuit IV3 is fed to the respective MOSFETs Q20 and Q21 of each unit circuit uDCR through the inverter circuits IV1 and IV2. The inverter circuit IV3 outputs a high level signal when a voltage higher than 5V is applied to the X address terminal XA0, and in reality a voltage of 7 to 8V or more that is applied to the high level (5V) of the address signal is applied. When the high (5V) or low (OV) level of the normal address signal is applied, the low level signal is output. In this embodiment, the logical threshold voltage of inverter circuit IV3 is set to perform the above operation by the gate voltage Vcc and the sizes of MOSFETs Q1 to Q3. The first circuit AC1 outputs a low level when the normal call operation is performed due to the high or low level (5V or OV) of the address signal. The first circuit AC1 is a process for inspecting a memory cell of an EPROM. The high level is output by identifying the input signal using the X address terminal which is not used.

The second circuit, AC2, becomes the MOSFET Q4, Q5, the N-channel MOSFET Q6, and the CMOS inverter circuit IV5. The second circuit AC2 is the same as the circuit without the inverter circuit IV2 of the first circuit AC1. The source of the MOSFET Q4, that is, the input terminal of the second circuit, is connected to the X address terminal XA1. The CMOS inverter circuit IV5, which is the MOSFETs Q5 and Q6, is the same as the inverter circuit IV3. Therefore, like the first circuit AC1, the second circuit AC2 outputs a low level in the normal call operation and a high level in the inspection process.

The inspection method for the PROM type EPROM having the above structure will be described next.

(1) Stress application process (heating and voltage application process)

The OTP-type EPROM to be inspected is aged at a temperature of 100 to 150 degrees C in a thermostat. In consideration of the heat resistance of plastic resin 16, it is preferable to make temperature mentioned above into 150 degrees C or less.

In order to detect a defect without injecting charges into the memory cell MC without a defect, the following operation is set. That is, a relatively high voltage, for example, a storage voltage Vpp, is applied to the word line WL so that the data line DL is at the ground potential or a potential close thereto. For this purpose, the address control circuit AC is used.

A high voltage is applied to the X address terminal XA0 so that the inverter circuit IV3 outputs a high level signal. In this embodiment, the storage voltage Vpp (12.5V) is applied. This outputs a high level signal from inverter circuit IV3. This high level signal is applied to MOSFETs Q20 and Q21 through inverter circuits IV1 and IV2. As a result, the MOSFET Q20 becomes non-conductive and the MOSFET Q21 conducts.

On the other hand, a low voltage is applied to the X address terminal XA1 so that the inverter circuit IV5 outputs a low level signal. In this embodiment, OV or 5V (ground potential or power source potential) is applied. As a result, a low level signal is output from inverter circuit IV5. This low level signal is inverted by inverter circuit IV4 and applied to MOSFETs Q19 and Q22. As a result, MOSFET Q19 becomes non-conductive and MOSFET Q22 becomes conductive.

의 로우·레벨(OV)가, 스트레스 인가공정의 사이에 인가된다. 한편, 스트레스 인가공정의 사이에, 기억회로 W에서 모든 워드선 WL에, 스트레스 인가를 위한 높은 전압, 예를들면, 기억 전압 Vpp가 인가된다. 따라서, MOSFET QD1이 비도동으로 되는 결과, 각 워드선 WL에, 저항 R을 통해서, 높은전압 Vpp가 인가된다.Therefore, the output of each unit circuit uDCR becomes high level irrespective of the level of the X address signal (ie, complementary address signal). In other words, all outputs of the X decoder X-DCR are at a high level. As a result, the high level signal, for example, 5V is applied to the source of the MOSFET QD1. The write enable signal is provided to the gate electrode of MOSFET QD1.

Low level OV is applied during the stress application process. On the other hand, a high voltage for applying stress, for example, the storage voltage Vpp, is applied to all the word lines WL in the memory circuit W during the stress application process. Therefore, as a result of the MOSFET QD1 becoming non-conducting, a high voltage Vpp is applied to each word line WL through the resistor R.

During the stress application process, all data lines DL are in a non-memory state, that is, in an unselected state. That is, the drain of each memory transistor QM is at or near the ground potential OV (a floating state close to OV).

This is realized by the following method.

Y Decoder Y-DCR turns off all switch elements SW. Alternatively, the discharge MOSFET provided at one end of the data line DL not connected to the switch element SW is conducted before or during the stress application step. Alternatively, the ground potential is supplied to the data line DL through the input buffer circuit DIB at the input / output terminal I / O while all the switch elements are conducted by the Y decoder Y-DCR.

As a result, the MOSFETs QM of all the memory cells MC are in a state where the control gate, the source, and the drain are at the high voltage Vpp, the ground potential GND, and the ground potential GND, or a potential close thereto.

A desired potential, for example, a ground potential, may be applied to the X address terminals XA2 to XAn.

If this aging is continued for several hours and an electric field stress due to the storage voltage Vpp is applied between the control gates, the floating gates, and the substrates of all the memory cells, the following phenomenon occurs in the defective memory cell.

In a memory cell in which the insulating film 3 between the semiconductor substrate 1 and the floating gate 4 is defective as shown in FIG. 3A, electrons (negative charge) on the substrate 1 attracted to the electric field of the control gate 6 leak through the defect and float. Stored in Gate 4. As a result, the threshold voltage Vth of the memory cell is increased (charge / gain) as in the case where so-called storage is performed.

As shown in FIG. 3B, in the memory cell in which a defect occurs in the insulating film 5 between the floating gate 4 and the control gate 6, the positive charge of the control gate 6 is pushed toward the substrate 1, through which the defect Stored at floating gate 4. It is also thought that holes after the electrons in the floating gate 4 attracted to the electric field of the control gate 6 fall into the control gate 6 remain. As a result, the threshold voltage Vth of the memory cell is lowered (charge loss), so that the memory cell becomes a deflation type.

These are poor memory cells, all of which impair the characteristics of the normal EPROM. During or after aging, the presence or absence of these memory cells is checked. A chip having such a memory cell is removed as a defective product.

(2) Charge gain inspection process.

The memory cell whose threshold voltage Vth has risen by the charge gain is the same as that in which the memory is performed. Therefore, the calling method so far is used as it is.

에서 형성된 라이트 인에이블 신호

의 하이레벨을 MOSFET QD1, QD2에 인가한다. 기억회로 W에 접속된 워드선 WL의 한쪽끝은, 예를들면 접지전위 GND로 된다. X어드레스 단자, XA0∼XAn, Y어드레스 단자 YA0∼YAn에 각각 어드레스 신호를 입력한다. 이로인해,선택된 1개의 워드선 WL에 하이레벨을 인가하고, 선택된 1개의 Y선택선 YL에 대응하는 1개의 MOSFET QD2를 도동시켜, 선택된 데이터 선 DL를 센스앰프 SA에 접속한다. 그리고, 센스앤프 SA에 의해서 데이터선 DL의 전위의 변화를 검출한다. 사전에 각 데이터선의 전위를, 도시하지 않은 프리챠지 회로에 의해서, 예를들면,2V로 프리챠지하여 둔다. 제4도 A와 같이, 정상인 메모리 셀 MC1은, 위드선 WL의 하이레벨에 의해서"on"상태로 되기 위해서, 센스 앰프에 의해서 데이터선 DL의 전위 OV가 검출된다. 그리나, 불량 메모리 셀 MC2는, 제4도 B에 도시한 것과 같이, 스렛쉬홀드 전압의 상승에 의해서, 워드선WL가 하이레벨 일때에도, "off"상태로 있으므로, 프리챠지 전압(2V)가 그대로 검출된다. 모든 메모리 셀에 대해서 이것을 행하는 것에 의해, 챠지·게인 상태에 있는 불량 메모리 셀을 검사할 수 있다.Program signal not shown

Enable signal formed by

Is applied to MOSFETs QD1 and QD2. One end of the word line WL connected to the memory circuit W becomes, for example, the ground potential GND. The address signals are input to the X address terminals, XA0 to XAn, and Y address terminals YA0 to YAn, respectively. Thus, a high level is applied to one selected word line WL, and one MOSFET QD2 corresponding to one selected Y selection line YL is driven to connect the selected data line DL to the sense amplifier SA. Then, the sense n SA detects a change in the potential of the data line DL. The potential of each data line is precharged to 2V, for example, by a precharge circuit (not shown) in advance. As shown in FIG. 4A, the normal memory cell MC1 is turned on by the high level of the weed line WL, so that the potential OV of the data line DL is detected by the sense amplifier. However, as shown in Fig. 4B, the bad memory cell MC2 is in the " off " state even when the word line WL is at a high level due to the increase in the threshold voltage, so that the precharge voltage 2V is increased. It is detected as it is. By doing this for all the memory cells, the defective memory cells in the charge gain state can be inspected.

Also, even when the threshold voltage of the memory cell does not rise to the voltage applied to the word line (when the gain of the charge is small), a slight change in the potential of the data is detected, indicating that the memory cell is defective. There is a number.

(3) Charge loss inspection process.

In order to detect that the MOSFET QM of the memory chamber is in the deflation type, a call is made with all word lines WL at the ground potential. The control circuit AC is used for this.

A low voltage is applied to the X address terminal XA0 so that the inverter circuit IV3 outputs a low level signal. In this embodiment, OV or 5V (ground potential or power source potential) is applied. As a result, a low level signal is output from inverter circuit IV3. This low level signal is applied to MOSFETs Q20 and Q21 through inverter circuits IV1 and IV2. This causes the MOSFET Q20 to conduct, and the MOSFET Q21 becomes nonconducting.

On the other hand, a high voltage is applied to the X address terminal XA1 so that the inverter circuit IV5 outputs a high level signal. In this embodiment, the storage voltage Vpp (12.5 V) is applied. As a result, a high level signal is output from inverter circuit IV5. This high level signal is inverted by inverter circuit IV4 and applied to MOSFETs Q19 and Q22. As a result, the MOSFET Q19 becomes conductive and the MOSFET Q22 becomes non-conductive.

의 로우 레벨(OV)가, 챠지 로스 검사 공정의 사이에 인가된다. 한편, 기억회로 W에서 워드선 WL의 한쪽끝에, 예를들면, 접지전위가 인가된다, 따라서, MOSFET QD1이 도통되는 결과, 각 워드선 WL에 로우 레벨 신호가 인가된다.Therefore, the output of each unit circuit uDCR becomes low level irrespective of the level of the X address signal (ie, complementary address signal). That is, all outputs of the X decoder X-DCR become low level. As a result, the low level signal, for example, OV, is applied to the MOSFET QD1 source. The gate enable signal of MOSFET QD1 has a write enable signal

Low level OV is applied during the charge loss inspection process. On the other hand, for example, a ground potential is applied to one end of the word line WL in the memory circuit W. As a result, the MOSFET QD1 becomes conductive, so that a low level signal is applied to each word line WL.

On the other hand, the Y address signals are input to the Y address terminals YA0 to YAn as in a normal call, and each data line DL is selectively connected to the sense amplifier SA. The sense amplifier SA detects a change in potential of the data line DL precharged at 2V, for example. As a result, as shown in FIG. 4C, the defective memory cell MC3 having the low threshold voltage (depth type) in the charge-loss state is turned on even when the gate potential is OV, and thus the data line is turned on. The potential drops and the call voltage becomes OV. On the other hand, the normal memory cell MC4 is in the " off " state because the word line potential is OV, and the precharge voltage 2V of the data line is detected by the sense amplifier SA as shown in FIG. By doing this for each data line, the defective memory cell in the charged-loss state can be inspected.

In this case, call inspection can be performed on all data lines DL at the same time. The reason for this is that if any one of the defective memory cells exists, the call voltage in the sense and amplifier SA is OV.

Similar to the charge gain inspection process, even a small change in the threshold voltage of the memory cell can be detected.

By auditing the charge gain and the charge loss, it is possible to reliably check the two types of defects occurring in the memory cell by aging. Even with this test, no positive or negative charges are stored in the normal memory cell. In the OTP-type EPROM without a defect, no memory is stored by inspection, so that the device can be supplied to the user in a state of no memory.

In the above configuration, when a voltage of 12.5 V is applied to the X address terminals XA0 and XA1 during the stress applying process and the charge loss inspection process, the peripheral circuit is connected. It can be automatically set to the stress applied state or the charge loss test state. Moreover, it is not necessary to provide a new terminal for inspection.

The terminal used for the said inspection may be other terminals other than XA0 and XA1. Terminals for applying a signal for the stress application process to the control circuit AC are terminals which are not used during the stress application process, for example, X address terminals other than XA0 and XA1, Y address terminals, and data input / output terminals I. You can use either / O. As a terminal for applying a signal for the charge loss inspection process to the control circuit AC, terminals not used in the charge loss inspection process, for example, X address terminals other than XA0 and XA1 can be used.

The control circuits AC1 and AC2 may have other configurations. A circuit can be detected which indicates that the inspection process is applied to the terminal, and can transmit a high level or low level signal in accordance with the signal. In other words, when the normal high level (5V) or the low level (OV) is applied to the terminal, when the voltage higher than the high level is applied to the terminal, the output signal and the reverse phase signal is outputted. Good circuit.

As shown in FIG. 7, the X decoder X-DCR may have a two-stage configuration including the first decoder X-DCR1 and the second X decoder X-DCR2. For example, an internal address signal corresponding to the address signals AX0 to AX (n-3) is supplied to the first decoder from the X address buffer X-ADB. The second decoder X-DCR2 is supplied with an internal address signal corresponding to, for example, three bits of X address signals AX (n-2) to AXn from the X address buffer X-ADB. The unit circuit of the first decoder X-DCR1 has a configuration in which the MOSFETs Q7 and Q8 are removed from the unit circuit uDCR of the X decoder X-DCR shown in FIG. The unit circuit of the second decoder X-DCR2 has a configuration in which the MOSFETs Q7, Q8 and Q19 to Q22 are removed from the unit circuit uDCR of the X decoder X-DCR shown in FIG. Each of the outputs of the first and second decoders X-DCR1 and X-DCR2 is output to each word line WL through the NOR gate circuit G1 which is the P-channel MOSFETs Q23 and Q24 and the N-channel MOSFETs Q25 and Q26.

In the stress application step, 12.5 V is applied to the address terminal XA0, and OV or 5 V is applied to the XA1. By the address control circuit AC, all the outputs of the first decoder X-DCR1 become low level irrespective of the X address signals AX0 to AX (n-3). According to the X address signals AX (n-2) to AXn, one line of the eight outputs of the second decoder X-DCR2 becomes low. For this reason, the gate circuit G1 outputs a high level and applies electric field stress to the memory cell MC. According to this example, the stress applying step is performed in eight times by changing the output of the second decoder X-DCR2 one after the other.

In the charge loss inspection process, OV or 5V is applied to the address terminal XA0, and 12.5V is applied to XA1. By the address control circuit AC, all outputs of the first decoder X-DCR1 become high level regardless of the X address signals XA0 to XA (n-3). Regardless of the X address signals XA (n-2) to XAn, the gate circuit G1 outputs a low level. As a result, the potential of each word line WL becomes low.

In normal storage or recall, only the gate circuit G1, in which the outputs of the first and second decoders X-DCR1 and X-DCR2 are all at the low level, outputs a high level. As a result, one word line is selected.

According to the present invention, even when a defect exists in the insulating film on the side surface of the floating gate 4, the defect can be detected.

According to this invention, the following effects are acquired. By aging in a state where a high voltage applied to all of the word lines is applied, it is possible to cause charge memory and charge loss in a defective memory cell without heat for injecting charges into the defective memory cell. Since all of the word lines are configured to be OV, the existence of the charged and lost memory cells can be quickly detected only by detecting the voltage of the data lines.

Since the inspection can be performed in accordance with the voltage applied to the address terminal, the inspection can be performed without increasing the number of terminals.

A stress applying step of aging while applying a high voltage to the word line while keeping the data line at approximately OV level, a jagi gain inspection step of inspecting a memory cell subjected to high threshold voltage, and deflation. In the charge loss inspection process of inspecting a memory cell, a defect of the memory cell is inspected. This makes it possible to detect a defect of the memory cell even without storing the memory cell. After encapsulation, like a OTP-type EPROM, semiconductor memories that cannot be subjected to memory inspection can be inspected with high reliability.

In the stress application step, high voltage is applied to all word lines at the same time, and aging is performed. In the charge loss check process, all word lines are simultaneously called as OV, and data calls are made. As a result, in the stress application step and the charge loss inspection step, the stress application and inspection of all the memory cells can be performed simultaneously or approximately simultaneously, thereby reducing the inspection time.

Even after sealing in a package that is opaque to ultraviolet rays such as plastic, the defect inspection of the memory cell can be performed. As a result, the defect of the memory cell caused by various causes (mechanical stress during dicing, mold stress, etc.) after wafer completion can be detected.

As mentioned above, although the invention made by this inventor was demonstrated concretely according to the Example, this invention is not limited to the said Example, Needless to say that various changes are possible in the range which does not deviate from the summary.

The potential of the word line WL in the inspection process is determined without using the address control circuits AC1 and AC2.

For example, as shown in FIG. 8, the potential of the word line WL can be controlled by the exclusive OR gate circuits G2 and G3. In the stress application step, all the X address signals are set at high level. For this reason, one of the internal (complementary) address signals sent from the X address buffer X-ADB is set at high level and the other is set at low level. The low level of all the internal address signals is input to one of the gate circuits G2 and G3. The output of the gate circuits G2 and G3 becomes high by the high level of the signal? Input to the other side of the gate circuits G2 and G3. This causes all internal address signals to go high.

On the other hand, in the charge loss inspection process, all the X address signals are set at the low level. For this reason, one of the internal (complementary) address signals sent from the X address buffer X-ADB is set at high level, and the other is set at low level. The high level of all the internal address signals is input to one of the gate circuits G2 and G3. The outputs of the gate circuits G2 and G3 become low level due to the high level of the signal X input to the other side of the gate circuits G2 and G3. This causes all internal address signals to go low.

During normal recall and storage, the signal 신호 goes low. In this example, the X decoder X-DCR has a configuration in which the MOSFETs Q19 to Q22 of the X decoder X-DCR in FIG. 2 are omitted.

When stress is applied or when the charge loss test is performed, a word line may be selected in accordance with the address signal to apply 12.5V or 0V. In this system, however, more time is required than in the above example in order to picturize the required stress application time for each memory cell, particularly in the stress application process.

In the above description, the case where the invention made by the present inventors is mainly applied to the OTP-type EPROM which is the background of the use is described. However, the present invention is not limited thereto and may be applied to an EPROM capable of erasing by ultraviolet rays. According to the present invention, there is a great effect that the time for defect inspection is short and the erasure of the memory data after the completion of the inspection is unnecessary. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor memory device that is a MIS (Metal Insulator Semiconductor) FET having a floating gate, and a semiconductor memory device that uses a charge storage transistor such as an EEPROM. In any case, the insulating films covering the first and second gate insulating films and the floating gate need not be silicon oxide films. The present invention is also applied to an EPROM on-chip microcomputer, that is, a device in which an EPROM is formed on a microcomputer chip. The present invention is applied to a case where an EPROM is included in a memory IC card having a plurality of memory IC chips.

Claims (45)

A semiconductor substrate, a plurality of word lines extending in one direction on the semiconductor substrate, a plurality of data lines extending in a direction intersecting the word lines on the semiconductor substrate, formed on the semiconductor substrate, and between the data lines and the word lines An MISFET having a control gate connected to the word line, a floating gate, a semiconductor region connected to the data line, and a semiconductor region connected to a ground potential line, arranged in correspondence to an intersection, and accumulating charge in the floating gate. By applying a predetermined stress voltage of a high voltage level to the word line to change the threshold hold voltage of the plurality of memory cells storing data and the defective defective memory cell adjacent to the floating gate. When the voltage is applied to the word line, the potential of the data line is grounded. First means for dropping to or near the ground potential and second means for continuously applying a ground potential to the word line to detect the presence of a memory cell having a threshold hold voltage varied by the stress voltage. A semiconductor integrated circuit device. The method according to claim 1, further comprising an X decoder for selecting a predetermined one of the word lines in response to an X address signal and a plurality of external terminals for inputting an external signal. Is coupled to at least one of a first circuit and an external terminal for controlling the output of the X decoder to apply the stress voltage to the word line, and a predetermined first control input from the external terminal. And a second circuit for controlling the first circuit in accordance with a signal. The semiconductor integrated circuit device according to claim 2, wherein the plurality of external terminals are further coupled to the X decoder for inputting the X address signal for the X decoder. The apparatus of claim 2, wherein the second means is coupled to at least one of a third circuit and an external terminal for controlling the output of the X decoder to apply a ground potential to the word line. And a fourth circuit for controlling the third circuit according to a predetermined second control signal input from an external terminal. 5. The semiconductor integrated circuit device according to claim 4, wherein the external terminal is further coupled to the X decoder for inputting the X address signal for the X decoder. The method of claim 1, further comprising an address buffer coupled to an external terminal and forming an internal address signal from an address signal input from an external terminal, such that the stress voltage or ground potential can be applied to the word line. A semiconductor integrated circuit device comprising a control circuit for controlling the output of the address buffer circuit. The semiconductor integrated circuit device according to claim 1, wherein the stress voltage has a voltage level equal to a voltage level for storing data in the memory cell. A control substrate, a floating gate, and a data line formed on a semiconductor substrate, a data line and a word line formed on the semiconductor substrate, and a semiconductor line, and arranged to correspond to an intersection point between the data line and the word line, and connected to the word line. A method for inspecting a semiconductor integrated circuit device, comprising: a MISFET having a semiconductor region connected to the semiconductor region; and a semiconductor region connected to the ground potential line, the memory cell storing data by accumulating charge in the floating gate. In a state where a predetermined stress voltage of a high voltage level is applied to the word line and a voltage equal to the ground potential is applied to the data line to change the threshold hold voltage of the defective memory cell adjacent to the floating gate. Aging balls for aging the semiconductor integrated circuit device by heating After the aging process, a test step of inspecting the memory cell to detect the presence of a memory cell whose threshold hold voltage is increased by the aging step and after the aging step, the threshold hold voltage is increased by the aging step. An inspection method of a semiconductor integrated circuit device including an inspection step of inspecting the memory cell to detect the presence of a lowered memory cell. The MISFET according to claim 8, wherein each of the MISFETs includes an upper insulating film between the floating gate and the control gate, and a lower insulating film between the floating gate and the semiconductor substrate, wherein a threshold hold voltage is increased by the aging process. The inspection process for detecting the presence of a defective memory cell detects a MISFET having a defective underlayer insulating film, and the inspection process for detecting the presence of a memory cell whose threshold hold voltage has dropped by the aging process is defective. An inspection method of a semiconductor integrated circuit device for detecting a memory cell having an upper insulating film. 10. The semiconductor integrated circuit device according to claim 9, wherein the semiconductor integrated circuit device further comprises: an X decoder for selecting a predetermined one of the word lines in response to an X address signal; a plurality of external terminals for inputting an external signal; A first circuit for controlling the output of the decoder and a second circuit for controlling the first circuit according to a control signal input from at least one of the external terminals, and controlling the output of the X decoder. Inspection of the semiconductor integrated circuit device in which the first circuit is controlled by the second circuit having a control signal input from the external terminal so that the predetermined stress voltage is applied to the word line. Way 10. The semiconductor integrated circuit device according to claim 9, wherein the semiconductor integrated circuit device further includes an X decoder for selecting a predetermined one of the word lines in response to an X address signal, a plurality of external terminals for inputting external terminals, and X. A first circuit for controlling the output of the decoder and a second circuit for controlling the first circuit according to a control signal input from at least one of the external terminals, and controlling the output of the X decoder. The first circuit is controlled by the second circuit having a control signal input from the external terminal in the inspection step of detecting a drop in the threshold hold voltage so that the ground potential is applied to the word line. Inspection method of semiconductor integrated circuit device. The method of claim 9, wherein the stress voltage has a voltage level equal to a memory voltage level for storing data in the memory cell. A semiconductor substrate, a plurality of word lines extending in one direction on the semiconductor substrate, a plurality of data lines extending in a direction intersecting the weed line on the semiconductor substrate, formed on the semiconductor substrate, and between the data lines and the word lines An MISFET having a control gate connected to the word line, a floating gate, a semiconductor region connected to the data line, and a semiconductor region connected to a ground potential line, arranged in correspondence to an intersection, and accumulating charge in the floating gate. A predetermined stress voltage of a high voltage level to change a threshold hold voltage of a plurality of memory cells for storing data and the word line and having an insulating defect adjacent to the floating gate. The threshold hold voltage changed by the stress voltage First means for continuously applying a ground potential to the word line to detect the presence of an excitation memory cell and the data line, and when the stress voltage is applied to the word line, bringing the potential of the data line to ground potential. Or a second means for dropping near the ground potential. The EPROM of claim 13, wherein the stress voltage has a voltage level equal to a memory voltage level for storing data in the memory cell. 15. The apparatus of claim 14, wherein the first means comprises: selecting means for selecting one of the word lines in accordance with an address signal, and storing a memory voltage having the storage voltage level coupled to the word line to a selected word line. Memory means for applying, and control means coupled to said selection means and controlling said selection means in accordance with said control signal such that said word line is in one of a selected or unselected state in accordance with a control signal. 16. The apparatus of claim 15, wherein said selecting means comprises an X decoder for selecting one of said word lines in response to said address signal, said control means being coupled to said X decoder and said word line A first circuit for controlling the X decoder to be in the selected state and a second circuit coupled to the X decoder and for controlling the X decoder to make the word line non-selected. 17. The EPROM of claim 16, wherein the control signal comprises a first control signal for controlling the first circuit and a second control signal for controlling the second circuit. 18. The EPROM of claim 17, further comprising a plurality of external terminals for inputting the address signal, wherein one of the external terminals also inputs first and second control signals. 20. The EPROM of claim 18, further comprising a package for packaging the semiconductor substrate so as to cover the memory cell and not allowing ultraviolet light to pass through. The EPROM of claim 13, wherein when the first means applies a ground potential to the word line, the second means sets the potential of the data line to perform a call operation. A semiconductor substrate, a plurality of word lines extending in one direction on the semiconductor substrate, a plurality of data lines extending in a direction intersecting the word lines on the semiconductor substrate, formed on the semiconductor substrate, and between the data lines and the word lines An MISFET having a control gate connected to the word line, a floating gate, a semiconductor region connected to the data line, and a semiconductor region connected to a ground potential line, arranged in correspondence to an intersection, and accumulating charge in the floating gate. A predetermined stress voltage of a high voltage level so as to change the threshold hold voltage of a plurality of memory cells storing data, the defective memory cell coupled to the word line and imposed on the floating gate. The threshold hold voltage changed by the stress voltage Coupled to the data line and first means for continuously applying a ground potential to the word line to detect the presence of an excited memory cell, and when the stress voltage is applied to the word line, shift the potential of the data line to ground potential. Or an EPROM formed on the microcomputer chip comprising a second means for dropping near the ground potential. The EPROM of claim 21, wherein the stress voltage is formed on a microcomputer chip having a voltage level equal to a memory voltage level for storing data in the memory cell. 23. The apparatus of claim 22, wherein the first means comprises: selecting means for selecting one of the weed lines according to an address signal, and storing a memory voltage having the memory voltage level coupled to the word line to a selected word line. A storage means coupled to the selection means, the control means for controlling the selection means in accordance with the control signal such that the word line is in one of the selected or unselected states in accordance with the control signal. EPROM. 24. The apparatus of claim 23, wherein said selecting means comprises an X decoder for selecting one of said word lines in response to said address signal, said control means being coupled to said X decoder and said word line A microcomputer chip comprising a first circuit for controlling the X decoder to be in the selected state and a second circuit coupled to the X decoder and for controlling the X decoder to make the word line non-selected EPROM formed above. The microcomputer chip of claim 24, wherein the control signal comprises a first control signal for controlling the first circuit and a second control signal for controlling the second circuit. Formed EPROM. 26. The EPROM of claim 25, further comprising a package for packaging the semiconductor substrate so as to cover the memory cell and including a package that does not pass ultraviolet rays. A control substrate, a floating gate, and a data line formed on a semiconductor substrate, a data line and a word line formed on the semiconductor substrate, and formed on the semiconductor substrate, and arranged in correspondence to an intersection point between the data line and the word line, and connected to the word line. A method for inspecting an EPROM formed on a microcomputer chip comprising a MISFET having a semiconductor region connected to and a semiconductor region connected to a ground potential line, the memory cell storing data by accumulating charge in the floating gate. A predetermined stress voltage of a high voltage level is applied to the word line and a voltage equal to the ground potential is applied to the data line to change the threshold hold voltage of the defective memory cell adjacent to the floating gate. Aging the EPROM by heating in a state; After the aging process, a test step of inspecting the memory cell to detect the presence of a memory cell whose threshold hold voltage is increased by the aging step, and after the aging step, the threshold hold voltage is lowered by the aging step. An inspection method of an EPROM formed on a microcomputer chip comprising an inspection process for inspecting the memory cell to detect the presence of the memory cell. 28. The semiconductor device of claim 27, wherein each of the MISFETs includes an upper insulating film between the floating gate and the control gate, and a lower insulating film between the floating gate and the semiconductor substrate, and a threshold hold voltage by the aging process. The inspection process for detecting the presence of the raised memory cell detects the MISFET having a defective lower insulating film, and the inspection process for detecting the presence of the memory cell whose threshold hold voltage has been lowered by the aging process is defective. A method for inspecting an EPROM formed on a microcomputer chip for detecting a memory cell having a conflicting insulating film having a crack. 30. The device according to claim 28, wherein the EPROM formed on the microcomputer chip is further coupled to a control means, to the control means and to the word line, and according to the output of the control means, one of the ground potential and the threshold voltage. And a first means for applying the word line to said word line. 30. The method of claim 29, wherein the stress voltage is formed on a microcomputer chip having a voltage level equal to a memory voltage level for storing data in the memory cell. 31. The method of claim 30, wherein the first means comprises: selecting means for selecting one of the word lines in accordance with an address signal, and storing a memory voltage having the storage voltage level coupled to the word line to a selected word line. An EPROM formed on a microcomputer chip comprising memory means for applying, and control means coupled to said selection means and controlling said selection means in accordance with said control signal such that said word line is in one of a selected or unselected state in accordance with a control signal. Inspection method. 32. The inspection of an EPROM formed on a microcomputer chip according to claim 31, wherein the EPROM formed on the microcomputer chip further packages the semiconductor substrate to cover the memory cell and includes a package that does not pass ultraviolet light. Way. A semiconductor substrate, a plurality of word lines extending in one direction on the semiconductor substrate, a plurality of data lines extending in a direction intersecting the word lines on the semiconductor substrate, formed on the semiconductor substrate, and between the data lines and the word lines An MISFET having a control gate connected to the word line, a floating gate, a semiconductor region connected to the data line, and a semiconductor region connected to a ground potential line, arranged in correspondence to an intersection, and accumulating charge in the floating gate. By applying a predetermined stress voltage of a high voltage level to the word line to change the threshold hold voltage of a plurality of memory cells storing data and a defective memory cell adjacent to the floating gate. When the voltage is applied to the word line, the potential of the data line is grounded. First means for dropping to or near the ground potential line, second means for continuously applying a ground potential to the word line by detecting the presence of a memory cell having a threshold hold voltage varied by the stress voltage; And a package for packaging the semiconductor substrate so as to cover the memory cell and not passing ultraviolet rays. A semiconductor substrate, a plurality of word lines extending in one direction on the semiconductor substrate, a plurality of data lines extending in a direction intersecting the word lines on the semiconductor substrate, formed on the semiconductor substrate, and between the data lines and the word lines An MISFET having a control gate connected to the word line, a floating gate, a semiconductor region connected to the data line, and a semiconductor region connected to a ground potential line, arranged in correspondence to an intersection, and accumulating charge in the floating gate. A plurality of memory shells for storing data, said word lines being coupled to said word line to convert a predetermined stress voltage at a high voltage level to change the threshold hold voltage of an insulating defective memory cell adjacent said floating gate. The threshold hold voltage changed by the stress voltage First means for continuously applying a ground potential to the word line to detect the presence of an excited memory cell, coupled to the data line, to the potential roll ground potential of the data line when the stress voltage is applied to the word line Or a second means for dropping near the ground potential and a package for covering the semiconductor substrate so as to cover the memory cell and not passing ultraviolet rays. A semiconductor substrate, a plurality of word lines extending in one direction on the semiconductor substrate, a plurality of data lines extending in a direction crossing the word lines on the semiconductor substrate, formed on the semiconductor substrate, and between the data line and the weed line An MISFET having a control gate connected to the word line, a floating gate, a semiconductor region connected to the data line, and a semiconductor region connected to a ground potential line, arranged in correspondence to an intersection, and accumulating charge in the floating gate. A plurality of memory cells for storing data, said word lines being coupled to said word line to change a threshold hold voltage of said defective memory cell adjacent said floating gate to said predetermined stress voltage at said high voltage level. The threshold hold voltage changed by the stress voltage First means for continuously applying a ground potential to the word line to detect the presence of an excited memory cell, coupled to the data line, bringing the potential of the data line to ground potential when the stress voltage is applied to the word line Or an EPROM formed on a microcomputer chip comprising a second means for dropping near the ground potential and a package covering the memory cell to cover the memory cells and not passing ultraviolet rays. A control substrate, a floating gate, and a data line formed on a semiconductor substrate, a data line and a word line formed on the semiconductor substrate, and formed on the semiconductor substrate, and arranged in correspondence to an intersection point between the data line and the word line, and connected to the word line. 10. A method for inspecting a semiconductor integrated circuit device, comprising: a MISFET having a semiconductor region connected to and a semiconductor region connected to a ground potential line, the memory cell storing data by accumulating charge in the floating gate; Heating in a state where a predetermined stress voltage of a high voltage level is applied to the word line and a voltage equal to the ground potential is applied to the data line so as to change the threshold hold voltage of the faulty memory cell adjacent to the floating gate. Aging the semiconductor integrated circuit device by After the aging process, a test step of inspecting the memory cell to detect the presence of a memory cell whose threshold hold voltage is increased by the aging process and a threshold hold voltage is dropped by the aging process after the aging process. An inspection step of inspecting the memory cell to detect the presence of the memory cell, wherein the semiconductor integrated circuit device further comprises a package that covers the semiconductor substrate to cover the memory cell and does not pass ultraviolet rays. Inspection method of a semiconductor integrated circuit device comprising. The threshold hold voltage according to claim 36, wherein each of the MISFETs includes an upper insulating film between the floating gate and the control gate, and a lower insulating film between the floating gate and the semiconductor substrate. The inspection process for detecting the presence of the raised memory cell detects the MISFET having a defective lower insulating film, and the inspection process for detecting the presence of the memory cell whose threshold hold voltage has been lowered by the aging process is defective. A method for inspecting a semiconductor integrated circuit for detecting a memory cell having an upper insulating film. 38. The semiconductor integrated circuit device according to claim 37, wherein the semiconductor integrated circuit device is further coupled to a control means, to the control means and to the word line, wherein the word of one of the ground potential and the stress voltage is dependent upon the output of the control means. A method for inspecting a semiconductor integrated circuit device comprising first means for applying a line. 39. The semiconductor integrated circuit device according to claim 38, wherein the semiconductor integrated circuit device further comprises an external terminal coupled to the control means, the control means outputting the output in response to an external signal supplied to the external terminal. A method of inspecting a semiconductor integrated circuit device for supplying the means. 40. The method of claim 39, wherein the stress voltage has a voltage level equal to a memory voltage level for storing data in the memory cell. 41. The apparatus of claim 40, wherein the first means comprises: selecting means for selecting one of the word lines in accordance with an address signal, and storing a memory voltage having the storage voltage level coupled to the word line to a selected word line. And a storage means for applying, said control means being coupled to said selection means, said semiconductor means for controlling said selection means in response to said external signal such that said word line is in one of a selected or unselected state in accordance with said external signal. Inspection method of integrated circuit device. 42. The apparatus of claim 41, wherein said selecting means comprises an X decoder for selecting one of said word lines in response to said address signal, said control means being coupled to said X decoder and said word line A first circuit for controlling the X decoder to be in the selected state and a second circuit coupled to the X decoder and for controlling the X decoder to make the word line non-selected; Inspection method. 43. The method for inspecting a semiconductor integrated circuit device according to claim 42, wherein said semiconductor integrated circuit device further comprises several external terminals for inputting said address signal. A control substrate, a floating gate, and a data line formed on a semiconductor substrate, a data line and a weed line formed on the semiconductor substrate, and formed on the semiconductor substrate, corresponding to an intersection point between the data line and the word line, and connected to the word line. A method for inspecting an EPROM formed on a microcomputer chip comprising a MISFET having a semiconductor region connected to and a semiconductor region connected to a ground potential line, the memory cell storing data by accumulating charge in the floating gate. And a predetermined stress voltage of a high voltage level is applied to the word line and a voltage equal to the ground potential is applied to the data line to change the threshold hold voltage of the defective memory cell adjacent to the floating gate. Aging the EPROM by heating at After the aging process, after the aging process, a test process for inspecting the memory cell to detect the presence of the memory cell whose threshold hold voltage is increased by the aging process, and after the aging process, the threshold hold voltage is lowered by the aging process. And an inspection process for inspecting the memory cell to detect the presence of the memory cell, wherein the EPROM formed on the microcomputer chip further packages the semiconductor substrate to cover the memory cell and does not pass ultraviolet rays. An inspection method of an EPROM formed on a microcomputer chip containing a cage. 45. The threshold hold voltage according to claim 44, wherein each of the MISFETs comprises an upper insulating film between the floating gate and the control gate, and a lower insulating film between the floating gate and the semiconductor substrate. The inspection process for detecting the presence of the raised memory cell detects the MISFET having a defective lower insulating film, and the inspection process for detecting the presence of the memory cell whose threshold hold voltage has been lowered by the aging process is defective. A method for inspecting an EPROM formed on a microcomputer chip for detecting a memory cell having an upper insulating film with a film.

Images