KR940006173B1 - Circuit for clerk conversion - Google Patents

Abstract

The clock converting circuit comprises a clock generator for generating a basic clock, one or more demultipliers for demultiplying the basic clock by a sequential demultiplying ratio, a clock select controller for generating first and second select signals, a first selector for selectively generating each output of the demultiplier by the first select signal, a synchronizing signal generator for generating vertical and horizontal synchronizing signal, a logic operator for logically operating the outputs of the synchronizing signal generator and the first selector, and a second selector for selectively generating the outputs of the logic operator and the clock generator by the second select signal, thereby preventing data from losing during a mutual data exchange.

Description

Clock conversion circuit

1 is a circuit diagram according to the present invention.

2 is a timing diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

10: clock generator 20: divider

30: first selector 40: micom

50: synchronization signal generator 60: first gate

70: second gate 80: second selector

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video camera, and more particularly, to a clock converting circuit for appropriately converting clocks supplied thereto in order to match mutual speed when writing image data recorded in a buffer memory into an IC card or the like.

In general, a video still camera records the incoming data into a buffer memory and records it back into a memory such as an IC card. In this case, the speeds of the buffer memory and the IC card must match, but generally they are inconsistent.

For this reason, the use of the IC card must always be limited in its kind. This has brought many limitations in product design and use.

Accordingly, an object of the present invention is to provide a clock converting circuit capable of allowing data exchange between them even if the speeds of the buffer memory and the IC card are different in the video still camera.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram according to the present invention, and a clock generator 10 for generating a basic clock and a divider 20 for receiving the basic clocks of the clock generator 10 and dividing them in sequential division ratios and outputting them in parallel. And a first selector 30 that receives the parallel frequency divider output of the frequency divider 20 and selectively outputs the same by a predetermined first selection signal, and a synchronization signal generator that generates and outputs vertical and horizontal synchronization signals in response to a predetermined clock ( 50), the first gate 60 to logically multiply the outputs of the synchronization signal generator 50 and the first selector 30, the output of the first gate 60 and the synchronization signal generator 50 A second gate 70 for logically multiplying an output, a second selector 80 for selectively outputting an output of the second gate 70 and an output of the clock generator 10 by a predetermined second selection signal; Output the first and second selection signals to the first and second selectors 30.80 in time. It consists of a microcomputer 40 for controlling the first, second selector (30.80).

2 is a timing diagram according to the present invention, FIG. 2A is an output of the first selector 30, FIG. 2B is a horizontal synchronization signal of the synchronization signal generator 50, and FIG. Vertical sync signal. 2d is an output of the second gate 70, 2e is a second selection signal of the microcomputer 40, and 2f is an output signal of the second selector 80. FIG.

Hereinafter, an embodiment of the present invention will be described in detail based on the above configuration.

The present invention is to record image data recorded in a buffer memory in a digital video camera to a memory means such as an IC card regardless of its allowable speed.

That is, the read block of the buffer memory is read down to the allowable speed of the IC card, and the memory card is given a tight clock to the IC card so that the data written in the buffer memory can be written to the IC card without loss. It is to be.

In FIG. 1, the output clock of the clock generator 10 is supplied to the divider 20, divided and output in parallel. In the divided form, two signals are sequentially divided into four times when signals are input and output in parallel.

These divided signals are all input to the first selector 30, where the microcomputer 40 supplies the first selector 30 to the first selector 30. Then, the first selector 30 selects and outputs one of the parallel output signals of the divider 20 input in parallel accordingly.

The output of the first selector 30 and the horizontal synchronous output signal of the synchronous signal generator 50 are input to the first gate 60 and logically multiplied with each other. This ANDed signal is then ANDed again at the second gate 70 and the vertical synchronization signal of the synchronization signal generator 50.

The second selector 80 selects and outputs the output of the second gate 70 and the output of the clock generator 10, and the selecting state is the second selection signal of the microcomputer 40 (FIG. 2e degrees).

단이 선택되어 제 2d 도와 같이 분주된 클럭신호 즉 게이트(70)에서 출력되는 파형이 출력된다.If the second selection signal (Fig. 2e) output from the microcomputer 40 is in the logic " high " state, the B stage of the second selector is selected so that the clock signal of the clock generator 10 is immediately outputted. If it is in the "low" state, the second selector 80

The stage is selected to output the divided clock signal, that is, the waveform output from the gate 70 as shown in the 2d diagram.

Therefore, the signal selected by the second selector 80 becomes equal to the second f degree. That is, the f signal has a form in which the clock signal of the clock generator 10 and the divided clock signal of the second gate 70 are alternated according to the selection signal state of the microcomputer 40.

Therefore, the output clock of the second selector 80 can be mutually converted into two states, and when used as a read or write clock, even if a memory having a different speed is used, the output clock of the second selector 80 can be performed without losing data when exchanging data. have.

As described above, the present invention converts the read and write clocks even though the inherent speeds of the mutual memories are different when the data is temporarily stored in the buffer memory and then transferred to the memory such as an IC card as in a video still camera. There is an advantage that data exchange is possible.

Claims (3)

A clock conversion circuit comprising: clock generation means for generating a basic clock, one or more division means for dividing the basic clock of the clock generation means in a sequential predetermined division ratio, and outputting each of them; Clock selection control means for outputting first and second selection signals, first selection means for condensing and outputting each divided output of the frequency division stage by the first selection signal predetermined state, and receiving the predetermined clock vertically and horizontally Synchronizing signal generating means for generating a synchronizing signal, logic calculating means for logically calculating and outputting the divided clock selected by the synchronizing signal generating means and the first selecting means, output of the logical calculating means and output of the clock generating means And second selection means for selectively outputting by the second selection signal. 2. The apparatus of claim 1, wherein the dividing means comprises two or more dividers for dividing the clock generating means, dividing the two divided basic clocks, and outputting the divided clocks in parallel. Clock conversion circuit. 2. The logic unit as set forth in claim 1, wherein the logic operation means comprises: a first logic gate for logically multiplying the output selected by the first selection means and the horizontal synchronization signal output from the synchronization signal generating means, and the first logic gate and the synchronization signal. And a second logic gate for logically multiplying the vertical synchronization signal output from the generating means.

Images