KR940000942B1 - Bit synchronous circuit - Google Patents

Abstract

The circuit includes a phase and frequency comparator (PFC,11) for outputting the latched clock pulses, a PFC gain adjustment means (12) for outputting the pulse from a 2nd output terminal, an N division means (13) for dividing the clock pulses from a voltage controlled oscillation means (15), a low-pass filter means (14) for outputting the voltage of the low frequency. The PFC (11) circuit includes D flip-flops (301,302,303), a receiver (304), exclusive OR/NOR gates (305), and an exclusive NOR gate (306).

Description

Bit synchronization circuit

1 is a block diagram of a bit synchronization circuit according to the prior art.

2 is a block diagram of a bit synchronization circuit according to the present invention.

3 is a detailed view of a phase and frequency comparator.

4 is a signal waveform diagram for the block of FIG.

5 is a detailed view of a phase and frequency comparison gain regulator.

6 is a signal waveform diagram for each block of FIG.

* Explanation of symbols for the main parts of the drawings

1,11: Phase and frequency comparator (PFC)

2,14: low pass filter or integrator

3,15: voltage controlled oscillator 12: PFC gain regulator

13: N divider 103: Inverter

104,105: exclusive OR gate

101,102,301 to 303, 501 to 504,506,511 to 51n: D flip flop

500: shift register 304: receiver

305: Exclusive OR / NOR gate 306: Exclusive NOR gate

505: OR gate

According to the present invention, the loop gain of the PLL (Phase Locked Loop) does not change sensitively according to the bit pattern and bit rate of the binary data to be input, and the clock is stably stable even at a high bit rate (over 500 Mpps). And a bit synchronization circuit for recovering data.

(A) is a block diagram of a conventional bit synchronization circuit, (b) is a phase and frequency comparator (hereinafter referred to as PFC) circuit diagram of (a), and (c) is a block diagram of (b) As an operation timing diagram, 1 denotes a PFC, 2 denotes a low pass filter (LPF) or integrator, and 3 denotes a voltage controlled oscillator (VCO).

As shown in (b) and (c) of FIG. 1, the phase and frequency comparators of the conventional bit synchronization circuit input the input data and the output of the voltage controlled oscillator, and the phase of the transition generated from the input data. Since the phases of the clock pulses of the voltage controlled oscillators are compared and the results are output directly, the pulse widths output from the phase and frequency comparators were smaller than the clock pulses and periods of the voltage controlled oscillators. Whenever a transition occurs in the input data, the PFC Output from (1). Belkin (US Patent 4,400,667), Summers (UK Patent 8,039,874, US Patent 4,422,176), Hogge (US Patent 4,535,459).

By the way, in general, the bit synchronization PFC 1 changes the number of pulses output from the PFC 1 according to the number of transitions occurring in the input data, and according to the bit pattern (probability of transitions in the data) of the input data. The loop gain of the PLL changes sensitively (DLDuttweiler, “The Jitter Performance of Phase-Locked Loops Extracting Timing from m Baseband Data Waveforms”, The Bell System Technical Journal, Jan 1976).

Therefore, if the loop gain of the PLL circuit is increased, the bit synchronization circuit becomes unstable when a large amount of transition occurs in the data. If the loop gain is decreased, the bit synchronization circuit becomes unstable when the transition occurs little in the data.

In addition, the low pass filter or integrator 2 of the PLL used in the bit synchronization circuit detects the magnitude of the low pass frequency component, which mainly includes a DC component, among the frequency components of the pulses output from the PFC 1, thereby controlling the voltage controlled oscillator 3. When the width of the pulse output from the PFC (1) is small, that is, when the bit rate of the data is high, the low frequency component is so small that it is impossible to detect and the PLL circuit becomes unstable. Belkin (US Patent 4,400,667), Summers (UK Patent 8,039,874, US Patent 4,422,176), Hogge (US Patent 4,535,459).

Accordingly, the present invention is to solve the above-mentioned conventional problems, limiting the number of pulses output from the PFC when a lot of transitions occur in the data, and the pulses output from the PFC when a few transitions occur in the data Passing it through properly controls the gain of the PFC so that the PLL loop gain of the bit sync does not change sensitively according to the bit pattern of the data. It is an object of the present invention to provide a bit synchronization circuit for optimally operating a bit-synchronous PLL by shaping the width of a pulse output from a PFC in a form independent of the bit rate of data so that it can be detected without distortion.

In order to achieve the above object, the present invention is characterized.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

2 is a block diagram showing a schematic configuration of a bit synchronization circuit according to the present invention, in which 11 is a PFC, 12 is a PFC gain regulator, 13 is an N divider, 14 is a low-pass filter or integrator, and 15 is a voltage controlled oscillator. .

Referring to the drawings the configuration and operation of the present invention will be described.

The PFC 11 compares each time there is a transition in the input data whether the phase of the rising transition of the VCO clock pulse CP is behind or before the center of the bit unit interval of the externally input binary data. The logic level is output as a latch clock pulse that can be latched at a valid point in time (the point at which a transition occurs in the input data).

The PFC gain controller 12 generates a pulse at the first output terminal U when the phase of the rising transition of the VOC clock pulse CP is later than the center of the bit unit interval of the binary input data connected to the PFC 11. If it is ahead, the second output terminal D generates a pulse. When the frequency of occurrence of the shift of the latch clock pulse output from the PFC 11 is greater than the set frequency, the pulse is set to the set frequency (phase and frequency comparison gain limit). The result output from the PFC 11 is processed regardless of the bit pattern and bit rate of the input data, and the result is converted into pulses having a pulse width larger than the VCO clock pulse period. The output of the PFC 11 is output to the first and second output terminals U and D as pulses having a pulse width greater than the VDCO clock pulse period.

The low-pass filter or integrator 14 performs low-pass filtering or integration of the binary data inputted by low-pass filtering or integrating the voltage or current difference of the pulses output from the first and second output terminals U and D of the PFC gain regulator 12. It outputs with the voltage of the low frequency component only including the direct current which concerns the phase of the center of a bit interval, and the phase of the rising transition of VCO clock pulse (CP).

The voltage controlled oscillator 15 outputs a clock pulse CP whose phase and frequency are changed according to the output voltage of the low pass filter or integrator 14 to the PFC 11.

The N divider 13 divides the clock pulse CP driven by the voltage controlled oscillator 15 and outputs the divided clock pulse DCP to the PFC gain regulator 12 to output the PFC gain regulator 12. The output of allows the frequency and width of the pulses to be shaped by the divided clock pulses (DCP).

FIG. 3 is a circuit diagram of the PFC 11 of FIG. 2, where 301, 302 and 303 are D flip-flops, 304 are receivers, 305 are exclusive OR / NOR gates, and 306 are exclusive NOR gates.

The PFC 11 according to the present invention is a bit synchronization digital PFC (patent application No. 11070, 1990) filed by the present applicant, and shows binary data of the data input terminal D1 as shown in FIG. D flip-flop 301 and binary data of which the in-phase clock pulse CP of the voltage-controlled oscillator 15 of FIG. 2 through the receiver 304 is input to the clock input terminal CP1. The D flip-flop 303 and the D flip-flop 301 are inputted to the input terminal D3 and the reverse phase clock pulse / CP through the receiver 304 is input to the clock input terminal CP3. D flip-flop 302 with the output Q1 as the input of the data input terminal D2 and the reverse phase pulse pulse / CP through the receiver 304 as the input of the clock input terminal CP2, the D flip Exclusive OR / NOR gate 305 for inputting the positive outputs Q2, Q3 of the flops 302 and 303, and Q1 and Q3 for the outputs of the D flip flops 301 and 303 as inputs. Consists of the exclusive NOR gate 306.

FIG. 4 is a signal waveform of each part of FIG. 3, and FIG. 4 (a) is a case where the transition position of the clock pulse CP of the voltage controlled oscillator 15 of FIG. 2 is earlier than the center of the data bit unit interval. FIG. 4B shows a case where the transition position of the clock pulse CP of the voltage controlled generator 15 of FIG. 2 is behind the center of the data bit unit interval.

A case in which the transition position of the clock pulse CP of the voltage controlled oscillator 15 of FIG. 2 is earlier than the center of the data bit unit will be described with reference to FIG.

The data re-timed with the in-phase clock pulse CP with respect to the clock pulse CP is converted into the data Q2 and the reverse phase clock pulse with the re-timed data with the reverse phase clock pulse / CP again with respect to the clock pulse CP. The output UD of the exclusive OR of the exclusive OR / NOR gate 305 taking an exclusive OR since there is no phase difference with the timing data Q3 maintains a "0" logic level. In addition, the phase difference between the data Q1 retimed with the in-phase clock pulse and the data Q3 retimed with the reverse phase clock pulse always differs by 1/2 of the period of the clock pulse CP. Each time there is an output UDCP of the exclusive NOR gate 306 of FIG. 3, a pulse having a "0" logic level pulse width of 1/2 cycle of the clock pulse CP is generated. Accordingly, when there is a rising transition in the output UDCP of the exclusive NOR gate 306 of FIG. 3, the OR output UD of the exclusive OR / NOR gate 305 of FIG. 3 is a logic level '0' and the third transition. The NOR output (/ UD) of the exclusive OR / NOR gate 305 of 3 degrees becomes the logic level "1".

A case in which the transition position of the clock pulse CP of the voltage controlled oscillator 15 of FIG. 2 is behind the center of the data bit unit interval will be described with reference to FIG. 4B.

The phase difference between the data Q2 re-timed with the in-phase clock pulse CP and the data Q3 re-timed with the reverse phase clock pulse / CP is re-timed. There will be one cycle. Therefore, the phase difference of these two retimed data Q2 and Q3 of the output UD of the exclusive OR of the exclusive OR / NOR gate 305 of FIG. 3 is output at a logic level "1". In addition, the phase difference between the data Q1 retimed with the in-phase clock pulse CP and the data Q3 retimed with the inverse clock pulse / CP is always generated by 1/2 of the clock pulse CP period. Therefore, whenever there is a transition in the input data, the output (UDCP) of the exclusive NOR gate 306 of FIG. 3 re-times the pulses whose logic level pulse width is 1/2 of the clock pulse. This occurs at the center of the data Q2 and Q3.

Thus, when there is a transition in the output (UDCP) of the exclusive NOR gate 306 of FIG. 3, the OR output UD of the exclusive OR / NOR gate 305 of FIG. 3 is a logic level '1' and the The NOR output (/ UD) of the exclusive OR / NOR gate 305 of 3 degrees becomes the logic level '0'.

5 is a circuit diagram of the PFC gain regulator 12 of FIG. 2, where 500 is a shift register, 501 to 504, 506, 511 to 51n are D flip flops, and 505 is an OR gate, respectively.

The PFC gain regulator 12 of FIG. 2 inputs the OR output UD of the exclusive OR / NOR gate 305 (FIG. 3) in the PFC 12 of FIG. 2 as shown in FIG. D flip-flop 501 which uses the output UDCP of the exclusive NOR gate 306 (FIG. 3) of the PFC 12 of FIG. 2 as a clock input, and the exclusive OR / NOR gate 305 of FIG. Of the D flip-flop 502 and the D flip-flops 501 and 502 whose NOR output (/ UD) is a data input and the output (UDCP) of the exclusive NOR gate 306 of FIG. 3 is a clock input. OR gate 505 with positive outputs Q11 and Q12 as input, output DCP of N divider 13 in FIG. 2 as clock inputs, and output of OR gate 505 as data inputs. The D-flop flop 506 with the positive output Q16 as the one input of the OR gate 505 and the clear input of the D-flop flops 501 and 502, and the constant output Q11 of the fraudulent D-flop flop 501 As data input, D flip-flop 503 having the output DCP of the N divider 13 of FIG. 2 as a clock input and the constant output terminal Q13 connected to the first output terminal U of the PFC gain regulator 12 of FIG. The positive output Q12 of the D flip-flop 502 is a data input, and the output DCP of the N-split 13 of FIG. 2 is a clock input, and the constant output terminal Q14 is a PFC of FIG. A D flip-flop 504 connected to the second output terminal D of the gain regulator 12 and a shift register 500 composed of (n) D flip-flops 511 to 51n.

The shift register 500 connects the data input terminal D21 of the D flip flop 511 of the first stage to the positive output terminal Q16 of the D flip flop 506, and the D flip flop 511 of the first stage. The output terminal Q21 is input to the data input terminal of the D flip-flop that follows, and the clock input terminal of the D flip-flop 511 to 5n of each stage is output to the output terminal DCP of the N divider 13 in FIG. The positive output terminal Q2n of the D flip flop 51n of the last stage is connected to the D flip flop 511 to 5in of each stage and the clear terminals CD16 and CD21 to CD2n of the D flip flop 506. do.

The operation description of the PFC gain regulator 12 of FIG. 2 configured as described above is as follows.

If a rising transition occurs in the output signal UDCP input from the PFC 11 of FIG. 2 and the clear terminals CD11 and CD12 of the two D flip-flops 501 and 502 maintain a logic level of '0', One of the two D flip-flops 501 and 502 has a constant output Q of logic level '1'. Later, when a rising transition occurs at the output DCP of the N divider 13 in FIG. 2, the positive output Q16 of the D flip-flop 506 becomes a logic level '1' so that the two D flip-flops ( Clear 501,502).

Since the data input terminal D16 and the constant output terminal Q16 of the D flip-flop 506 are connected to the OR gate 505, the D flip-flop 506 is not cleared by the clear terminal CD. Constant output Q16 maintains logic level '1'. However, the clear terminal CD16 of the D flip flop 506 is connected to the positive output Q2n of the D flip flop 51n at the end of the shift register 500 including n D flip flops 511 to 51n. Since the positive output Q16 of the D flip-flop 506 becomes the logic level "1", after (n) rise transitions occur at the output DCP of the N divider 13 of FIG. The positive output Q16 of the D flip-flop 506 is cleared to a logic level '0'. Since the D flip-flops 501 and 502 are cleared while the positive output Q16 of the D flip-flop 506 is maintained at the logic level "1", the output (UDCP) of the PFC 11 of FIG. Will not operate.

Therefore, even if the rising transition occurs frequently at the output UDCP of the PFC 11 of FIG. 2 (even if a large amount of transition occurs in the input data), the first and second outputs U of the PFC gain adjuster 12 are U. The pulse generation period output from the constant outputs Q13 and Q14 of the D flip-flops 503 and 504, which are D, is limited to a predetermined minimum pulse repetition generation period (T _MIn = (n + 1) x DCP). The pulse width also generates a pulse having one period pulse width of the output DCP of the N divider 13 in FIG. The period of the output DCP of the N divider 13 of FIG. 2 and the number n of the D flip-flops 511 to 51n indicate the bit rate of the input data, the bit pattern, the loop gain of the PLL, and the like. Consideration can be made optimally.

FIG. 6 is a signal waveform diagram of each part of FIG. 5, and in FIG. 5, the number of the D flip-flops (511 to 51n) is three, and the N-divided output (DCP) is the voltage controlled oscillator 915. This is a signal waveform diagram when the clock pulse CP is divided into two clocks.

FIG. 6A shows a signal waveform in which the rising transition of the divided clock pulses of the N divider 13 of FIG. Is also.

FIG. 6 (b) shows a case in which the transition in the data occurs with a probability of 1/2 and the rising transition of the two-divided clock pulses of the N divider 13 of FIG. Signal waveform diagram.

The present invention constructed and operated as described above enables the bit synchronization having a loop gain insensitive to the bit pattern and the bit rate to be substituted for the conventional bit synchronization circuit and has the following effects.

First, since the PLL loop gain of the bit sync circuit changes insignificantly according to the input data bit pattern, even when '0' or '1' is continuous in the data string when it is used for NRZ bit sync without using line cde. Performs bit synchronization.

Second, since the width of the pulse output from the PFC 11 can be freely adjusted, it operates stably even in bit synchronization of high-speed (500Mbps or more) data transmission.

Claims (3)

In the bit synchronization circuit for restoring the clock and data stably at a high bit rate without changing the loop gain of the PLL (Phase Locked Loop) sensitively depending on the bit pattern and bit rate of the binary data to be input; The result of comparing the rising transition of the VCO clock pulse (CP), which is the output of the bit synchronization circuit to which it belongs, is before or after the center of the bit unit interval of the binary data inputted from the outside, Phase and frequency comparison means (Phase and Frequency Comparator; hereinafter referred to as PFC) 11 for outputting a latch clock pulse so that the logic level can be latched at an input data transition point; Connected to the PFC 11, if the phase of the rising transition of the VCO clock pulse (CP) is behind the center of the bit unit interval of the binary input data at the first output terminal (U), if the second output terminal (D) PFC gain adjusting means (12) for generating a pulse at the; Low-pass filter means for low-pass filtering or integrating the voltage (current) difference of the pulses output from the first and second output terminals (U, D) of the PFC gain control means (12) to output a voltage of only the low-frequency component (14); Voltage controlled oscillation means (15) for outputting a clock pulse (CP) whose phase and frequency are changed in accordance with the output voltage of the low pass filtering means (14) to the PFC (11); And N dividing means (13) for dividing a clock pulse (CP) from said voltage controlled oscillating means (15) and outputting it to said PFC gain adjusting means (12). 2. The phase and frequency comparison means (11) according to claim 1, wherein the phase and frequency comparison means (11) has an in-phase clock pulse in phase with the input as a clock (CP) output from the voltage controlled oscillation means (15), and an inverse phase with the input. Receiving means 304 for outputting a clock pulse; A first D flip-flop (301) using a common clock pulse output from the receiving means (304) as a clock input and the binary data as a data input; A second D flip-flop 303 which uses a reverse phase clock pulse output from the receiving means 304 as a clock input and a binary data input from the outside as a data input; A third 3D flip-flop 302 which uses the reverse phase clock pulse output from the receiving means 304 as a clock input and the positive output Q1 of the first D flip-flop 301 as a data input; Exclusive negative OR processing means (306) for inputting positive outputs (Q1, Q3) of the first and second D flip-flops (301,303); And an exclusive-OR and negative-OR processing means (305) for inputting the positive outputs (Q3, Q2) of said second and third 3D flip-flops (303,302). 3. The output according to claim 2, wherein the phase and frequency comparison gain adjusting means (12) is an output UD of the exclusive OR and negative OR processing means 305 as a data input and the output of the exclusive negative OR means 306. 4D flip-flop 501 which uses UDCP as a clock input; The fifth 5D flip-flop 502 of which the exclusive negative OR output (/ UD) is the data input and the output (UDCP) of the exclusive negative OR means 306 is the clock input. ); A sixth D flip-flop 503 for setting the output Q11 of the fourth D flip-flop 501 as a data input and a clock input for the output DCP of the N division means 13; A seventh D flip-flop 504 which uses the positive output Q12 of the fifth 5D flip-flop 502 as a data input and a clock input of the output DCP of the N division means 13; Logical sum processing means (505) for setting the positive outputs (Q11, Q12) of the fourth and fifth D flip-flops (501,502) to two of three inputs; The output of the OR processing means 505 is a data input, the output DCP of the N distributing means 13 is a clock input, and the constant output Q16 is the other input of the OR operation means 505. An eighth D flip-flop 506; And a plurality of D flip-flops 511 to 51n, and each of the positive outputs Q21 to Q2n is input using the positive output Q16 of the eighth D flip-flop 506 as the input of the data input terminal D21. The data input of the D flip-flop, the output (CDP) of the dividing means 13 as the clock input, and the output is the clear input of the plurality of D flip-flops (511 to 51n) and the eighth D-flop flop (506) And a shift register means (500).