KR930015896A - Image Memory System for Interpolation of Subsampling Signals - Google Patents
Image Memory System for Interpolation of Subsampling Signals Download PDFInfo
- Publication number
- KR930015896A KR930015896A KR1019910024481A KR910024481A KR930015896A KR 930015896 A KR930015896 A KR 930015896A KR 1019910024481 A KR1019910024481 A KR 1019910024481A KR 910024481 A KR910024481 A KR 910024481A KR 930015896 A KR930015896 A KR 930015896A
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- interpolation
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- signal
- image memory
- memory system
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Abstract
본 발명은 서브 샘플링된 신호의 보간을 위한 영상 메모리 시스템과 관련된 것으로 종래에는 이러한 메모리 시스템이 IDTV나 EDTV등의 전용 메모리로 설계되어지거나 각 보간신호 데이타를 동시에 융통적으로 얻는데 제약이 있어서 바람직한 것이 못되었으나, 본 발명에선 NTSC의 대역 압축 방식에서 신호보간을 위한 각종 신호의 형태를 저장한 메모리와, 이 메모리로 부터 복수 보간신호를 동시에 얻어낼 수 있도록 각종 보간신호를 저장하고 있는 이것을 홀, 짝수 라인별로 저장시킨 제1-제4 메모리(M1-M4:15-18)와, 이 제1-4 메모리(M1-M4)로 부터 다수 보간신호를 동시에 선별하여 출력할 수 있도록 제어하는 영상메모리 제어부(14)를 일체로 포함한 구성의 서브 샘플링 신호의 보간을 위한 영상 메모리 시스템을 제공하는데 있다.The present invention relates to an image memory system for interpolation of sub-sampled signals. In the related art, such a memory system is designed as a dedicated memory such as IDTV or EDTV, or has limitation in obtaining each interpolation signal data flexibly. However, in the present invention, in the NTSC band compression method, a memory storing various types of signals for signal interpolation, and various interpolation signals are stored so that multiple interpolation signals can be simultaneously obtained from this memory. Controlling so that a plurality of interpolation signals can be simultaneously selected and output from the first to fourth memories M 1 to M 4 : 15-18 and the first to fourth memories M 1 to M 4 . An object of the present invention is to provide an image memory system for interpolating subsampling signals having an integrated image memory control unit (14).
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제1도는 본 발명에 의한 영상 메모리 데이타 구성의 참고도, 제2도는 본 발명에 의한 영상 메모리 회로의 실시예도, 제3도는 제2도와 관련된 영상메모리 제어부의 실시예도, 제4도 (가) 내지 (라)는 본 발명의 시스템 회로에 관련된 동작 타이밍 펄스의 형태를 나타낸 참고도, 제5도는 본 발명의 시스템에서 이용되는 신호의 동작 타이밍챠트.1 is a reference diagram of a video memory data structure according to the present invention, FIG. 2 is an embodiment of an image memory circuit according to the present invention, FIG. 3 is an embodiment of an image memory control unit related to FIG. 2, and FIGS. (D) is a reference diagram showing the form of an operation timing pulse related to the system circuit of the present invention, and FIG. 5 is an operation timing chart of signals used in the system of the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910024481A KR930015896A (en) | 1991-12-26 | 1991-12-26 | Image Memory System for Interpolation of Subsampling Signals |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910024481A KR930015896A (en) | 1991-12-26 | 1991-12-26 | Image Memory System for Interpolation of Subsampling Signals |
Publications (1)
Publication Number | Publication Date |
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KR930015896A true KR930015896A (en) | 1993-07-24 |
Family
ID=67345779
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019910024481A KR930015896A (en) | 1991-12-26 | 1991-12-26 | Image Memory System for Interpolation of Subsampling Signals |
Country Status (1)
Country | Link |
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KR (1) | KR930015896A (en) |
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1991
- 1991-12-26 KR KR1019910024481A patent/KR930015896A/en not_active Application Discontinuation
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