KR930012342U - Priority processing circuit - Google Patents
Priority processing circuitInfo
- Publication number
- KR930012342U KR930012342U KR2019910020621U KR910020621U KR930012342U KR 930012342 U KR930012342 U KR 930012342U KR 2019910020621 U KR2019910020621 U KR 2019910020621U KR 910020621 U KR910020621 U KR 910020621U KR 930012342 U KR930012342 U KR 930012342U
- Authority
- KR
- South Korea
- Prior art keywords
- processing circuit
- priority processing
- priority
- circuit
- processing
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019910020621U KR940003400Y1 (en) | 1991-11-28 | 1991-11-28 | Priority processing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019910020621U KR940003400Y1 (en) | 1991-11-28 | 1991-11-28 | Priority processing circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930012342U true KR930012342U (en) | 1993-06-25 |
KR940003400Y1 KR940003400Y1 (en) | 1994-05-23 |
Family
ID=19323098
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR2019910020621U KR940003400Y1 (en) | 1991-11-28 | 1991-11-28 | Priority processing circuit |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR940003400Y1 (en) |
-
1991
- 1991-11-28 KR KR2019910020621U patent/KR940003400Y1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR940003400Y1 (en) | 1994-05-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
FI924811A (en) | ELECTRONIC INFORMATIONSANSKAFFNINGSSYSTEM | |
DE59105872D1 (en) | Processor circuit. | |
DE69119152D1 (en) | Circuit arrangement | |
DE69317350D1 (en) | Comparison circuit | |
DE69206651D1 (en) | Circuit arrangement | |
DE69213986D1 (en) | Circuit arrangement | |
DE69216663D1 (en) | Circuit | |
DE69208205T2 (en) | Protection circuit | |
KR920015873U (en) | NMOS exclusive Oagate circuit | |
DE69220456T2 (en) | Circuit arrangement | |
DE69317200T2 (en) | Data processing circuit | |
DE69215184D1 (en) | Integrated circuit | |
DE69227657T2 (en) | Photographic processing | |
DE59207876D1 (en) | Photographic processing | |
DE69221455T2 (en) | Centering circuit | |
DK0489194T3 (en) | circuit Event | |
KR930012342U (en) | Priority processing circuit | |
KR930003781U (en) | Priority processing circuit | |
DE59207276D1 (en) | Photographic processing | |
KR920020384U (en) | Dividing circuit | |
KR920015487U (en) | Multiple interrupt processing circuit | |
DE69221943T2 (en) | Chrominance signal processing circuit | |
DE69225519D1 (en) | Chrominance signal processing circuit | |
DE69119363D1 (en) | Hold circuit | |
KR920001355A (en) | Interrupt control processing circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
REGI | Registration of establishment | ||
FPAY | Annual fee payment |
Payment date: 20030417 Year of fee payment: 10 |
|
LAPS | Lapse due to unpaid annual fee |