KR930010484B1 - On screen display apparatus of tv - Google Patents

Abstract

The on screen display generates and displayes characters and diagrams regardless to length or shape. The on screen display includes a size word register (2) for size data of on-screen characters, a horizontal size adjuster (3) for generating horizontal size of character and address of a character storage memory, an oscillator (1) for generating clock signal applied to the horizontal size adjuster (3), a first multiplexer (5) for deciding address of a video RAM (6), a video RAM (6) for reading and writing data on address decided by the first multiplexer (5), a second multiplexer (51) for deciding address of character generating RAM (8) according to output signal of the video RAM and address bus, a character generating RAM (8) for controlling character generation, and a third multiplexer (52) for selecting character generating.

Description

On Screen Display Device

1 is a block diagram of an on-screen display device of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an on screen display device that displays characters on a screen of a video device such as a TV and a VTR. In particular, the programmer can display characters and figures to be displayed on the screen. (Character Generation ROM), on-screen display device that can be displayed regardless of the type of characters prepared in.

In general, an On Screen Display (OSD) device function refers to a function of displaying a character or a figure such as a time or channel number on a screen of a TV and a VRT. In the image processing system incorporating such OSD function, when a control signal for performing a function selected by a programmer is output at the output side of the control signal transmitter, it is received at the control signal receiver. In addition, the microcomputer outputs a control signal such as data and clock for generating on-screen characters to its output side while executing a program by the input control signal, and the on-screen character output unit controls the data clock output from the microcomputer. 'R, G, B' and blanking signals for character display by signals are output to the output side thereof, and the image output section is the R, G, B 'and blanking signals and video signals outputted from the on-screen character output section. The signal output from the processing unit is combined to generate a signal for output on the screen.

In the above system, the OSD device has a configuration difference depending on the function of each product, but basically, a character generation ROM, a video RAM, a column counter, and a row counter. It consists of blocks, such as a counter and an output control part.

The character display method of a conventional OSD device using such an OSD block is described in that character information is encoded in a character generation ROM and a video RAM is used to display a character generation ROM having character information. By storing the address, you display the desired character. That is, the content of the video RAM is the address of the character generating ROM, and the content of the character generating ROM is the character information. Therefore, assuming that the size of the character generating ROM is 64 words, there is no choice but to increase the size of the character generating ROM when more characters are required. However, if the size of the character generating ROM increases, the size of the chip naturally increases, causing a problem of cost increase. In particular, when trying to display the Hangul or Hanja will encounter this difficulty more easily.

As described above, in the MCU (Memory Control Unit) incorporating an OSD chip or an OSD function, the character generation part is configured as a ROM, so that the number and types of displayable characters are ROM. In the case of limiting the capacity of the memory device, if a new character is to be displayed, a problem arises in that a new chip is generated by modifying the ROM content by changing the coding of the ROM.

Accordingly, an object of the present invention is to divide the character generator ROM into a ROM and a RAM to store characters, and to input or output character information to the RAM by a program so that the number of characters that can be expressed by making a new character is programmable. It is an object of the present invention to provide an on-screen display device having unlimited expression ability.

In order to achieve the above object, the present invention is a character generating ROM, a video RAM, a column counter, a row counter, an output control unit in the OSD device, the character generating ROM is composed of a character generating ROM and RAM generally used a lot Character information is stored in the character generation ROM, and new characters or figures are stored in the character generation RAM so that the CPU can directly read or write the contents of the RAM by a program.

Hereinafter, with reference to the accompanying drawings, the configuration, operation, and effects of the present invention will be described in detail.

According to the present invention, a CPU having a data bus and an address bus capable of transmitting data and an address to be displayed on a screen (not shown) and a data bus value of the CPU determine the size of one character to be displayed on the screen. A size word register (2) for storing a value, a horizontal adjuster (3) for generating a horizontal direction size of a character and an address of a storage location according to an input clock signal, and a control unit for controlling the horizontal adjuster (3) An oscillation unit 1 for generating a clock signal, a vertical adjustment unit 2 for generating a vertical size of a character and an address of a storage location according to the input horizontality, contents of the address bus of the CPU and the horizontal vertical adjustment unit A first multiplexer (5) for determining the address of the video RAM (6) by inputting the output signals of (3,4) and a video for inputting / outputting characters through the data bus to the address determined by the first multiplexer (5) RAM 6, The second multiplexer 51 which determines the address of the text generation RAM 8 by the output of the video RAM 6 and the address bus, the text generation ROM 7 storing the text information, and the first multiplexer 51 of the first multiplexer 51. Character generation RAM 8 in which new character information is stored by an output signal and a data bus, a third multiplexer 52 for selectively outputting the character generation ROM / RAM 7, and color of characters are determined. The display controller 10 is configured to control the display of characters on the screen by inputting the output signal of the color word register 9, the third multiplexer 52 and the output signal of the color word register 9.

The horizontal adjuster 3 stores a horizontal size counter 31 for countering an input clock (oscillator clock) and a horizontal position for storing a horizontal position of a character to be displayed on a screen (meaning a position at which display starts). A position register 30, a horizontal position counter 32 for countering the horizontal position of the current scanning line, and a horizontal address counter 33 for countering the horizontal address of the character to be displayed, wherein the vertical adjustment unit 4 A vertical size counter 41 for counting the size of the vertical direction, a vertical position register 40 for storing the vertical position (meaning the position at which display starts) of characters to be displayed on the screen, and a vertical position A vertical position counter 42 for countering, and a vertical address counter 43 for countering the vertical address of the display character.

The size word register 1, the horizontal synchronous signal storage position register 30, the vertical synchronous signal storage register 40, the video RAM 8 and the color word register 9 are controlled by a data bus of the CPU. The first and second multiplexers 5 and 51 are configured to be controlled by the address bus of the CPU.

1 is a block diagram of an on-screen display device according to the present invention, OSCIN, OSCOUT terminal is a terminal for receiving a clock (clock) to know the horizontal axis coordinates of the TV screen and the LC or RC oscillation circuit of about 4-8MHz HSYNC and VSYNC are input terminals for receiving a horizontal synchronization signal and a vertical synchronization signal of the TV, respectively. R, G, and B are red, green, and blue (red, green, blue) meaning character data (character data) is a short sleep, and the output color combination of these three signals determines the color of the character. The BLK terminal is a terminal for blanking the video signal of the TV. When this signal is high, the video signal is not output on the TV screen. Instead, the character information of the three R, G, and B terminals is displayed. do.

In addition, a size word register (2) is a register connected to a data bus and capable of being read / write by a program, and a dot according to the value of the register (2). (dot) size is determined. When the size of a dot is determined, the size of the text is automatically determined, so this register determines the size of the text.

Table-1 shows an example of the size of a dot and a letter that depends on the value of a size word register (2), which means one scanning line of 1H, and is measured by counting horizontal synchronization signals. The number is known. Tdot It means one cycle of clock applied to OSCIN / OSCOUT terminal.

TABLE 1

The horizontal size counter 31, which is a 2-bit counter that clears the dot signal when the horizontal synchronous signal is high, counts the horizontal size while counting when the horizontal synchronous signal is input from the HSYNC terminal. When the value of the counter 31 is equal to the value of the size wonder register 2, the output pulse is output to the horizontal position counter 32, and counting starts again from zero.

The horizontal position counter 32 is cleared when the horizontal synchronization signal is high to count the output pulse of the horizontal size counter 31. At this time, if the value of the horizontal position register 30, which is a 5-bit programmable register that determines the coordinates to start the display in dots, is equal to the value of the horizontal position counter 31, the output becomes high. Then, the display proceeds from this time.

On the other hand, when a vertical synchronous signal is input to the VSYNC terminal, the vertical size counter 41 outputs an output pulse to the vertical position counter 42 when the count value equals the value of the size word register 2 while counting the vertical synchronous signal. Output and count back from zero.

In the vertical position counter 40, the output pulse of the vertical size counter 41 is counted when the vertical synchronization signal is high and cleared when the vertical synchronization signal is low.

The vertical position register 40 is a 5-bit programmable register that determines the coordinates of starting the display in dots.

When the value of the vertical position register 40 and the value of the vertical position counter 42 coincide with each other, the output of the vertical position counter 42 becomes high to enable display.

The horizontal address counter 33 is cleared when the output of the horizontal position counter 32 is zero, and counts the output of the horizontal size counter 31 when the output of the horizontal position counter 32 is high. When this value is 12, the next column address of the video RAM 16 is designated (the address of the next column of characters). The vertical address counter 43 is cleared when the vertical position counter 42 is low, and counts the value of the vertical size counter 41 when it is high. When the count value reaches 18, the video RAM 6 Specify the next row address of the.

Therefore, the contents of the address bus and the output 2 bits of the horizontal structure counter 33 and the output 6 bits of the vertical address counter 43 are combined so that 8 bits are applied to the multiplexer 5 to thereby determine the address of the video RAM 6. The output of the horizontal address counter 33 determines the column address, and the vertical address counter 43 determines the address of the row.

In the video RAM 6, a program can be directly input / output by the CPU through an address bus and a data bus of a CPU (not shown), and the characters to be displayed on the screen can be determined by the program. .

The video RAM 6 is composed of 4 rows x 16 columns, and one word is composed of 8 bits. If the MSB is applied to the multiplexer 52, the character generating ROM 7 is selected and is low. Select the character generator ROM (8). In addition, the output of the video RAM 6 becomes the address of the character generating ROM / RAM (7,8), and the character generating ROM / RAM (7,8) may have 128 words of 12 x 18 bits of data, respectively. have.

However, in the case of the character generating RAM 8, since only 16 words are enough to perform the function, it is composed of 12 × 18 × 16 and receives the address from the video RAM 6 and the address from the CPU address bus. Outputs the address of the character to be represented by the output signal of the multiplexer 51 which muxes the signal, and can directly read / write by a program through the CPU data bus so that new character information can be stored at any time. Therefore, infinite kinds of characters can be represented on the TV screen.

When the output of the character generating ROM / RAM (7, 8) is high, the character should be displayed. Therefore, the character generating ROM or RAM is selected by the output signal of the video RAM 6 and the display controller 10 BLK terminal is selected. Outputs high so that the text signal is displayed on the screen instead of the video signal of the TV. The color of the character is determined by the F, G and B terminals. The values of the R, G, and B terminals are controlled by the output values of the color word register (9), which is a 3-bit programmable register, and the combination of these three terminals (R, G, B) provides eight colors. Can produce

As such, the OSD device of the present invention is capable of representing any character or figure that a programmer wants to display on the screen by a program with a character generating RAM, and is particularly useful when displaying Hangul or Hanja on a screen. It has the advantage of being convenient.

Claims (4)

The CPU having the data bus and address bus for transmitting data and address to be displayed on the screen and the data bus value of the CPU determine the size of one character to be displayed on the screen and store the size word register (2). ), A horizontal control unit 3 for generating a part of the horizontal direction size of the character and an address of the character storage place, an oscillator 1 for generating a clock signal for controlling the horizontal control unit 3, and a character. The vertical control unit 4 which generates a part of the address of the vertical direction size and the character storage location of the video bus, and the contents of the address bus and the output signals of the horizontal control unit and the vertical control unit 3, 4 A first multiplexer (5) for determining an address of (6), a video RAM (6) for inputting and outputting characters through a data bus to an address determined by the first multiplexer (5), and an output of the video RAM (6); Text generation by address bus Character generation in which character generation is controlled by a second multiplexer 51 for determining the address of (8), a character generation ROM 7 in which character information is stored, and an output signal and a data bus of the first multiplexer 51; RAM 8, a third multiplexer 52 for selectively outputting to the character generating ROM / RAM 7, 8, a color word register 9 for determining the color of a character, and the third multiplexer 52 An on-screen display device comprising a display controller (10) for controlling the display of characters on a screen by inputting the output signal of the color word register and the output signal of the color word register (9). 2. The horizontal adjusting unit (2) according to claim 1, wherein the horizontal adjusting unit (2) includes a horizontal size counter (41) for countering the horizontal size of a character, a horizontal position register (30) for storing a horizontal position at which character display starts, and horizontality of a scanning line An on-screen display device comprising: a horizontal position counter (32) for counting a clock to know a position; and a horizontal address counter (33) for counting a horizontal address. 2. The vertical adjustment unit (4) according to claim 1, wherein the vertical adjustment unit (4) has a vertical size counter (41) for countering the vertical size of a character, a vertical position register (40) for storing a vertical position at which character display starts, and horizontal And a vertical position counter (42) for counting a synchronous signal to indicate a horizontal position of the current scanning line, and a vertical address counter (43) for counting a vertical address. The size word register (1), the horizontal position register (30), the vertical position register (40), the video RAM (6), and the character generating RAM (8) according to any one of claims 1, 2 and 3. And the color word register (9) is controlled by the data bus of the CPU, and the first and second multiplexes (5, 51) use the address bus of the CPU as one input.