KR930009183B1 - Motion display circuit of digital tv - Google Patents

Abstract

The circuit for controlling tracks of image motion in digital T.V comprises: a frame memory for storing a frame of brightness signal and color signal, a control signal generator for making horizontal synchronous signal and clock signal and generating control signal for said frame memory, and a color signal output means for providing color signal to CRT, after converting data of said frame memory to said analog signal. Thus this invention provides the function for tracing tracks of image motion and as the result a more dynamic screen for user.

Description

Motion trace display circuit of digital television receiver

1 is a video signal processing block diagram of a general digital television receiver.

2 is a block diagram showing the motion trajectory of the present invention.

3 (a) to 3 (c) are explanatory views showing an example of displaying a motion trajectory by the present invention.

* Explanation of symbols for main parts of the drawings

1A-1D: Frame memory 2: Control signal generator

3: color signal generator 4: comparison circuit

5: Light Enable Control Unit CPT: Color Picture Tube

AD1: AND gate ND1: NAND gate.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reproducing the trajectory of a moving object at a slow speed in a digital television receiver, and more particularly, to a motion trajectory display circuit of a digital television receiver suitable for observing a fast moving object in detail in sports broadcasting. .

FIG. 1 is a block diagram of a video signal processing of a general digital television receiver. As shown therein, a frame memory 1A-1C for storing a luminance signal Y, a color difference signal RY, and BY for one frame, respectively. And a control signal for generating a clock signal in phase with the horizontal synchronization signal Hsyn and generating various control signals of the frame memories 1A-1C using the horizontal synchronization signal Hsyn and the vertical synchronization signal Vsyn. The generation unit 2 and the data read from the frame memories 1A-1C are converted into analog signals, and the red signal R, the green signal F, and the blue signal B are converted into analog signals. It is composed of a color signal output unit (3) for extracting and outputting the same to the color picture tube (CPT).

The control signal generator 2 is connected to the flicker clock signal SCK while the luminance signal Y, the color difference signal RY, and BY, which have been processed as digital signals, are respectively provided to the frame memories 1A-1C. The read / write signals having the same period are supplied to the frame memories 1A-1C. Accordingly, the open dress count value of the counter built in the frame memories 1A-1C is increased, and the open dress reset signal is generated from the moment when the horizontal synchronization signal Hsyn is inputted to the control signal generator 2. While the open address of the frame memories 1A-1C becomes Φ, the counter value of the row address is increased by one, and the row address counter is reset to Φ every time the vertical sync signal Vsyn of the even field is generated. As a result, the contents of the address stopped by the row / column address counter are read and rewritten every one clock of the read / ride signal. Is activated at low potential, new data is written to the frame memories 1A-1C, and if not inactive at high potential, unstored data is read. However, the above write enable signal ( ) Is finally determined by the still picture control signal. Therefore, when it is stopped, the luminance signal Y, the color difference signal RY, and BY are sequentially stored in the frame memories 1A-1C when the control signal SCS is at low potential. Are stored, read and displayed on the color picture tube (CPT).

On the other hand, if the still picture control signal SCS is given at high potential, it is impossible to write a new luminance signal Y and color difference signals RY, BY in the frame memories 1A-1C, while already storing the memory. The contents are read repeatedly and a still image appears on the color picture tube CP.

However, in such a conventional circuit, only a still image can be displayed, and a function of displaying a motion trajectory at a slow speed is not provided. Therefore, when a viewer wants to observe an object moving at a high speed in detail, it cannot be displayed. There was a fault.

The present invention has been devised to display the trajectory of a fast moving object at a slow speed in order to solve this problem, which will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a moving trajectory display circuit of a digital television receiver according to the present invention. As shown therein, a frame memory for storing luminance signals Y, color difference signals RY, and BY for one frame, respectively, is shown. 1A-1C, a horizontal synchronizing signal Hsyn, and a vertical synchronizing signal Vsyn are input to generate a clock signal in synchronism with the horizontal synchronizing signal Hsyn, and using the frame memory 1A-1C. The data read from the frame memory 1A-1C is converted into analog data using a control signal generator 2 for generating various control signals, and a sampling clock signal (SCK) input from the control signal generator 2. After converting to a signal, a still image composed of a color signal output unit 3 which extracts a red signal R, a green signal G, and a blue signal B and supplies it to a color picture tube CPT. In digital television receiver circuit, newly input one frame When the frame memory 1D storing the luminance signal Y for one minute and the luminance signal Yf delayed by one frame and the luminance signal Y currently input through the frame memory 1D are compared with each other, And a comparator circuit 4 for outputting a signal, and an AND gate AD1 and a NAND gate ND1 to control write enable of the frame memory 1D, and output signal CCS of the comparator circuit 4. And logically combining the motion trajectory display control circuit MCS and the still image control signal SCS to control the write enable WE of the frame memories 1A-1C so that the motion trajectory hints are read from them. The operation and effects of the present invention configured as the light enable control unit 5 will be described in detail with reference to FIG. 3 as follows.

Write enable terminal of the frame memory (1A-1C) The luminance signal Y is written to the flame memories 1A and 1D while the low potential is applied to the?, And the color difference signals RY and BY are written to the frame memories 1B and 1C, respectively. do.

On the other hand, the still picture control signal (SCS) and the motion trajectory display control signal (MCS) are supplied to the light enable control unit 5 from a processor (not shown in the figure) built in the television receiver, and these signals are supplied to the viewer's movement. It depends on the function of trajectory display / stop screen function.

When a viewer's motion trajectory sound request is input to the processor by a remote control or an operation switch, the motion trajectory display control signal MCS and the still picture control signal SCS are output from the high potential.

Accordingly, the write enable terminal of the frame memory 1D ( Is applied to the frame memory 1D, so that a new luminance signal Y cannot be written to the frame memory 1D. However, at this time, the comparison circuit 4 compares the luminance signal of the previous frame applied from the frame memory 1D with the luminance signal Y currently input, and outputs a high potential every time, which is the NAND gate ND1. NAND and the high-potential motion trajectory display control signal (MCS), the low potential is output from the NAND gate (ND1) at each time, the still image control signal (SCS) is in a high potential inactive (Inactive) state As a result, new contents (Y, RY, BY) are written to the flame memories 1A-1C at every high potential output in the comparison circuit 4. That is, the contents of the frame memories 1A-1C only change in portions where the luminance signals Y that are input differ.

3 is a diagram showing an example of displaying a motion trajectory according to the present invention. The motion trajectory display control signal MCS is assumed to be in a high potential state as follows.

When video signals such as (a) are sequentially input, the ball appears to move from the left to the right of the screen.

When the motion trajectory display control signal MCS becomes high potential, new contents are not recorded in the frame memory 1D, and the contents of the previous frame remain as shown in (b).

Since the comparison circuit 4 outputs the high potential only at different portions of the above (a) and (b), the screen is displayed as shown in (c). As a result, the original image is an object moving from the left side to the right side of the screen as shown in (a). When the motion trace display function is applied, the trajectory of the moving object is displayed as shown in (c).

As described in detail above, the present invention has an advantage of providing a more dynamic screen to the viewer by adding a frame memory and a comparison circuit to the existing still picture circuit so as to display a motion trajectory.

Claims (1)

Comparing the luminance signal Y currently input to the comparison circuit 4 with the luminance signal Yf of the previous frame previously stored in the frame memory 1D, the high potential is output only at different portions, and the frame memory 1A- 1C) Write enable signal ( And a video signal is stored in the frame memories (1A-1C) so as to display the motion trajectory.