KR930008646A - Personal computer serial communication interface - Google Patents

Personal computer serial communication interface Download PDF

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Publication number
KR930008646A
KR930008646A KR1019910018856A KR910018856A KR930008646A KR 930008646 A KR930008646 A KR 930008646A KR 1019910018856 A KR1019910018856 A KR 1019910018856A KR 910018856 A KR910018856 A KR 910018856A KR 930008646 A KR930008646 A KR 930008646A
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KR
South Korea
Prior art keywords
channel
serial communication
mpsc
output
ctl
Prior art date
Application number
KR1019910018856A
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Korean (ko)
Inventor
박재민
Original Assignee
정용문
삼성전자 주식회사
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Publication date
Application filed by 정용문, 삼성전자 주식회사 filed Critical 정용문
Priority to KR1019910018856A priority Critical patent/KR930008646A/en
Publication of KR930008646A publication Critical patent/KR930008646A/en

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Abstract

직렬 통신 인터페이스(Serial Communication Interface), 회로에 관한 것으로, 특히 MPSC(Multi-protocol Serkal Cmtroller)를 이용한 직렬 통신 제어기에 관한 것이다.Serial communication interface (Serial Communication Interface), and a circuit, in particular relates to a serial communication controller using a multi-protocol Serkal Cmtroller (MPSC).

상기 MPSC를 이용한 통신 제어기는 PC/AT 시스템에 접속되어 입출력 신호를 접속하는 PC/AT 버스로부터 출력되는 어드레스와 콘트롤 신호를 디코딩하여 제어신호를 출력하는 CTL-L과, 상기 PC/AT 버스 입출력되는 데이터를 버퍼링하는 버퍼를 가지고 있다. 그리고 상기 CTL-L과 버퍼에는 A, B 두 개의 송수신 채널을 가지고 있으며, 상기 CTL-L의 출력 제어에 의해 A 채널의 송수신 DMA 요구신호와 B채널의 송수신 요구신호를 발생함과 동시에 상기 버퍼를 통한 데이터를 A채널/B채널로 송수신하는 MPSC가 접속 구성된다.The communication controller using the MPSC is connected to a PC / AT system, the CTL-L to decode the address and the control signal output from the PC / AT bus to connect the input / output signal and output the control signal, and the PC / AT bus It has a buffer to buffer the data. In addition, the CTL-L and the buffer have two transmit and receive channels A and B. The output control of the CTL-L generates the transmit / receive DMA request signal of the A channel and the transmit / receive request signal of the B channel, and the buffer is simultaneously transmitted. An MPSC for transmitting and receiving data through the A / B channels is connected.

상기와 같이 MPSC를 이용한 통신 제어기는 2개의 직렬 통신 채널에서 DMA 요구신호를 발생함으로서, 직렬 통신을 보다 효율적으로 할 수 있다.As described above, the communication controller using the MPSC generates the DMA request signals in two serial communication channels, thereby making serial communication more efficient.

Description

퍼스널 컴퓨터의 직렬 통신 인터페이스Personal computer serial communication interface

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 2 도는 본 발명에 따른 직렬 통신 인터페이스 회로도.2 is a serial communication interface circuit diagram according to the present invention.

Claims (1)

퍼스널 컴퓨터의 직렬 통신 인터페이스에 있어서, PC/AT 시스템에 접속되어 입출력 신호를 접속하는 PC/AT 버스(10)와, 상기 PC/AT 버스(10)를 통한 어드레스와 콘트롤 신호를 디코딩하여 제어신호를 출력하는 CTL-L(21)과, 상기 PC/AT 버스(10)로 입출력되는 데이터를 버퍼링하는 버퍼(44)와, A, B 두 개의 송수신 채널을 가지고 있으며, 상기 CTL-L(21)의 출력 제어에 의해 A 채널의 송수신 DMA 요구신호와 B채널의 송수신 요구신호를 발생함과 동시에 상기 버퍼(44)를 통한 데이터를 A채널/B채널로 송수신하는 MPSC(54)와 상기 CTL-L(20)의 제어신호와 버피(44)의 출력에 의해 소정주기의 전송 클럭율 상기 MPSC(54)로 제공하고, 타임베이스 인터럽트 신호를 상기 PC/AT 시스템으로 제공하는 PIT(46)와, 상기 MPSC(56)의 A채널에 접속되어 외부와의 통신을 행하는 제1데이터 송수신부(22)와, 상기 MPSC(56)의 B채널에 접속되어 외부와의 통신을 행하는 제2데이터 송수신부(24)로 구성함을 특징으로 하는 회로.In the serial communication interface of a personal computer, a PC / AT bus 10 connected to a PC / AT system to connect an input / output signal and an address and control signal through the PC / AT bus 10 are decoded to control a control signal. A CTL-L 21 for outputting, a buffer 44 for buffering data input / output to the PC / AT bus 10, and two transmission / reception channels A and B, and the CTL-L 21 The MPSC 54 and the CTL-L (transmitting / receiving request signal of the A channel and the B channel transmitting / receiving request signal of the A channel and the data transmitted through the buffer 44 to the A channel / B channel by the output control. A PIT 46 for providing a transmission clock rate of the predetermined period to the MPSC 54 by the control signal of 20 and the output of buffy 44, and providing a timebase interrupt signal to the PC / AT system; The first data transmission / reception unit 22 connected to the A-channel of 56 to communicate with the outside, and And a second data transmission / reception unit (24) connected to the B channel of the MPSC (56) to communicate with the outside. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910018856A 1991-10-25 1991-10-25 Personal computer serial communication interface KR930008646A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910018856A KR930008646A (en) 1991-10-25 1991-10-25 Personal computer serial communication interface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910018856A KR930008646A (en) 1991-10-25 1991-10-25 Personal computer serial communication interface

Publications (1)

Publication Number Publication Date
KR930008646A true KR930008646A (en) 1993-05-21

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ID=67348806

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910018856A KR930008646A (en) 1991-10-25 1991-10-25 Personal computer serial communication interface

Country Status (1)

Country Link
KR (1) KR930008646A (en)

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